KR100961946B1 - A vertically aligned mode liquid crystal display - Google Patents

A vertically aligned mode liquid crystal display Download PDF

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Publication number
KR100961946B1
KR100961946B1 KR20030030195A KR20030030195A KR100961946B1 KR 100961946 B1 KR100961946 B1 KR 100961946B1 KR 20030030195 A KR20030030195 A KR 20030030195A KR 20030030195 A KR20030030195 A KR 20030030195A KR 100961946 B1 KR100961946 B1 KR 100961946B1
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South Korea
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electrode
formed
substrate
data line
wiring
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KR20030030195A
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Korean (ko)
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KR20040097765A (en
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김동규
백승수
신애
탁영미
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삼성전자주식회사
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    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1337Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133707Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1343Electrodes
    • G02F1/134309Electrodes characterised by their geometrical arrangement
    • G02F1/134336Matrix
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/137Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells characterised by the electro-optical or magneto-optical effect, e.g. field-induced phase transition, orientation effect, guest-host interaction or dynamic scattering
    • G02F1/139Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells characterised by the electro-optical or magneto-optical effect, e.g. field-induced phase transition, orientation effect, guest-host interaction or dynamic scattering based on orientation effects in which the liquid crystal remains transparent
    • G02F1/1393Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells characterised by the electro-optical or magneto-optical effect, e.g. field-induced phase transition, orientation effect, guest-host interaction or dynamic scattering based on orientation effects in which the liquid crystal remains transparent the birefringence of the liquid crystal being electrically controlled, e.g. ECB-, DAP-, HAN-, PI-LC cells

Abstract

Gate lines and data lines are formed on the first substrate, and pixel electrodes and thin film transistors, which are divided into a plurality of small regions by the first cutouts, are formed in the pixel regions defined by the intersections. On the second substrate facing the first substrate, a common electrode having a first cutout and a second cutout for dividing the pixel electrode into small regions and an opening overlapping the data line are formed. Thus, by forming a plurality of openings separately from the second incision, the load of the signal transmitted through the data line is reduced, the amount of change in the liquid crystal capacitance applied to the data line is reduced, and the light leakage caused by the side crosstalk is reduced, Opening ratio can be increased
Liquid Crystal Display, Vertical Orientation, Opening, Small Domain, Common Electrode

Description

Vertically oriented liquid crystal display {A VERTICALLY ALIGNED MODE LIQUID CRYSTAL DISPLAY}

1 is a layout view of a thin film transistor substrate for a liquid crystal display according to a first exemplary embodiment of the present invention.

2 is a layout view of a color filter substrate for a liquid crystal display device according to a first embodiment of the present invention;

3 is a layout view of a liquid crystal display according to a first exemplary embodiment of the present invention;

4 is a cross-sectional view taken along line IV-IV ′ of FIG. 3,

5 is a layout view illustrating a structure of a liquid crystal display including a thin film transistor array panel according to a second exemplary embodiment of the present invention.

FIG. 6 is a cross-sectional view of the liquid crystal display of FIG. 5 taken along the line VI-VI '. FIG.

121 gate line, 123 gate electrode,

171 data lines, 173 source electrodes,

175 drain electrodes, 190 pixel electrodes,

191, 192, 193 incisions, 151, 153 amorphous silicon layer,

270 reference electrode, 279 opening

The present invention relates to a vertical alignment mode liquid crystal display device, and more particularly, to a vertical alignment mode liquid crystal display device that realizes a wide viewing angle by dividing a pixel region into a plurality of small domains using domain dividing means.

In general, a liquid crystal display device injects a liquid crystal material between an upper display panel on which a reference electrode and a color filter are formed, and a lower display panel on which a thin film transistor and a pixel electrode are formed. By applying a different potential to form an electric field to change the arrangement of the liquid crystal molecules, and through this to control the light transmittance is a device that represents the image.

Among them, the vertical alignment mode liquid crystal display in which the long axis of the liquid crystal molecules are arranged perpendicular to the upper and lower substrates without an electric field is applied, and thus, the contrast ratio is large and the wide viewing angle is easily realized.

Means for implementing a wide viewing angle in a vertical alignment mode liquid crystal display include a method of forming an incision pattern on the electrode and a method of forming protrusions. All of these are methods of securing a wide viewing angle by forming a fringe field to evenly distribute the tilting direction of the liquid crystal in four directions. Among these, the patterned vertically aligned (PVA) mode, which forms an incision pattern on the electrode, is recognized as a wide viewing angle technology that can replace the In Plane Switching (IPS) mode.

In addition, the PVA mode has relatively fast response characteristics compared to the twisted nematic (TN) method because the liquid crystal molecules do not twist and move only by elasticity that is splayed or bent in a direction perpendicular to the electric field direction.

However, a plurality of wirings are formed on the thin film transistor array panel of the liquid crystal display such as a gate line for transmitting a scan signal and a data line for transmitting an image signal. Has capacitance. This self-resistance and capacitance act as a load on each wiring and distort the signal transmitted through the wiring through RC delay. In particular, the coupling between the data line and the common electrode drives the liquid crystal molecules positioned between the two to induce light leakage around the data line, thereby degrading the image quality and widening the black matrix to block such light leakage. It causes a decrease in the aperture ratio.

The technical problem to be achieved by the present invention is to reduce the load on the data line to improve the image quality.

Another object of the present invention is to reduce the capacitance caused by the coupling between the data line and the reference electrode to reduce light leakage around the data line.

In order to solve this problem, the present invention forms an opening in an area of the common electrode overlapping the data line.

In more detail, the liquid crystal display according to the exemplary embodiment of the present invention is formed for each pixel region defined by the first wiring, the second wiring insulated from the first wiring, and the first wiring and the second wiring crossing each other. A first domain having a pixel electrode, a first wiring, a second wiring, and a thin film transistor connected to the pixel electrode divided into a plurality of small portions by a first domain dividing means, the first substrate and the first substrate facing each other; And second domain dividing means for dividing the pixel electrode into a plurality of small domains along with the dividing means, and a second substrate having a common electrode having an opening which is separated from the second domain dividing means and overlaps the second wiring. .

The first domain dividing means is an incision that the pixel electrode has, and the second domain dividing means is an incision that the common electrode has.

At this time, the width of the common electrode located between the second domain dividing means and the opening is preferably in the range of 3-6 μm.

According to another exemplary embodiment, a liquid crystal display device extends in a horizontal direction and faces a gate line having a gate electrode, a gate insulating film formed on the gate line, a semiconductor layer formed on the gate insulating film on the gate electrode, and a gate electrode. A first substrate and a first substrate including a pixel electrode having a source electrode, a drain electrode, and a source electrode, the data line crossing the gate line, and the drain electrode and having a first cutout for dividing and aligning liquid crystal molecules. A second incision facing the first incision and separated from the second incision and the second incision for dividing and aligning the liquid crystal molecules, and having a common electrode having an opening extending along the data line on the data line. It includes a substrate.                     

The storage substrate may further include a storage electrode line formed on the first substrate in the same layer as the gate line and overlapping the pixel electrode to form a storage capacitor.

At this time, it is preferable that the openings are arranged to be separated into at least two or more along the data line, and the width of the common electrode between the second cutout and the opening and the adjacent openings is preferably in the range of 3-6 μm.

The semiconductor device may further include an ohmic contact formed between the data line and the drain electrode, and the semiconductor layer and the ohmic contact may be formed along the data line and the drain electrode.

In this case, the semiconductor layer except for the channel region of the thin film transistor may have the same planar shape as the data line and the drain electrode.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.                     

Next, a structure of a liquid crystal display according to an exemplary embodiment of the present invention will be described with reference to the drawings.

1 is a layout view of a thin film transistor array panel for a liquid crystal display according to a first embodiment of the present invention, FIG. 2 is a layout view of a color filter display panel for a liquid crystal display according to a first embodiment of the present invention, and FIG. 4 is a layout view of a liquid crystal display according to a first exemplary embodiment, and FIG. 4 is a cross-sectional view of the liquid crystal display of FIG. 3 taken along the line IV-IV '.

The liquid crystal display device is formed of a liquid crystal molecule that is formed between the thin film transistor array panel 100 on the lower side and the upper opposing display panel 200 facing them, and is substantially perpendicular to the two display panels 100 and 200. It consists of a liquid crystal layer 300 including a 310.

The thin film transistor array panel 100 formed of a transparent insulating material such as glass is made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), and includes a pixel electrode having cutouts 191, 192, and 193. 190 is formed, and each pixel electrode 190 is connected to a thin film transistor to receive an image signal voltage. In this case, the thin film transistor is connected to the gate line 121 for transmitting the scan signal and the data line 171 for transmitting the image signal, respectively, to turn on and off the pixel electrode 190 according to the scan signal. . The lower polarizer 12 is attached to the bottom surface of the thin film transistor array panel 100. Here, the pixel electrode 190 may not be made of a transparent material in the case of a reflective liquid crystal display, and in this case, the lower polarizer 12 is also unnecessary.

The opposing display panel 200 made of a transparent insulating material such as glass also has a black matrix 230 to prevent light leakage from the edge of the pixel, a color filter 240 of red, green, and blue, and a transparent conductive material such as ITO or IZO. The reference electrode 270 made of a material is formed. Here, the cutouts 271, 272, and 273 and the openings 279 are formed in the reference electrode 270. The black matrix 230 may be formed not only in the peripheral portion of the pixel area but also in the portion overlapping the cutouts 271, 272, and 273 of the reference electrode 270. This is to prevent light leakage caused by the cutouts 271, 272, and 273.

The liquid crystal display according to the first embodiment will be described in more detail.

In the thin film transistor array panel 100, the gate line 121 is formed on the lower insulating substrate 110 in a horizontal direction. The gate electrode 123 is formed in the form of a protrusion on the gate line 121, and a portion 125 positioned near one end of the gate line 121 transmits a gate signal from the outside to the gate line 121. . The storage electrode line 131 is formed on the insulating substrate 110 in parallel with the gate line 121. The storage electrode line 131 is connected to two storage electrodes 133a and 133b formed in the vertical direction, and the two storage electrodes 133a and 133b are connected to each other by the horizontal storage electrode 133c. At this time, two or more sustain electrode lines 131 may be provided. The gate line 121, the gate electrode 123, the storage electrode line 131, and the storage electrode 133 are formed of a metal such as aluminum or chromium. At this time, they may be formed as a single layer, or may be formed as a double layer formed by successively laminating a chromium layer and an aluminum layer. In addition, a variety of metals may be used to form the gate wiring and the common wiring.

The gate insulating layer 140 made of silicon nitride (SiNx) or the like is formed on the gate line 121, the storage electrode line 131, and the storage electrodes 133a and 133b.

The data line 171 is formed in the vertical direction on the gate insulating layer 140. A source electrode 173 is formed in the data line 171 as a branch, a drain electrode 175 is formed adjacent to the source electrode 173, and is located near one end of the data line 171. ) Transfers an image signal from the outside to the data line 171. In addition, a leg metal piece 172 overlapping the gate line 121 is formed on the gate insulating layer 140. The data line 171, the drain electrode 175, and the leg metal piece 172 are also formed of a conductive film containing a conductive material such as chromium and aluminum, similarly to the gate line 121. It can also be formed in a single layer or multiple layers.

An amorphous silicon layer 151, which is used as a channel portion of the thin film transistor, is formed under the source electrode 173 and the drain electrode 175, and the channel portion amorphous silicon layer 151 is also vertically disposed under the data line 171. Long connection. Resistive contact members 163 and 165 are formed on the amorphous silicon layer 151 to reduce contact resistance between the source and drain electrodes 173 and 175 and the channel portion amorphous silicon layer 151. The contact member 163 also extends below the data line 171 and uses amorphous silicon doped at high concentration with n-type impurities.

On the data line 171 or the like, a protective film 180 made of an inorganic insulating material such as silicon nitride or an organic insulating material such as resin is formed. A contact hole 185 exposing the drain electrode 175 is formed in the passivation layer 180.

The pixel electrode 190 having the cutouts 191, 192, and 193 is formed on the passivation layer 180. The pixel electrode 190 is formed using a transparent conductor such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductor having excellent light reflection characteristics such as aluminum (Al). The cutouts 191, 192, and 193 formed in the pixel electrode 190 may be divided into the horizontal cutout 192 formed in the horizontal direction at a position that half-divides the pixel electrode 190. And diagonal openings 191 and 193 formed in diagonal directions, respectively. At this time, the upper and lower diagonal openings 191 and 193 are perpendicular to each other. This is to evenly distribute the direction of the fringe field in four directions.

In addition, a storage wiring connecting bridge 91 is formed on the same layer as the pixel electrode 190 to connect the storage electrode 133a and the storage electrode line 131 of the pixels adjacent to each other across the gate line 121. The storage wiring connecting leg 91 is in contact with the storage electrode 133a and the storage electrode line 131 through the contact holes 183 and 184 formed over the passivation layer 180 and the gate insulating layer 140. The sustain wiring connection leg 91 overlaps the leg metal piece 172, and these may be electrically connected to each other. The sustain wiring connection leg 91 serves to electrically connect the entire sustain wiring on the lower substrate 110. Such a maintenance wiring can be used to repair a defect of the gate line 121 or the data line 171, if necessary, and the leg metal piece 172 can be used to check the laser line for the repair. It is formed to assist the electrical connection of the retaining wire connecting bridge (91).

The gate contact assistant member 95 and the data contact assistant member 97 are formed on the passivation layer 180. The gate contact auxiliary member 95 is connected to the end portion 125 of the gate line through a contact hole 182 formed over the passivation layer 180 and the gate insulating layer 140. It is connected to the end portion 179 of the data line through a contact hole 183 formed in the passivation layer 180.

The opposing display panel 200 has a black matrix 230 formed on the upper insulating substrate 210 to prevent light leakage from the pixel edge. The red, green, and blue color filters 240 are formed on the black matrix 230. The planarization layer 250 is formed on the entire surface of the color filter 230, and the reference electrode 270 having the cutouts 271, 272, and 273 and the openings 279 is formed thereon. The reference electrode 270 is formed of a transparent conductor such as ITO or indium zinc oxide (IZO).

The cutouts 271, 272, and 273 of the reference electrode 270 sandwich the diagonal openings 191 and 193 of the pixel electrode 190 in the center thereof, and are parallel to the diagonal line and the sides of the pixel electrode 190. It includes a refractive portion. At this time, the refraction portion is classified into a longitudinal refraction portion and a horizontal refraction portion. In addition, a plurality of openings 279 are formed in the reference electrode 270 corresponding to the data line 171 along the data line 171. In this case, the spacing b between the opening 279 and the longitudinal refractions of the cutouts 271, 271, and 273 and the spacing a between the openings 279 adjacent to each other on the upper portion of the data line 171 are manufactured. It is preferable that the process is wider than the resolution of the exposure machine used in the photolithography process, and it is preferable that it is usually 3-6 μm or more. This structure is defined as the spacing b between the opening 279 and the longitudinal refractions of the cutouts 271, 271 and 273 and the spacing a between the openings 279 adjacent to each other on the top of the data line 171. By connecting the reference electrode 270, a path of the reference voltage applied to the reference electrode 270 may be secured in various directions.

In the same structure as that of the exemplary embodiment of the present invention, an opening 279 is formed in the reference electrode 270 overlapping the data line 171 to minimize delay with respect to the data signal transmitted to the data line. Can improve. In addition, the capacitance caused by the coupling between the data line 171 and the reference electrode 270 may be reduced to minimize light leakage occurring around the data line 171.

When the thin film transistor substrate and the color filter substrate having the above structure are aligned and combined, and a liquid crystal material is injected and vertically aligned therebetween, the basic structure of the liquid crystal display according to the present invention is provided. When the thin film transistor substrate and the color filter substrate are aligned, the cutouts 191, 192, and 193 of the pixel electrode 190 and the cutouts 271, 272, and 273 of the reference electrode 270 have a plurality of small domains. Divide into These small domains are classified into four types according to the average major axis direction of the liquid crystal molecules located therein.

Next, a method of manufacturing a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention having such a structure and effects will be described.

First, a conductive film including Cr or Mo alloy or aluminum having excellent physicochemical properties is deposited on the substrate 110, and then patterned by a photolithography process using a mask to form the gate line 121 and the sustain electrodes 133a and 133b. And the sustain electrode line 131.

Next, three layers of a gate insulating layer 140 made of silicon nitride, an amorphous silicon layer, and a doped amorphous silicon layer are successively stacked, and the amorphous silicon layer and the doped amorphous silicon layer are patterned together by a photolithography process using a mask to form a gate. The semiconductor layer 151 and the ohmic contact layer thereon are formed on the gate insulating layer 140 on the electrode 123 (second mask).

Next, a conductive film such as Cr or Mo alloy or aluminum or aluminum alloy is deposited and patterned by a photolithography process using a mask to be connected to the data line 171 and the data line 171 crossing the gate line 121 to be connected to the gate electrode. The source electrode 173 and the source electrode 173 extending to the upper portion of the upper part 121 are separated from the source electrode 173, and the drain electrode 175 facing the source electrode 173 is formed around the gate electrode 121.

Subsequently, the doped amorphous silicon layer not covered by the data line 171 and the drain electrode 175 is etched to complete the ohmic contacts 163 and 165 positioned at both sides of the gate electrode 123. The semiconductor layer 151 between the doped amorphous silicon layers 163 and 165 is exposed. Subsequently, in order to stabilize the surface of the exposed semiconductor layer 151, it is preferable to perform oxygen plasma.

Next, an a-Si: C: O film or a-Si: O: F film is grown by chemical vapor deposition (CVD), an inorganic insulating film such as silicon nitride, or an organic insulating film such as an acrylic material is coated The passivation layer 180 is formed. In this case, in the case of a-Si: C: O film, SiH (CH 3 ) 3 , SiO 2 (CH 3 ) 4 , (SiH) 4 O 4 (CH 3 ) 4 , and Si (C 2 H 5 O 4 ) is used as a basic source, and is deposited while flowing a gas mixed with an oxidant such as N 2 O or O 2 and Ar or He. In the case of an a-Si: O: F film, vapor deposition is performed while flowing a gas containing O 2 added to SiH 4 , SiF 4, or the like. At this time, CF 4 may be added as an auxiliary source of fluorine.

Subsequently, the passivation layer 180 is patterned together with the gate insulating layer 140 by a photolithography process to expose the end portions 125, the drain electrodes 175, and the end portions 179 of the data lines 181 and 182. , 183). Here, the contact holes 181, 182, and 183 may be formed in an angled or circular shape, and the area of the contact holes 125 and 179 exposing the pads 125 and 179 may not exceed 2 mm × 60 μm. It is preferable that it is 0.5 mm x 15 micrometers or more, and it is preferable that the side walls of the contact holes 181, 182, and 183 have a tapered structure.

Next, an end portion 125 of the gate line 125 is formed through the pixel electrode 190 and the contact holes 182 and 183 connected to the drain electrode 175 through the contact hole 181 by depositing and etching an ITO or IZO film. And a gate contact auxiliary member 95 and a data contact auxiliary member 97 respectively connected to the end portion 179 of the data line. It is preferable to use nitrogen as the gas used in the pre-heating process before laminating ITO or IZO. This is to prevent the metal oxide film from being formed on top of the metal film exposed through the contact holes 181, 182, and 183.

5 and 6 will be described in detail with respect to the structure of the liquid crystal display device including a thin film transistor array panel according to a second embodiment of the present invention.

5 is a layout view illustrating a structure of a liquid crystal display including a thin film transistor array panel according to a second exemplary embodiment of the present invention, and FIG. 6 is a cross-sectional view taken along line VI-VI ′ of the liquid crystal display of FIG. 5. to be.

5 and 6, in the thin film transistor array panel, the gate line 121 extending in the horizontal direction and the data line 171 extending in the vertical direction cross each other to define a pixel area, and each pixel area includes a thin film transistor and a thin film transistor. The pixel electrode 190 having the cut patterns 191, 192, 193, 194, 195, 196, 197, and 198 is formed. A common electrode 270 having cutout patterns 271, 272, 273, 274, 275, 276, 277, and 278 is formed on the opposing display panel 200 facing the thin film transistor array panel. Cutting patterns 191, 192, 193, 194, 195, 196, 197, and 198 of the pixel electrode 190 and cutting patterns 191, 192, 193, 194, 195, 196, 197, and 198 of the common electrode 270. ) Are alternately arranged as in the first embodiment, and the pixel region is divided into a plurality of small domains. Although the opening pattern is described as an example of the domain dividing means, it may be used as a protrusion or bone conduction domain dividing means.

As shown in FIGS. 5 and 6, the thin film transistor array panel 100 according to the second exemplary embodiment of the present invention is mostly similar to FIGS. 3 and 4.

However, a plurality of linear semiconductors 151 and a plurality of ohmic contacts 163 and 165 are provided.

The linear semiconductor 151 is substantially planar with the plurality of data lines 171 and the plurality of drain electrodes 175 except for the channel region of the thin film transistor between the source electrode 173 and the drain electrode 175. . That is, although the data line 171 and the drain electrode 175 are separated from each other in the channel region, the linear semiconductor 151 is connected here without disconnection to form a channel of the thin film transistor. The ohmic contacts 163 and 165 have the same shape as the data line 171 and the drain electrode 175, respectively.

The gate line 121, the semiconductor 151, and the ohmic contacts 163 and 165 have a tapered structure.

In the method of manufacturing the thin film transistor array panel according to the second exemplary embodiment of the present invention, the data line 171, the drain electrode 175, and the semiconductor layer 151 are patterned by a photolithography process using one photoresist pattern. In this case, the photoresist pattern includes a first portion and a second portion having different thicknesses, wherein the second portion is positioned in the channel region of the thin film transistor, and the first portion is positioned in the data line and drain electrode region. Has a thickness thinner than the first portion. Here, the first and second portions are used as etching masks for patterning the semiconductor layer 151, and the first portions are used as etching masks for patterning the data lines and drain electrodes. As such, there may be various methods of varying the thickness of the photoresist pattern according to the position. For example, a translucent area may be added to the photomask in addition to the transparent area and the light blocking area. There is a way to put it. The translucent region is provided with a slit pattern, a lattice pattern, or a thin film having a medium transmittance or a medium thickness. When using the slit pattern, it is preferable that the width of the slit or the distance between the slits is smaller than the resolution of the exposure machine used for the photographic process. Another example is to use a photoresist film that can be reflowed. That is, a thin portion is formed by forming a reflowable photoresist pattern with a normal mask having only a transparent region and a light shielding region, and then reflowing to allow the photoresist film to flow down into a region where no residue remains.

The effect of the second embodiment is the same as that of the first embodiment. That is, the load on the wiring is reduced, the amount of change in the liquid crystal capacitance on the wiring is reduced, the light leakage due to the side crosstalk is reduced, and the aperture ratio can be increased.

In addition, although the opening is formed in the reference electrode corresponding to the data line in the embodiment of the present invention, the opening may be added to the reference electrode corresponding to the gate line in another embodiment.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated. In particular, the arrangement of the cutouts formed on the pixel electrode and the common electrode may be variously modified, and modifications such as placing protrusions instead of forming the cutout may be possible.

As described above, by forming the data line opening by removing the common electrode above the data line, the load on the wiring is reduced, the amount of change in the liquid crystal capacitance applied to the wiring is reduced, and the light leakage due to side crosstalk is reduced. The aperture ratio can be increased. When the load on the wiring is reduced, limitations in the selection and resolution of the conductive material used as the data line can be overcome. In addition, if the amount of change in the liquid crystal capacitance applied to the wiring is reduced, the problem of the vertical cross-talk which appears first when the charging rate is low is improved, thereby increasing the limit on the charging rate. In addition, it is possible to obtain a liquid crystal display device having excellent image quality by reducing light leakage and increasing aperture ratio by side crosstalk.

Claims (10)

  1. Insulating first substrate,
    First wiring formed on the first substrate,
    A second wiring formed on the first substrate and insulated from and intersecting the first wiring;
    A thin film transistor connected to the first wiring and the second wiring, a pixel electrode connected to the thin film transistor and divided into a plurality of small portions by a first domain dividing means;
    An insulating second substrate facing the first substrate,
    Second domain dividing means formed on the second substrate and dividing the pixel electrode into a plurality of small domains together with the first domain dividing means;
    The opening is spaced apart from the second domain dividing means and disposed between two neighboring pixel electrodes, and overlaps the first wiring or the second wiring and extends in the longitudinal direction along the first wiring or the second wiring. Common electrode
    Including,
    The opening is positioned between the boundary lines of two pixel electrodes neighboring the first wiring or the second wiring.
  2. In claim 1,
    Wherein the first domain dividing means is a cutout of the pixel electrode and the second domain dividing means is a cutoff of the common electrode.
  3. In claim 2,
    The width of the common electrode positioned between the second domain dividing means and the opening is in the range of 3-6 μm.
  4. Insulating first substrate,
    A gate line formed on the first substrate and extending in a horizontal direction and having a gate electrode;
    A gate insulating film formed on the gate line,
    A semiconductor layer formed on the gate insulating film on the gate electrode;
    A data line including a source electrode and a drain electrode facing the gate electrode and the source electrode and crossing the gate line;
    A pixel electrode connected to the drain electrode and having a first cutout for dividing and aligning liquid crystal molecules;
    An insulating second substrate facing the first substrate,
    A second cutout and a second cutout for dividing the liquid crystal molecules along with the first cutout and the second cutout, and overlap the gate line or the data line and extend in the longitudinal direction along the gate line or the data line. Common electrode with opening
    Including,
    And the opening is positioned between a boundary line between two pixel electrodes adjacent to the gate line or the data line.
  5. In claim 4,
    And a storage electrode line formed on the first substrate in the same layer as the gate line and overlapping the pixel electrode to form a storage capacitor.
  6. In claim 4,
    And at least two openings separated from each other along the gate line or the data line.
  7. In claim 6,
    The width of the common electrode between the second cutout, the opening, and the opening adjacent to each other is in a range of 3-6 μm.
  8. In claim 4,
    And a resistive contact member formed between the semiconductor layer, the data line, and the drain electrode.
  9. In claim 8,
    And the semiconductor layer and the ohmic contact are formed along the data line and the drain electrode.
  10. The method of claim 9,
    The semiconductor layer except for the channel region of the thin film transistor has the same planar shape as the data line and the drain electrode.
KR20030030195A 2003-05-13 2003-05-13 A vertically aligned mode liquid crystal display KR100961946B1 (en)

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KR20030030195A KR100961946B1 (en) 2003-05-13 2003-05-13 A vertically aligned mode liquid crystal display
US10/844,239 US7110075B2 (en) 2003-05-13 2004-05-12 Liquid crystal display with domain-defining members and separate opening in the common electrode overlapping the gate or data lines
JP2004144019A JP2004341530A (en) 2003-05-13 2004-05-13 Vertical alignment type liquid crystal display device
CNB2004100631575A CN100432803C (en) 2003-05-13 2004-05-13 Liquid crystal display
TW93113530A TWI291234B (en) 2003-05-13 2004-05-13 Liquid crystal display
US11/523,302 US7379142B2 (en) 2003-05-13 2006-09-19 Liquid crystal display

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KR100961946B1 true KR100961946B1 (en) 2010-06-10

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Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101061844B1 (en) * 2004-06-29 2011-09-02 삼성전자주식회사 Manufacturing method of thin film display panel
KR101160825B1 (en) * 2004-08-18 2012-06-29 삼성전자주식회사 Liquid crystal display
KR101061848B1 (en) * 2004-09-09 2011-09-02 삼성전자주식회사 Thin film transistor panel and multi-domain liquid crystal display including the same
JP4658622B2 (en) * 2005-01-19 2011-03-23 シャープ株式会社 Substrate for liquid crystal display device and liquid crystal display device
US7639333B2 (en) 2005-04-06 2009-12-29 Samsung Electronics Co., Ltd. Display panel and liquid crystal display apparatus including the same
KR101189270B1 (en) * 2005-04-06 2012-10-15 삼성디스플레이 주식회사 Panel and liquid crystal display includig the same
KR20060116878A (en) * 2005-05-11 2006-11-15 삼성전자주식회사 Substrate for display device, method of manufacturing the same and liquid crystal display device having the same
KR101251994B1 (en) * 2005-07-01 2013-04-08 삼성디스플레이 주식회사 Liquid crystal display
US7656487B2 (en) 2005-07-01 2010-02-02 Samsung Electronics Co., Ltd. Liquid crystal display
KR101261611B1 (en) * 2005-09-15 2013-05-06 삼성디스플레이 주식회사 Liquid crystal display
KR100643376B1 (en) * 2005-10-24 2006-10-31 삼성전자주식회사 Display device and method of making display device
KR101279189B1 (en) * 2005-11-10 2013-07-05 엘지디스플레이 주식회사 Liquid crystal display device of horizontal electronic field applying type and fabricating method thereof
KR101251996B1 (en) * 2005-12-07 2013-04-08 삼성디스플레이 주식회사 Liquid crystal display
CN101038407B (en) * 2006-03-17 2010-09-08 奇美电子股份有限公司 Vertical nematic liquid crystal with multiple display zones
KR101189090B1 (en) * 2006-07-18 2012-11-09 삼성디스플레이 주식회사 Liquid crystal display apparatus and mathod of driving thereof
KR101282402B1 (en) * 2006-09-15 2013-07-04 삼성디스플레이 주식회사 Liquid crystal display device
WO2008050501A1 (en) * 2006-09-29 2008-05-02 Sharp Kabushiki Kaisha Display device and method of producing display device
TWI342428B (en) * 2006-12-29 2011-05-21 Chimei Innolux Corp Mva liquid crystal display panel
TWI349138B (en) * 2006-12-29 2011-09-21 Chimei Innolux Corp Multi-domain vertical alignment liquid crystal panel
KR101427708B1 (en) * 2007-02-01 2014-08-11 삼성디스플레이 주식회사 Liquid crystal display panel
WO2008136150A1 (en) * 2007-04-23 2008-11-13 Sharp Kabushiki Kaisha Display, and method of manufacturing display
CN101354508B (en) * 2007-07-23 2010-06-02 中华映管股份有限公司 Liquid crystal display panel
KR20100005883A (en) 2008-07-08 2010-01-18 삼성전자주식회사 Array substrate and liquid crystal display apparatus having the same
KR20100008566A (en) * 2008-07-16 2010-01-26 삼성전자주식회사 Liquid crystal display
JP5332548B2 (en) * 2008-11-26 2013-11-06 凸版印刷株式会社 Color filter and liquid crystal display device including the same
KR101539953B1 (en) * 2008-12-04 2015-07-29 삼성디스플레이 주식회사 Liquid crystal display apparatus
KR101722501B1 (en) * 2009-01-09 2017-04-04 삼성디스플레이 주식회사 Thin film transistor and liquid crystal display having the same
WO2010092706A1 (en) 2009-02-13 2010-08-19 シャープ株式会社 Array substrate, liquid crystal display device, and electronic device
CN101840099B (en) * 2009-03-18 2012-12-26 北京京东方光电科技有限公司 Liquid crystal display panel and manufacture method thereof
JP2011048396A (en) * 2010-12-06 2011-03-10 Sharp Corp Substrate for display device and display device
KR101791579B1 (en) * 2011-04-08 2017-10-31 삼성디스플레이 주식회사 Liquid crystal display
JP5572603B2 (en) * 2011-08-30 2014-08-13 株式会社ジャパンディスプレイ Liquid crystal display
JP6139308B2 (en) * 2013-07-12 2017-05-31 スタンレー電気株式会社 Liquid crystal display
TWI537656B (en) 2014-03-14 2016-06-11 群創光電股份有限公司 Display device
US9659973B2 (en) 2014-03-14 2017-05-23 Innolux Corporation Display device
US9507222B2 (en) 2014-03-14 2016-11-29 Innolux Corporation Display device
US10324345B2 (en) 2014-03-14 2019-06-18 Innolux Corporation Display device and display substrate
US9570365B2 (en) 2014-03-14 2017-02-14 Innolux Corporation Display device and test pad thereof
US9750140B2 (en) 2014-03-14 2017-08-29 Innolux Corporation Display device
US9513514B2 (en) 2014-03-14 2016-12-06 Innolux Corporation Display device

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06118447A (en) * 1992-10-06 1994-04-28 Sony Corp Liquid crystal panel
JPH08286207A (en) * 1995-04-14 1996-11-01 Casio Comput Co Ltd Liquid crystal display element
CN1139837C (en) * 1998-10-01 2004-02-25 三星电子株式会社 Film transistor array substrate for liquid crystal display and manufacture thereof
KR100293809B1 (en) * 1998-05-29 2001-04-07 박종섭 Ips-va mode liquid crystal display having multi domain
KR100357216B1 (en) * 1999-03-09 2002-10-18 엘지.필립스 엘시디 주식회사 Multi-domain liquid crystal display device
KR100354906B1 (en) * 1999-10-01 2002-09-30 삼성전자 주식회사 A wide viewing angle liquid crystal display
KR100635940B1 (en) * 1999-10-29 2006-10-18 삼성전자주식회사 A vertically aligned mode liquid crystal display
JP3425928B2 (en) * 2000-05-30 2003-07-14 シャープ株式会社 Liquid crystal display device and method of manufacturing the same
KR100366770B1 (en) * 2001-04-06 2003-01-06 삼성전자 주식회사 a liquid crystal display
KR100759978B1 (en) * 2001-07-12 2007-09-18 삼성전자주식회사 A vertically aligned mode liquid crystal display and a color filter substrate for the same

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US20070008475A1 (en) 2007-01-11
US7379142B2 (en) 2008-05-27
TW200527679A (en) 2005-08-16
US7110075B2 (en) 2006-09-19
CN1550862A (en) 2004-12-01
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US20040227888A1 (en) 2004-11-18
TWI291234B (en) 2007-12-11
JP2004341530A (en) 2004-12-02

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