KR20020007877A - Substrate for manufacturing semiconductor package - Google Patents
Substrate for manufacturing semiconductor package Download PDFInfo
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- KR20020007877A KR20020007877A KR1020000041404A KR20000041404A KR20020007877A KR 20020007877 A KR20020007877 A KR 20020007877A KR 1020000041404 A KR1020000041404 A KR 1020000041404A KR 20000041404 A KR20000041404 A KR 20000041404A KR 20020007877 A KR20020007877 A KR 20020007877A
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- KR
- South Korea
- Prior art keywords
- semiconductor package
- singulation
- circuit board
- printed circuit
- manufacturing
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
Description
본 발명은 반도체 패키지 제조용 부재에 관한 것으로서, 더욱 상세하게는 스트립 형태로 이루어진 부재에 싱귤레이션 공정을 용이하게 실시할 수 있도록 네모서리를 제외한 싱귤레이션 라인을 따라 슬롯홀을 형성한 구조의 반도체 패키지 제조용 부재에 관한 것이다.The present invention relates to a member for manufacturing a semiconductor package, and more particularly, to manufacturing a semiconductor package having a structure in which slot holes are formed along a singulation line except for four corners so that a singulation process can be easily performed on a strip-shaped member. It is about absence.
통상적으로 반도체 패키지는 전자기기의 집약적인 발달과 소형화 경향으로 고집적화, 소형화, 고기능화를 실현할 수 있는 제조 추세에 있는 바, 반도체 칩탑재판의 저면이 외부로 노출된 구조의 반도체 패키지, 솔더볼과 같은 인출단자를 포함하는 볼 그리드 어레이 반도체 패키지등, 리드프레임, 인쇄회로기판, 필름등의 부재를 이용하여 다양한 종류의 패기키가 경박단소화로 개발되어 왔고, 개발중에 있다.In general, semiconductor packages are in the manufacturing trend to realize high integration, miniaturization, and high functionality due to the intensive development and miniaturization of electronic devices. Various types of package keys have been developed in a light and thin form by using a member such as a lead frame, a printed circuit board, a film, and the like, such as a ball grid array semiconductor package including a terminal.
상기 나열한 부재중에 인쇄회로기판의 구조를 설명하고, 이를 이용하여 반도체 패키지를 제조하는 공정을 첨부한 도 3을 참조로 설명하면 다음과 같다.The structure of the printed circuit board among the members listed above will be described with reference to FIG. 3 to which a process of manufacturing a semiconductor package using the same is described below.
상기 인쇄회로기판(10)은 다수의 반도체 패키지 영역으로 나누어진 스트립 형태로 되어 있는 바, 각각의 반도체 패키기 영역은 수지층(40)과, 이 수지층(40)을 중심으로 양면에 식각 처리된 전도성패턴(50)과, 이 전도성패턴(50)의 일부를 노출시키며 코팅 처리된 커버코트(60)와, 상기 수지층(40)을 관통하여 상하의 전도성패턴(50)을 연결하는 전도성의 비아홀(80)로 구성되고, 상면의 커버코트(60) 사이로 노출된 전도성패턴(50)은 와이어 본딩용으로 사용되며, 저면의 커버코트(60) 사이로 노출된 전도성패턴(50)은 인출단자(70)를 부착하기 위한 볼랜드가 된다.The printed circuit board 10 has a strip shape divided into a plurality of semiconductor package regions, and each semiconductor package region is etched on both sides of the resin layer 40 and the resin layer 40. Conductive via 50 to expose the conductive pattern 50, a portion of the conductive pattern 50, and a coated cover coat 60 and a conductive pattern 50 connected through the resin layer 40 to the upper and lower conductive patterns 50. Conductive pattern 50 consisting of 80, exposed between the cover coat 60 of the upper surface is used for wire bonding, the conductive pattern 50 exposed between the cover coat 60 of the bottom surface is the lead terminal 70 ) Is a ball land for attaching.
따라서, 상기 인쇄회로기판(10)의 중앙부에 형성된 반도체 칩 탑재영역에 반도체 칩을 부착하는 공정과, 상기 인쇄회로기판(10)상의 커버코트(60) 사이로 노출된 와이어 본딩용 전도성패턴(50)과 상기 반도체 칩의 본딩패드간을 와이어로 본딩하는 공정과, 상기 반도체 칩과 와이어와 전도성패턴등을 외부로부터 보호하기 위하여 수지로 몰딩하는 공정과, 상기 인쇄회로기판(10)의 저면에 형성된 볼랜드에 솔더볼과 같은 인출단자(70)를 부착하는 공정과, 상기 스트립 형태로 된 인쇄회로기판(10)을 낱개의 단위로 싱귤레이션시키는 공정을 마지막으로 첨부한 도 3의 반도체 패키지(100)가 완성된다.Therefore, the process of attaching the semiconductor chip to the semiconductor chip mounting region formed in the central portion of the printed circuit board 10, and the conductive pattern 50 for wire bonding exposed between the cover coat 60 on the printed circuit board 10 Bonding between the bonding pads of the semiconductor chip with a wire, molding the semiconductor chip with wires, a conductive pattern, and the like to protect from the outside, and a borland formed on the bottom surface of the printed circuit board 10. The semiconductor package 100 of FIG. 3 is finally attached to a process of attaching a lead terminal 70, such as solder balls, and a process of singulating the printed circuit board 10 in the form of strips into individual units. do.
한편, 상기 스트립 형태의 인쇄회로기판을 하나의 단위로 싱귤레이션하는 공정은 인쇄회로기판(10)의 싱귤레이션 라인(30)을 따라 싱귤레이션 펀치를 사용하여 펀칭을 함에 따라 이루어지는데, 이때 다음과 같은 문제점이 발생한다.Meanwhile, the process of singulating the strip-shaped printed circuit board as a unit is performed by punching using a singulation punch along the singulation line 30 of the printed circuit board 10. The same problem occurs.
1) 싱귤레이션 펀치의 펀칭시 하중에 의하여 커버코트에 크랙이 발생한다.1) Crack occurs in the cover coat due to the load when punching the singulation punch.
2) 펀칭시의 하중이 크기 때문에 펀치와 싱귤레이션 다이의 수명이 감소한다.2) The life of punch and singulation die is reduced because of the large load during punching.
3) 펀칭시 하중에 의하여 반도체 패키지의 평면도가 불규칙해질 수 있다.3) The plan view of the semiconductor package may be irregular due to the load during punching.
4) 싱귤레이션 영역에 펀치의 하중이 너무 집중되어, 마이크로 갭을 유발할 수 있다.4) The load of the punch is too concentrated in the singulation area, which can cause a micro gap.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위하여 인쇄회로기판의 싱귤레이션 라인의 네모서리를 제외한 부위에 미리 슬롯홀을 형성하여, 싱귤레이션 공정시 싱귤레이션 라인에 대한 펀치의 하중이 집중됨이 방지되며 펀치가 네모서리만 펀칭함에 따라, 싱귤레이션이 용이하게 이루어지도록 한 구조의 반도체 패키지 제조용 부재를 제공하는데 목적이 있다.Therefore, in order to solve the problems described above, the present invention forms slot holes in advance except for the corners of the singulation line of the printed circuit board to prevent the punch load on the singulation line from being concentrated during the singulation process. And it is an object of the present invention to provide a member for manufacturing a semiconductor package having a structure to facilitate singulation as the punch punches only the corners.
도 1은 본 발명에 따른 반도체 패키지 제조용 부재를 나타내는 평면도,1 is a plan view showing a member for manufacturing a semiconductor package according to the present invention,
도 2는 종래의 반도체 패키지 제조용 부재를 나타내는 평면도.2 is a plan view showing a conventional member for manufacturing a semiconductor package.
도 3은 도 1과 도 2의 부재를 이용하여 제조된 반도체 패키지를 나타내는 단면도.3 is a cross-sectional view illustrating a semiconductor package manufactured using the members of FIGS. 1 and 2.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
10 : 인쇄회로기판 20 : 슬롯홀(Slot hole)10: printed circuit board 20: slot hole
30 : 싱귤레이션 라인(Singulation line)30: Singulation line
40 : 수지층 50 : 전도성 패턴(Patten)40: resin layer 50: conductive pattern (Patten)
60 : 커버코트(Cover coat) 70 : 인출단자60: cover coat 70: withdrawal terminal
80 : 비아홀 (Via hole) 100 : 반도체 패키지80: Via hole 100: Semiconductor package
이하, 본 발명을 첨부도면을 참조로 상세하게 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
상기한 본 발명의 목적을 달성하기 위한 본 발명은 다수의 반도체 패키지 영역이 형성된 스트립 형태의 반도체 패키지 제조용 부재에 있어서, 상기 부재의 싱귤레이션 라인(30)의 네모서리를 제외한 부위에 슬롯홀(20)을 형성하여 달성된 것을 특징으로 한다.According to the present invention for achieving the object of the present invention, in the strip-shaped semiconductor package manufacturing member formed with a plurality of semiconductor package region, the slot hole 20 in the portion except the four corners of the singulation line 30 of the member It is characterized by achieved by forming a).
상기 부재는 스트립 형태로 된 인쇄회로기판 또는 회로필름인 것을 특징으로 한다.The member is characterized in that the printed circuit board or circuit film in the form of a strip.
특히, 상기 부재의 슬롯홀(20)의 안쪽 라인은 싱귤레이션 라인(30)과 일치되게 형성된다.In particular, the inner line of the slot hole 20 of the member is formed to match the singulation line 30.
여기서 본 발명을 실시예로서, 첨부한 도면을 참조로 더욱 상세하게 설명하면 다음과 같다.Herein, the present invention will be described in more detail with reference to the accompanying drawings.
첨부한 도 1은 본 발명에 다른 반도체 패키지 제조용 부재를 나타내는 평면도로서, 상기 부재는 인쇄회로기판(10)을 나타낸다.1 is a plan view showing a member for manufacturing a semiconductor package according to the present invention, wherein the member shows a printed circuit board 10.
상기 인쇄회로기판(10)은 다수의 반도체 패키지 영역이 일방향으로 등간격을 이루며 형성된 스트립 형태로서, 각각의 반도체 패키지 영역은 상술한 바와 같이 수지층(40)과, 이 수지층(40)을 중심으로 양면에 식각 처리된 전도성패턴(50)과, 이 전도성패턴(50)의 일부를 노출시키며 상하면에 코팅 처리된 커버코트(60)와, 상기 수지층(40)을 관통하여 상하의 전도성패턴(50)을 연결하는 전도성의 비아홀(90)로 구성되어 있다.The printed circuit board 10 has a strip shape in which a plurality of semiconductor package regions are formed at equal intervals in one direction, and each semiconductor package region has a resin layer 40 and the resin layer 40 as described above. The conductive pattern 50 etched on both sides, a portion of the conductive pattern 50 is exposed, and the cover coat 60 is coated on the upper and lower surfaces, and the upper and lower conductive patterns 50 penetrate through the resin layer 40. It is composed of a conductive via hole (90) connecting.
여기서, 상기와 같이 구성된 스트립 형태의 인쇄회로기판(10)에서 각각의 반도체 패키지 영역 즉, 싱귤레이션 라인(30)을 따라 슬롯홀(20)을 형성하는 바, 네모서리를 제외한 부위에 형성한다.Here, in the strip-shaped printed circuit board 10 configured as described above, the slot hole 20 is formed along each semiconductor package area, that is, the singulation line 30, and is formed in a portion excluding a corner.
좀 더 상세하게는, 상기 슬롯홀(20)은 그 안쪽라인이 싱귤레이션 라인(30)과 일치되도록 형성된다.In more detail, the slot hole 20 is formed such that its inner line coincides with the singulation line 30.
따라서, 상기와 같은 구조의 인쇄회로기판을 이용하여 상술한 바와 같이 반도체 칩 부착 공정과, 와이어 본딩 공정과, 몰딩 공정과, 인출단자 부착 공정을 거쳐 마지막으로 상기 스트립 형태로 된 인쇄회로기판을 낱개의 단위로 싱귤레이션시키는 공정을 진행하게 되는데, 싱귤레이션 펀치가 상기 인쇄회로기판의 슬롯홀(20)을 제외한 네모서리를 펀칭함으로써, 싱귤레이션이 손쉽게 이루어진다.Therefore, the printed circuit board in the form of a strip is finally separated through the semiconductor chip attaching process, the wire bonding process, the molding process, and the drawing-out terminal attaching process as described above using the printed circuit board having the above structure. The singulation process is performed in the unit of S. The singulation punch is easily punched by punching the four corners except the slot hole 20 of the printed circuit board.
즉, 싱귤레이션 펀치가 인쇄회로기판(10)의 슬롯홀(20)을 제외한 네모서리 부위만 펀칭함에 따라, 싱귤레이션 라인에 하중이 집중되는 현상이 배제되며 용이하게 싱귤레이션이 이루어진다.That is, since the singulation punch punches only the corners of the printed circuit board 10 except for the slot hole 20, the phenomenon in which the load is concentrated on the singulation line is eliminated and the singulation is easily performed.
한편, 상기 인쇄회로기판(10) 이외에 스트립 형태로 된 부재로서, 필름과 필름상에 전도성패턴이 식각 처리된 회로필름과 같은 부재의 싱귤레이션 라인에도 상기 슬롯홀을 형성하여, 싱귤레이션을 손쉽게 실시할 수 있다.Meanwhile, as a member having a strip shape in addition to the printed circuit board 10, the slot hole is formed in a singulation line of a member such as a circuit film in which a conductive pattern is etched on the film and the film, thereby easily performing singulation. can do.
이상에서 본 바와 같이 본 발명에 따른 반도체 패키지 제조용 부재에 의하면 스트립 형태로 된 부재의 싱귤레이션 라인의 네모서리를 제외한 부위에 슬롯홀을 형성함으로써, 싱귤레이션 공정시 네모서리만 펀칭함에 따라 싱귤레이션이 용이하게 이루어지고, 물론 싱귤레이션 라인에 대한 싱귤레이션 펀치의 하중이 집중되는 것이 배제되어 부재의 손상을 방지할 수 있는 장점이 있다.As described above, according to the member for manufacturing a semiconductor package according to the present invention, by forming a slot hole in a portion except for the corners of the singulation line of the strip-shaped member, the singulation is performed by punching only the corners during the singulation process. It is easily made, and of course, the concentration of the singulation punch on the singulation line is excluded from the concentration, and thus there is an advantage of preventing damage to the member.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000041404A KR20020007877A (en) | 2000-07-19 | 2000-07-19 | Substrate for manufacturing semiconductor package |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000041404A KR20020007877A (en) | 2000-07-19 | 2000-07-19 | Substrate for manufacturing semiconductor package |
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| KR20020007877A true KR20020007877A (en) | 2002-01-29 |
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| Application Number | Title | Priority Date | Filing Date |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007079125A2 (en) * | 2005-12-29 | 2007-07-12 | Sandisk Corporation | Leadframe based flash memory cards |
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2000
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007079125A2 (en) * | 2005-12-29 | 2007-07-12 | Sandisk Corporation | Leadframe based flash memory cards |
| WO2007079125A3 (en) * | 2005-12-29 | 2007-10-04 | Sandisk Corp | Leadframe based flash memory cards |
| US7488620B2 (en) | 2005-12-29 | 2009-02-10 | Sandisk Corporation | Method of fabricating leadframe based flash memory cards including singulation by straight line cuts |
| US7795715B2 (en) | 2005-12-29 | 2010-09-14 | Sandisk Corporation | Leadframe based flash memory cards |
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