KR100401146B1 - Manufacturing method of substrate for manufacturing semiconductor package - Google Patents
Manufacturing method of substrate for manufacturing semiconductor package Download PDFInfo
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- KR100401146B1 KR100401146B1 KR10-2000-0073057A KR20000073057A KR100401146B1 KR 100401146 B1 KR100401146 B1 KR 100401146B1 KR 20000073057 A KR20000073057 A KR 20000073057A KR 100401146 B1 KR100401146 B1 KR 100401146B1
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- heat sink
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
본 발명은 반도체 패키지 제조용 부재의 제조 방법에 관한 것으로서, 특히 히트싱크에 회로필름이 부착된 구조의 반도체 패키지 제조용 부재를 제조함에 있어서, 종래의 포토레지스트와 같은 마스크의 사용을 배제시킴으로써, 마스크를 부치고 떼어내는 등의 공정수를 절감시켜 작업효율을 향상시킬 수 있고, 그에 따라 제조시간과 제조원가를 절감시킬 수 있도록BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a member for manufacturing a semiconductor package. In particular, in manufacturing a member for manufacturing a semiconductor package having a structure in which a circuit film is attached to a heat sink, a mask is provided by eliminating the use of a mask such as a conventional photoresist. In order to reduce the number of processes such as stripping, it is possible to improve the work efficiency, thereby reducing the manufacturing time and manufacturing cost.
소정의 크기와 두께를 갖는 히트싱크를 제공하는 단계와; 상기 히트싱크상에 반도체 패키지 영역을 나누어주는 슬롯홀과, 각 공정에서 고정수단이 삽입되는 가이드홀을 스탬핑수단으로 관통되게 형성하는 단계와; 상기 히트싱크상의 반도체 패키지 영역에 회로필름을 부착시키되, 칩이 부착되는 영역을 제외하고 부착시키는 단계와; 상기 히트싱크상의 칩 부착영역과, 반도체 패키지 영역을 제외한 영역을 하프에칭 처리하는 단계로 이루어진 것을 특징으로 하는 반도체 패키지 제조용 부재의 제조방법을 제공하고자 한 것이다.Providing a heat sink having a predetermined size and thickness; Forming a slot hole for dividing the semiconductor package region on the heat sink and a guide hole into which the fixing means is inserted in each process through the stamping means; Attaching a circuit film to a semiconductor package region on the heat sink, except for a region to which a chip is attached; It is an object of the present invention to provide a method for manufacturing a member for manufacturing a semiconductor package, comprising the step of half-etching the chip attaching region on the heat sink and a region other than the semiconductor package region.
Description
본 발명은 반도체 패키지 제조용 부재의 제조 방법에 관한 것으로서, 더욱 상세하게는 히트싱크에 회로필름이 부착된 구조의 반도체 패키지 제조용 부재의 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a member for manufacturing a semiconductor package, and more particularly, to a method for manufacturing a member for manufacturing a semiconductor package having a structure in which a circuit film is attached to a heat sink.
일반적으로 반도체 패키지는 전자기기의 급진전인 발전과 소형화 경향으로 인하여 고집적화, 소형화, 고기능화를 실현할 수 있는 제조 추세에 있는 바, 리드프레임, 인쇄회로기판, 회로필름등의 각종 부재를 이용하여 다양한 구조로 제조되고 있다.In general, semiconductor packages have been manufactured to realize high integration, miniaturization, and high functionality due to the rapid development and miniaturization of electronic devices. Is being manufactured.
특히, 상기 나열된 반도체 패키지 제조용 부재중 회로필름을 히트싱크에 부착시킨 구조의 부재가 첨부한 도 2에 도시한 바와 같은 구조로 제조되고 있는데, 그 종래의 제조 방법을 설명하면 다음과 같다.In particular, a member having a structure in which a circuit film is attached to a heat sink among the above-listed members for manufacturing a semiconductor package is manufactured as shown in FIG. 2, which is described below.
먼저, 소정의 크기와 두께를 갖는 동판(이하, 히트싱크라 칭함)을 구비하는 단계(110)와; 상기 히트싱크(14)의 상하 양면에 에칭액이 닿아도 부식되지 않는 포토레지스트(photoresist)와 같은 마스크(26)를 부착시키되, 에칭 처리되지 않는 영역에만 부착시키는 단계(120)를 진행시킨다.First, a step (110) having a copper plate (hereinafter referred to as heat sink) having a predetermined size and thickness; A mask 26, such as a photoresist, which does not corrode even when an etchant touches the upper and lower surfaces of the heat sink 14, is attached, but is attached only to a region that is not etched.
이때, 상기 마스크(26)가 부착되지 않은 영역은 에칭 처리되는 영역으로서, 첨부한 도 3a,3b에 도시한 바와 같이, 반도체 패키지 영역내의 반도체 칩 부착용홈(16)과 슬롯홀(18), 사이드레일(22)의 가이드홀(20)이 에칭에 의하여 형성될 영역에만 마스크가 부착되지 않게 된다.At this time, the region to which the mask 26 is not attached is a region to be etched. As shown in FIGS. 3A and 3B, the semiconductor chip attaching groove 16, the slot hole 18, and the side of the semiconductor package region are shown. The mask is not attached only to the region where the guide hole 20 of the rail 22 is to be formed by etching.
다음으로, 상기 마스크(26)가 부착되지 않은 영역을 에칭액으로 에칭 처리하는 단계(130)를 진행함으로써, 상기 반도체 칩 부착용 홈(16)은 하프에칭으로 형성되고, 슬롯홀(18)과 가이드홀(20)은 관통되어 형성된다.Next, by performing the step 130 of etching the region where the mask 26 is not attached with the etching solution, the grooves 16 for attaching the semiconductor chips are formed by half etching, and the slot holes 18 and the guide holes are formed. 20 is formed through.
이어서, 상기 히트싱크(14)의 상하 양면에 부착된 마스크(26)를 떼어내는 단계(140)를 진행한 다음, 상기 반도체 칩 부착용 홈(16)을 제외한 반도체 패키지 영역에 걸쳐 회로필름(12)을 양면테이프와 같은 접착수단으로 부착하는 단계(150)를 마지막으로 반도체 패키지 제조용 부재(10)가 완성된다.Subsequently, the process of removing the mask 26 attached to the upper and lower surfaces of the heat sink 14 is performed 140, and then the circuit film 12 is spread over the semiconductor package region except for the semiconductor chip attaching groove 16. Finally, the step 150 of attaching the adhesive medium such as a double-sided tape is completed.
이때, 상기 회로필름(12)은 베이스층으로서 절연체인 수지필름(30)과; 이 수지필름(30)상에 에칭 처리된 전도성패턴(28)과; 이 전도성패턴(28)들중 와이어 본딩용과 인출단자 부착용 전도성패턴을 노출시키면서 수지필름(30)상에 도포된 커버코트(32)로 구성되어 있다.In this case, the circuit film 12 includes a resin film 30 which is an insulator as a base layer; A conductive pattern 28 etched on the resin film 30; Among the conductive patterns 28, the cover coat 32 is coated on the resin film 30 while exposing the conductive patterns for wire bonding and the lead terminal attachment.
그러나, 상기 히트싱크상에 회로필름이 부착된 구조의 반도체 패키지 제조용 부재를 제조하는데 있어서, 다음과 같은 단점이 있었다.However, in manufacturing a semiconductor package manufacturing member having a structure in which a circuit film is attached on the heat sink, there are the following disadvantages.
우선, 상술한 종래의 반도체 패키지 제조용 부재의 제조 방법은 포토레지스트(photoresist)와 같은 마스크(mask)를 부착시키고, 후공정에서 다시 떼어내는 등의 여러 제조 공정수 진행되어 작업효율이 떨어지고, 그에따른 작업시간도 오래 걸리게 되어, 제조원가 상승의 원인이 되어 왔다.First, in the aforementioned method for manufacturing a semiconductor package manufacturing member, a number of manufacturing processes, such as attaching a mask such as a photoresist and detaching it in a later step, are performed to reduce work efficiency. The working time also takes a long time, causing a rise in manufacturing cost.
따라서, 본 발명은 상기와 같은 점을 감안하여, 히트싱크에 회로필름이 부착된 구조의 반도체 패키지 제조용 부재를 제조함에 있어서, 종래의 포토레지스트와 같은 마스크의 사용을 배제시킴으로써, 마스크를 부치고 떼어내는 등의 공정수를 절감시켜 작업효율을 향상시킬 수 있고, 그에따라 제조시간과 제조원가를 절감시킬 수 있도록 한 반도체 패키지 제조용 부재의 제조방법을 제공하는데 그 목적이 있다.Accordingly, in view of the above, the present invention eliminates the use of a mask, such as a conventional photoresist, in manufacturing a member for manufacturing a semiconductor package having a structure in which a circuit film is attached to a heat sink. It is an object of the present invention to provide a method for manufacturing a member for manufacturing a semiconductor package, which can improve the work efficiency by reducing the number of processes, and the like, thereby reducing the manufacturing time and manufacturing cost.
도 1은 본 발명의 반도체 패키지 제조용 부재의 제조방법을 나타내는 단면도,1 is a cross-sectional view showing a method for manufacturing a member for manufacturing a semiconductor package of the present invention;
도 2는 종래의 반도체 패키지 제조용 부재의 제조방법을 나타내는 단면도,2 is a cross-sectional view showing a conventional method for manufacturing a member for manufacturing a semiconductor package;
도 3a,3b는 본 발명 또는 종래의 제조방법에 따라 최종 제조된 부재를 나타내는 평면도 및 저면도,3a and 3b are a plan view and a bottom view showing a member finally manufactured according to the present invention or a conventional manufacturing method,
도 4는 도 3의 부재를 이용하여 제조된 반도체 패키지를 나타내는 단면도.4 is a cross-sectional view illustrating a semiconductor package manufactured using the member of FIG. 3.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
10 : 부재 12 : 회로필름10 member 12 circuit film
14 : 히트싱크(heat sink) 16 : 반도체 칩 부착용 홈14 heat sink 16 groove for attaching semiconductor chip
18 : 슬롯홀 20 : 가이드홀18: slot hole 20: guide hole
22 : 사이드레일(side rail) 24 : 반도체 칩22: side rail 24: semiconductor chip
26 : 마스크 (mask) 28 : 전도성패턴26: mask 28: conductive pattern
30 : 수지필름 32 : 커버코트(cover coat)30: resin film 32: cover coat
34 : 인출단자 36 : 와이어34: withdrawal terminal 36: wire
38 : 수지 40 : 댐(dam)38: resin 40: dam
상술한 목적을 달성하기 위한 본 발명의 반도체 패키지 제조용 부재의 제조방법은:Method for manufacturing a semiconductor package manufacturing member of the present invention for achieving the above object is:
소정의 크기와 두께를 갖는 히트싱크를 제공하는 단계와;Providing a heat sink having a predetermined size and thickness;
상기 히트싱크상에 반도체 패키지 영역을 나누어주는 슬롯홀과, 각 공정에서 고정수단이 삽입되는 가이드홀을 스탬핑수단으로 관통되게 형성하는 단계와;Forming a slot hole for dividing the semiconductor package region on the heat sink and a guide hole into which the fixing means is inserted in each process through the stamping means;
상기 히트싱크상의 반도체 패키지 영역에 회로필름을 부착시키되, 칩이 부착되는 영역을 제외하고 부착시키는 단계와;Attaching a circuit film to a semiconductor package region on the heat sink, except for a region to which a chip is attached;
상기 히트싱크상의 칩 부착영역과, 반도체 패키지 영역을 제외한 영역을 하프에칭 처리하는 단계로 이루어진 것을 특징으로 한다.And half-etching the chip attaching region and the semiconductor package region except for the heat sink.
여기서 본 발명의 실시예를 첨부한 도면에 의거하여 보다 상세하게 설명하면 다음과 같다.Hereinafter, the embodiments of the present invention will be described in detail with reference to the accompanying drawings.
첨부한 도 1은 본 발명에 따른 반도체 패키지 제조용 부재의 제조방법을 순서대로 나타낸 도면으로서, 소정의 크기와 두께를 갖는 동 재질의 히트싱크(14)를 구비하는 단계(210)를 선행하여 진행시키게 된다.1 is a view showing a method of manufacturing a semiconductor package manufacturing member according to the present invention in order, proceeding step (210) having a heat sink 14 of the same material having a predetermined size and thickness in advance. do.
다음으로, 상기 히트싱크(14)상에 각각의 반도체 패키지 영역을 나누어주는 슬롯홀(18)과, 각 공정에서 핀과 같은 고정수단이 삽입되는 가이드홀(20)을 스탬핑수단으로 관통되게 형성하는 단계(220)를 진행하게 된다.Next, slot holes 18 for dividing each semiconductor package region on the heat sink 14 and guide holes 20 through which fixing means such as fins are inserted are formed to penetrate through the stamping means. Step 220 proceeds.
좀 더 상세하게는, 상기 반도체 패키지 영역은 일방향으로 다수개가 스트립 형태로 형성된 것으로서, 각 반도체 패키지 영역의 사방에 상기 슬롯홀(18)이 스탬핑으로 형성되고, 골격 역할을 하는 슬롯홀(18)의 바깥쪽 영역은 사이드레일(22)로서, 이 사이드레일(22)면에도 스탬핑에 의하여 소정 간격의 가이드홀(20)이 형성된다.More specifically, the semiconductor package regions are formed in a strip shape in a plurality of directions in one direction, and the slot holes 18 are formed by stamping on each side of each semiconductor package region, and the slot holes 18 serve as a skeleton. The outer region is a side rail 22, and guide holes 20 at predetermined intervals are formed on the side rail 22 by stamping.
다음으로, 상기 히트싱크(14)상의 반도체 패키지 영역에 회로필름(12)을 부착시키는 단계(230)를 진행시키되, 칩 부착용 홈(16)이 형성될 영역을 제외하고 부착시키게 된다.Next, the step 230 of attaching the circuit film 12 to the semiconductor package region on the heat sink 14 is performed, except for the region where the chip attaching groove 16 is to be formed.
한편, 상기 회로필름(12)은 베이스층인 수지필름(30)과; 이 수지필름(30)상에 식각 처리된 전도성패턴(28)과; 이 전도성패턴(28)들중에 와이어 본딩용 그리고 인출단자 부착용 전도성패턴이 외부로 노출되도록 수지필름(30)상에 도포된 커버코트(32)로 구성되어 있다.On the other hand, the circuit film 12 is a resin film 30 and the base layer; A conductive pattern 28 etched on the resin film 30; Among the conductive patterns 28, a cover coat 32 is applied on the resin film 30 so that the conductive patterns for wire bonding and the lead terminal attachment are exposed to the outside.
다음으로, 상기 회로필름(12)이 부착되지 않은 히트싱크(14)상의 칩 부착용 홈(16)이 형성될 영역과, 상기 가이드홀(20)을 포함하는 사이드레일(22) 영역에 걸쳐 에칭 처리하는 단계(240)를 진행시킴으로써, 본 발명의 반도체 패키지 제조용 부재(10)가 완성되는 바, 이때 상기 칩 부착용 홈(16)은 하프 에칭되어 사각홈 형태로 형성되고, 상기 가이드홀(20)이 형성된 사이드레일(22)면도 하프에칭되어 그 두께가 감소된다.Next, an etching process is performed over a region where a chip attaching groove 16 is formed on the heat sink 14 to which the circuit film 12 is not attached, and a side rail 22 region including the guide hole 20. By proceeding to step 240, the semiconductor package manufacturing member 10 of the present invention is completed, wherein the chip mounting groove 16 is half-etched to form a rectangular groove, the guide hole 20 is The formed side rail 22 surface is also half etched to reduce its thickness.
따라서, 상기 회로필름(12)이 종래의 마스크(26) 역할을 대신하여 수행하기 때문에, 종래에 마스크(26)를 부착하고 떼어내는 등의 공정이 배제되어진다.Therefore, since the circuit film 12 performs the role of the conventional mask 26, the conventional process such as attaching and detaching the mask 26 is excluded.
여기서, 상기와 같은 본 발명의 반도체 패키지 제조용 부재를 이용하여, 제조된 반도체 패키지를 첨부한 도 4를 참조로 설명하면 다음과 같다.Herein, referring to FIG. 4 to which the manufactured semiconductor package is attached using the above-described member for manufacturing a semiconductor package of the present invention, the following is described.
상기 부재(10)의 칩 부착용 홈(16)에 반도체 칩(24)을 삽입하여 접착수단으로 부착하는 단계와; 상기 반도체 칩(24)의 본딩패드와, 상기 부재(100)의 와이어 본딩영역간을 와이어(36)로 본딩하는 단계와; 상기 반도체 칩(24)과 와이어(36)등을 코팅재(42)로 인캡슐레이션하되, 코팅재(42)의 바깥쪽 흐름을 차단하기 위하여 인캡슐레이션 영역 라인을 따라 댐(40)을 먼저 형성하여 인캡슐레이션하는 단계와; 부재(10)의 인출단자 부착용 전도성패턴에 전도성의 솔더볼과 같은 인출단자(34)를 부착하는 단계를 거침으로써, 도 4의 반도체 패키지(100)로 제조되어진다.Inserting a semiconductor chip (24) into the chip attaching groove (16) of the member (10) and attaching it with an adhesive means; Bonding a bonding pad of the semiconductor chip 24 to a wire bonding region of the member 100 with a wire 36; The encapsulation of the semiconductor chip 24 and the wire 36, etc. with the coating material 42, but the dam 40 is first formed along the encapsulation area line to block the flow of the coating material 42 outside. Encapsulating; The semiconductor package 100 of FIG. 4 is manufactured by attaching a lead terminal 34 such as a conductive solder ball to a lead pattern for attaching the lead terminal of the member 10.
이상에서 본 바와 같이, 본 발명에 따른 반도체 패키지 제조용 부재의 제조방법에 의하면, 종래에 히트싱크에 에칭되지 않은 영역에 마스크를 부착하고, 다시 떼어내는 공정등을 배제하고, 회로필름이 직접 마스크 역할을 할 수 있도록 함으로써, 히트싱크에 회로필름을 부착하여 이루어진 반도체 패키지 제조용 부재의 제조공정수를 줄여서 작업효율을 향상시킬 수 있고, 또한 마스크의 사용이 배제됨에 따라 제조원가와 제조시간을 감소시킬 수 있는 잇점이 있다.As described above, according to the method for manufacturing a semiconductor package manufacturing member according to the present invention, a circuit film acts directly as a mask, excluding a process of attaching a mask to a region not conventionally etched in a heat sink and removing it again. By reducing the number of manufacturing steps of the semiconductor package manufacturing member formed by attaching a circuit film to the heat sink, the working efficiency can be improved, and the manufacturing cost and manufacturing time can be reduced by eliminating the use of a mask. There is an advantage.
Claims (1)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2000-0073057A KR100401146B1 (en) | 2000-12-04 | 2000-12-04 | Manufacturing method of substrate for manufacturing semiconductor package |
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| KR10-2000-0073057A KR100401146B1 (en) | 2000-12-04 | 2000-12-04 | Manufacturing method of substrate for manufacturing semiconductor package |
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| KR100401146B1 true KR100401146B1 (en) | 2003-10-10 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62214645A (en) * | 1986-03-14 | 1987-09-21 | Hitachi Chem Co Ltd | Semiconductor device |
| JPH04116958A (en) * | 1990-09-07 | 1992-04-17 | Nec Corp | Pin grid array type semiconductor device |
| JPH05144979A (en) * | 1991-11-25 | 1993-06-11 | Sumitomo Bakelite Co Ltd | Manufacture of semiconductor loading substrate |
| JPH05152496A (en) * | 1991-11-28 | 1993-06-18 | Sumitomo Bakelite Co Ltd | Semiconductor loaded board |
| JPH05175407A (en) * | 1991-12-25 | 1993-07-13 | Sumitomo Bakelite Co Ltd | Semiconductor mounting board |
-
2000
- 2000-12-04 KR KR10-2000-0073057A patent/KR100401146B1/en not_active IP Right Cessation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62214645A (en) * | 1986-03-14 | 1987-09-21 | Hitachi Chem Co Ltd | Semiconductor device |
| JPH04116958A (en) * | 1990-09-07 | 1992-04-17 | Nec Corp | Pin grid array type semiconductor device |
| JPH05144979A (en) * | 1991-11-25 | 1993-06-11 | Sumitomo Bakelite Co Ltd | Manufacture of semiconductor loading substrate |
| JPH05152496A (en) * | 1991-11-28 | 1993-06-18 | Sumitomo Bakelite Co Ltd | Semiconductor loaded board |
| JPH05175407A (en) * | 1991-12-25 | 1993-07-13 | Sumitomo Bakelite Co Ltd | Semiconductor mounting board |
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| KR20020043397A (en) | 2002-06-10 |
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