JPH04116958A - Pin grid array type semiconductor device - Google Patents

Abstract

PURPOSE:To dispense with a solder dip process and to suppress the generation of a failure with time of wettability of solder by a method wherein a conductor circuit and grid pins are electrically connected with each other and are fixed via local conductive paths, which are formed by pressure welding and deforming an anisotropic conductive film. CONSTITUTION:An anisotropic conductive film 4 is applied all over the whole surface of a wiring board 1 excluding the formation part of a recess 1a for semiconductor chip mounting use in the board 1 and rid pins 2 are inserted in through holes in such a way as to break through this film 4. Moreover, the pins 2 are firmly bonded in a connection process for applying a local pressure to the heads of the pins 2 under a high temperature (about 180 deg.C). When this connection process ends, local conductive paths, through which fellow conductive particles are connected with each other, are formed only on parts, which are located in the vicinities of the pins 2 and are pushed by the heads of the pins 2, of the film 4. As a result, the pins 2 and a copper foil wiring 5 on the substrate can be respectively connected independently and electrically with each other in a state that an insulation property is held between the pins 2 and the other pins 2 adjacent to the pins 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application 1] The present invention relates to a pin grid array type semiconductor device, and particularly to an electrical connection structure between grid pins and package substrate wiring.

[Conventional technology]

FIG. 5 is a sectional view showing an electrical connection structure between a package wiring board and grid pins in a conventional pin grid array type semiconductor device. As is clear from this figure, the diameter of the through hole in the package wiring board l is formed slightly larger than the diameter of the board insertion part of the grid pin 2, and the grid pin 2 is first mechanically temporarily fixed in the through hole by pressing. After that, it is fixed using the so-called solder dip method, in which it is immersed in solder melt. [For example, JP-A-61-104651
Japanese Patent Laid-Open No. 62-257754 relating to ``Method for soldering lead terminals of r-pin grid array package'' and ``Semiconductor mounting board.''

JP-A-62-257755, JP-A-62-26685
8, JP-A No. 63-285961].

[Problem to be solved by the invention]

At this time, the surface of the grid pin 2 made of copper or iron-nickel metal wire that is temporarily fixed mechanically in the through hole of the package wiring board is usually soldered. This solder plating film will melt during the solder dipping process after temporary fixing, so even if the solder plating thickness is initially applied to a considerable thickness,
After the solder dip process, the thickness often ends up being only about 1 μm. When the solder thickness becomes this thin, problems occur in solder wettability due to surface oxidation, which often causes oven failures when mounting on printed circuit boards.

In view of the above circumstances, an object of the present invention is to provide a pin that solves the problem of the conventional grid pin connection structure that causes deterioration of the solder wettability of the grid pin over time during the electrical connection stage between the package wiring board and the grid pin. An object of the present invention is to provide a grid array type semiconductor device.

[Means for Solving the Problems] According to the present invention, a pin grid array type semiconductor device has the following features:
A package wiring board having a recess for mounting a semiconductor chip and a conductor circuit on the substrate, a semiconductor chip placed in the recess for mounting the semiconductor chip, and a protrusion connected to the conductor circuit on the back side of the package wiring board. In a pin grid array type semiconductor device comprising a plurality of grid pins arranged in an array, the conductor circuit and the grid pins are electrically connected and fixed via local conductive paths formed by pressure contact deformation of an anisotropic conductive film. It consists of:

[Function J According to the present invention, the 1!4 foil wiring of the package wiring board and the grid pins are connected by local conductive paths formed by an anisotropic conductive film instead of the conventional dip solder. This eliminates the need for the conventional solder dip process. Therefore, the solder plating film thickness does not melt from the grid pin surface, which was a problem in the past, and the initial plating thickness can be left as is, which fundamentally solves the problem of poor solder wettability over time. obtain.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

1 and 2 are a sectional view of an electrical connection structure between a package wiring board and grid pins of a pin grid array type semiconductor device and an enlarged view of the vicinity of the grid pins, respectively, showing an embodiment of the present invention. According to this embodiment, a copper-clad laminated insulating board made of glass cloth epoxy, glass cloth triazine, or glass cloth polyimide is used for the package wiring board l, and a recess la for mounting a semiconductor chip is provided near the center of the copper-clad laminated insulating board. Furthermore, through holes and wiring circuits for connecting the bonding wires to the grid pins 2 are formed at the ends, respectively. Here, an anisotropically conductive film 4 is stretched over the entire surface of the wiring board 1 except for the area where the recess 1a for mounting the semiconductor chip is formed, and the grid pins 2 are arranged so that the grid pins 2 break through this anisotropically conductive film 4 into the through holes. inserted, and further local pressure is applied at high temperature (approximately 18
It is fixed in the connection process by attaching it to the head of the grid pin 2 at 0°C). After this connection process is completed, the anisotropically conductive film 4 near the grid pin has conductive particles that are mutually connected only in the portion pushed by the head of the grid pin 2, as is clear from the enlarged view in FIG. Since a local conductive path is formed that connects each other, the grid pins 2 and the copper foil wiring 5 on the board can be electrically connected independently while maintaining insulation with other adjacent grid pins 2. can do. At this time, the thickness of the anisotropic conductive film 4 is set to 0.5 to 1.0 mm, taking into consideration conductivity, adhesion, etc. OIlm and grid pin 2
A solder plating film 2a is applied in advance to a thickness (5 to 8 um) that does not cause deterioration of solder wettability over time. Here, 6 and 7 indicate the solder resist and the nickel-gold plating film of the substrate copper foil wiring 5, respectively.

The relationship between the through hole diameter and the grid pin diameter in this embodiment is completely arbitrary. In other words, by making the grid pin diameter smaller than the through-hole diameter, you can prevent a large force from being applied to the through-hole, and on the other hand, by making the grid pin diameter slightly larger, the mechanical force caused by indentation will be reduced by the adhesive force of the film. The mounting strength can be increased by adding supporting force, so it can be selected as appropriate.

FIG. 3 is a sectional view of an electrical connection structure between a package wiring board and grid pins showing another embodiment of the present invention. In this example, an anisotropic conductive film 4 is applied to the side surface of the board, and electrical connections are made to the internal and surface copper foil wiring using clip-type grid pins 2, similar to the previous example. It is possible to be effective.

As is clear from the above embodiments, according to the present invention, the electrical connection between the package wiring board and the grid pins is achieved through local conductive paths formed by the anisotropically conductive film. That is, since the conventional dip soldering process is completely unnecessary, there is no change in the thickness of the solder plating originally formed on the grid pins.

FIG. 4 is a graph showing the characteristics of grid pin solder wettability over time during high-temperature storage, showing the effects of the present invention in comparison with a semiconductor device having a conventional structure. In this experiment, changes in zero cross time at a high temperature of 150° C. were recorded over 500 hours, and if data A of the semiconductor device of the present invention is compared with data B of the conventional semiconductor device, the difference between the two is obvious.

〔Effect of the invention〕

As described in detail above, according to the present invention, the wiring on the board and the grid pins are connected to each other through local conductive paths formed by pressure-welded anisotropic conductive films, without using the conventional solder dip process. All pins are electrically connected independently. Therefore, the thickness of the solder plating initially formed on the grid pins can remain as is, so the solder wettability does not deteriorate over time, and the pin grid array type semiconductor device can be stored for a long time. can be provided.

[Brief explanation of drawings]

1 and 2 are a cross-sectional view of an electrical connection structure between a package wiring board and a grid pin and an enlarged view of the vicinity of the grid pin, respectively, showing one embodiment of the present invention, and FIG. 3 is another embodiment of the present invention. FIG. 4 is a cross-sectional view of an electrical connection structure between a package wiring board and a grid pin showing an example; FIG. FIG. 5 is a sectional view showing an electrical connection structure between a package wiring board and grid pins in a conventional pin grid type semiconductor device. ■...Package wiring board, la...Semiconductor chip mounting recess, 2...Grid pin, 2a...Solder plating film, 4...Anisotropic conductive film, 5...On board Copper foil wiring, 6...Solder resist, 7...Nickel-gold plating film.

Claims (1)

[Claims] A package wiring board having a recess for mounting a semiconductor chip and a conductor circuit on the substrate, a semiconductor chip placed in the recess for mounting the semiconductor chip, and a protrusion connected to the conductor circuit on the back side of the package wiring board. In a pin grid array type semiconductor device comprising a plurality of grid pins arranged in an array, the conductor circuit and the grid pins are electrically connected and fixed via local conductive paths formed by pressure contact deformation of an anisotropic conductive film. A pin grid array type semiconductor device characterized by: