KR20020002339A - Merged capacitor and capacitor contact process for concave shaped stack capacitor drams - Google Patents

Abstract

PURPOSE: A DRAM cell and its fabrication method are provided to reduce the number of critical photolithography steps and reduce the aspect ratio of bit line and capacitor conductive contacts. CONSTITUTION: A method for fabricating a semiconductor memory device comprises the steps of : (a) providing a semiconductor substrate comprising at least one transistor, the transistor comprising a source, a drain, and a gate. (b) depositing a first insulating layer having an upper surface over the transistor, (c) forming at least one electrical contact extending from one of the source and the drain through the first insulating layer to the upper surface of the first insulating layer, (d) forming a bit line layer comprising a first and a second approximately parallel bit lines over the first insulating layer, the bit lines spaced to define an area between the first and second bit lines, and (e) forming at least one stacked capacitor in the area between the first and second bit lines, the stacked capacitor extending through the bit line layer to the electrical contact.

Description

MERGEED CAPACITOR AND CAPACITOR CONTACT PROCESS FOR CONCAVE SHAPED STACK CAPACITOR DRAMS}

BACKGROUND OF THE INVENTION Field of the Invention The present invention relates generally to stacked capacitors of concave shape in DRAM cells, and more particularly to stack capacitors coplanar with bit lines and directly merged with electrical contacts in DRAM cells.

Advances in the state-of-the-art semiconductor industry require increasing the memory density and performance of semiconductor devices. This goal is sometimes achieved by adjusting a dynamic random access memory (DRAM) device to have a smaller size and operate at a smaller operating voltage. Miniaturization devices embedded in semiconductor substrates are spaced very close together and their packing density is significantly increased.

In general, each DRAM storage cell consisting of one metal-oxide-semiconductor field effect transistor (MOSFET) and one capacitor is widely used in the electronics industry to store data. One DRAM cell stores one bit of data in a capacitor with electrical charging. Metallization in contact with the semiconductor substrate is referred to as contact metallization. In MOS devices, the polysilicon film is a form of metallization that is used as the interconnect and gate of the MOS device. The inability to further miniaturize contact metallization is a major obstacle to DRAM miniaturization.

As DRAM density increases (over 1 MEGA range), thin film capacitors, such as stacked capacitors, trenched capacitors, or a combination thereof, have been deployed to meet minimum space requirements. Many of these designs are sophisticated and difficult to produce consistently and efficiently.

Efforts are being made to develop ways to fabricate interconnects and capacitors that minimize manufacturing costs and maximize device yield. In particular, efforts are being made to minimize the number of photoresist masking operations and to provide a method for providing maximum processing overlay tolerance to maximize production yield. Typically, two mask / etch steps are performed to form conductor connections to bit lines and node contacts in DRAM fabrication. Moreover, contact holes through the thick insulating layer create high aspect ratios (3 or more) that make contact etch processing difficult, resulting in reduced device yields due to the resulting etch defects.

Therefore, there is a need for DRAM cells and fabrication methods that reduce the number of major photolithography steps and reduce the aspect ratio of bit lines and capacitor conductive contacts.

In order to satisfy these and other needs, the present invention provides a semiconductor memory device having a semiconductor substrate including at least one transistor. The transistor has a source, a drain, and a gate. The device also has a first insulating layer having a top surface over the array of transistors. At least one electrical contact extends from one of the source and the drain to the top surface of the first insulating layer. The bit line layer includes at least one stacked capacitor in the area between the first and second bit lines, the first and second bit lines being substantially parallel over the first insulating layer and spaced therebetween to define an area therebetween. Equipped. The stack capacitor extends to the electrical contact through the bit line layer.

According to the invention, there is also provided a method of fabricating a semiconductor memory device on a semiconductor substrate, which:

a) providing a semiconductor substrate comprising at least one transistor, the transistor comprising a source, a drain, and a gate;

b) depositing a first insulating layer having a top surface over said transistor;

c) forming at least one electrical contact extending from one of the source and the drain to the top surface of the first insulating layer through the first insulating layer;

d) forming a bit line layer having first and second bit lines substantially parallel over said first insulating layer and spaced to define an area therebetween; And

e) forming at least one stack capacitor in said area between said first and second bit lines, said stack capacitor extending through said bit line layer to said electrical contact;

It includes.

1 is an electrical equivalent circuit diagram of a DRAM cell.

Fig. 2 is a top view of the device according to the present invention illustrating the relative positions of active areas where transistors are formed, the positions of capacitors, and bit lines and word lines having memory devices.

3 is a top view of a device according to another embodiment of the present invention illustrating the relative positions of active areas where transistors are formed, the positions of capacitors, and bit lines and word lines having memory devices.

4 is a structural elevation view of a memory storage device in accordance with the present invention showing a substrate with transistors forming the storage device during a process of fabricating a complete device.

FIG. 5 shows the structure of FIG. 4 after the structure is complete; FIG.

6 illustrates another embodiment of a DRAM structure according to the present invention.

<Explanation of symbols for the main parts of the drawings>

BL, 36: bit line

WL, 16: word line

SW: switching transistor

22: first insulating layer

10: Substrate

28: electrical contacts

42: storage capacitor

43: active area

The fabrication process is now given in detail that is used to create a high density DRAM cell structure having a stacked capacitor formed coplanar with the bit lines and merged with the electrical contacts. The DRAM device described in the present invention is composed of N channel transfer gate transistors. If desired, the present invention can be used to create a DRAM cell consisting of a P channel transfer gate transistor. This can be done by creating an N well region in the P-type semiconductor substrate and creating a P-type source and drain region between the polycide gate structures in the semiconductor substrate.

1 is an electrical circuit showing a basic element of a DRAM cell. This is a switching transistor, typically a MOS FET having a drain (D), a source (S), and a gate (G, G). The storage capacitor C, the word line WL, and the bit line BL are associated with the transistor. A number of such structures are arranged along a pattern on a substrate that is accessiblely interconnected outside the substrate through an array of bit lines and word lines.

2 is a top view of a substrate 10 having an array of DRAM cells constructed in accordance with the present invention, which is used to illustrate the present invention. A plurality of parallel bit lines 36 BL1, BL2, BL3 are shown arranged in space at regular intervals from each other. A second array of word lines 16 WL1 through WL4 extending perpendicular to the array of bit lines 36 is shown below the bit line layer. The word line layer is insulated with a space from the bit line layer so that there is no electrical contact between the word line and the bit line crossing each other. A number of storage capacitors 42 are shown in the space between the bit line and the word line.

In its simplest form, a switching transistor for each DRAM cell is formed in the active region 45 which is approximately bordered by a black dotted line on the substrate 10. Within the active region are the drain, gate, and source of the transistor. The connector 32 extends from the bit line 36 to the source of the transistor. Capacitor 42 is connected to the drain of the transistor as will be described later.

3 is another embodiment of the present invention, as is more common in a high density DRAM cell structure, two capacitors may be connected to the same bit line. In this case, the active region shown in bold lines extends to the second capacitor. A second transistor having a common source structure is used to connect this second capacitor to the bit line, as will be shown in more detail below.

Next, referring to FIG. 4, a structural elevation view of a single DRAM cell on a substrate constructed in accordance with the present invention prior to formation of a storage capacitor is shown. A switching transistor having a source region 20, a drain region 12, and a gate substrate 15 is formed on a substrate 10, which is typically a semiconductor substrate, according to known techniques. The gate structure includes a gate electrode 14 connected to the word line 16. Sidewall spacers 17, which are silicon nitride, are also typically included as part of the gate structure. Thermal oxide layer 11 and doped polysilicate layer 13 may also be included as part of the substrate.

The transistor is covered with a first insulating layer 22 deposited thereon at a thickness of 3,000 Å to 10,000 Å, filling the region between the gate structures. The first insulating layer 22 may include an insulating material such as boron phospho-silicate glass (BPSG). The first insulating layer 22 is flattened by chemical mechanical polishing (CMP) to form the first top surface 27.

Continuing with reference to FIG. 4, the electrical contact 28 is then formed through a starting lithographic anisotropic RIE process. RIE etchant such as C ₂ F ₈ -CF ₄ -CHF ₃ is used to selectively remove the BPSG layer 22 and the oxide layer 11 to form electrical contact vias. The vias are approximately 0.1 μm to 0.1 μm in area and are spaced about 0.2 μm apart. N-type doped polysilicon is then deposited to fill the contact vias to form electrical contacts 28. The doped polysilicon is flattened to the first top surface 27 by CMP. These electrical contacts 28 are in turn connected directly to the storage capacitor electrodes. In this structure the storage capacitor is a stacked capacitor structure and the contacts are connected to the bottom electrode. Alternatively, the contact 28 can be connected to the bit line contact 32. Thus, the DRAM cell of the present invention provides an electrical connection from the capacitor to the substrate in a single photolithographic RIE etch step upon formation of the electrical contact 28.

Once electrical contact is made, the first top surface 27 is covered with a second insulating layer 30 that is between 200 and 3000 microns thick. The second insulating layer provides a second top surface 31. The second insulating layer may include an insulating material such as tetraethoxysilane (TEOS) and BPSG. Subsequently, ion implantation is performed to dope the source 20 and drain 12 heavily in the region.

The bit line contact part 32 is formed in the second insulating layer 30. Bit line contact vias are formed through photolithography anisotropic reactive ion etching. The via etch extends from the second top surface 31 through the second insulating layer 30 to the first top surface 27. The via is connected to one of the electrical contacts 28 that extends from the substrate to the source region 20. The bit line contact vias are approximately 0.1 μm to 0.1 μm in area and are connected to electrical contacts between the active word lines 16.

In the subsequent photolithographic anisotropic etching step, support vias 34 are formed outside the array region. The support via 34 consequently connects the bit line to the sense amplification region of the DRAM cell. A support via 34 extending from the second top surface 31 through the second insulating layer 30 continues down through the first insulating layer 22. While both the bit line contact 32 and the support via 34 are etched from the second top surface 31, the support via 34 has to be etched significantly deeper than the bit line contact via 32 so that the etching step is separate. Is etched.

Continuing with reference to FIG. 4, conductive material is deposited on the etched bit line contact vias 32 and support vias 34. The conductive material fills the via to form conductive layer 36. Conductive layer 36 may be from 1000 Å to 3,000 두께 thick and may be deposited through CVD, LPCVD, or other known deposition processes. Conductive materials include tungsten (W), platinum (Pt), palladium (Pd), lead (Pb), iridium (Ir), gold (Au), rhodium (Rh), ruthenium (Ru), molybdenum (Mo), silver ( Ag), copper (Cu), aluminum (Al), or alloys or mixtures thereof. The conductive material is preferably tungsten.

Continuing with reference to FIG. 4, nitride layer 38 is deposited over conductive layer 36 to a thickness of 100 kV to 1,000 kV through CVD, LPCVD, or any known deposition process. The nitride layer 38 and the conductive layer are etched through the photolithographic anisotropic RIE to form bit lines. The etched bit lines are approximately parallel and 0.1 μm wide. An array of bit lines defines the space between each bit line. The space between each bit line is approximately 0.1 μm. A nitride sidewall spacer (41 shown in FIG. 2) is formed on the side of the bit line by a conventional method.

After the bit lines 36 and the bit line side walls are formed, a third insulating layer 40 is deposited between the bit lines and over the conformal layers. The third insulating layer may be BPSG, TEOS, spin on glass (SOG), or organic polymer. The third insulating layer 40 is planarized using chemical mechanical polishing (CMP), and a capacitor cavity is formed in the insulating material between the bit lines through conventional photolithographic anisotropic RIE treatment.

Figure 5 shows a structural elevation view of a DRAM structure with storage capacitors in place in accordance with the present invention. The capacitor cavity may be formed such that its opening is on the same plane as the top surface of the bit line 36. Alternatively, the capacitor cavity may be formed such that its opening is on the same plane as the layer deposited over the bit line layer 40, as shown in FIG. The capacitor opening is located in the region between the bit lines. The space between the bit lines determines the area of insulating material available to form the capacitor cavity. The capacitor cavity 42 is formed to extend from the top surface of the device through the bit line layer and the second insulating layer 30 to the electrical contact 28 at the first top surface 27. Capacitor cavity 42 is substantially aligned with electrical contact 28. The dimension of the capacitor cavity is determined in part by the space between the bit lines. The capacitor cavity is formed such that the insulating material is etched away leaving the bit lines and nitride sidewalls intact. The capacitor cavity dimension may be an area of 0.02 μm ² to 0.05 μm ² and a depth of 0.1 μm to 1.0 μm. Preferably, the capacitor cavity dimension is approximately 0.3 μm ² in area and 0.2 μm deep.

A diffusion barrier layer 44 is deposited over the third insulating layer 40 with a capacitor cavity. The barrier layer is preferably 200 μs thick and has conductors such as TiN, TaN, TaSiN, WN, AlN, TiAlN, GaN, AlGaN, RuO ₂ , IrO ₂ , and Re ₂ O ₃ . A layer of conductive electrode material 46 is conformally deposited over the diffusion barrier layer. Conductive electrode materials include precious metals including Pt, Pd, Ir, Au, Rh, Ru, Mo, alloys and combinations thereof. The conductive material may also include metals such as Ag, Cu, Al, alloys thereof, and combinations thereof. The conductive layer can be composed entirely of diffusion barrier layers. The layer of conductive electrode material may be between about 100 kV and 500 kV thick, preferably 300 kPa. Conductive electrode material 46 is coated with photo-resist and patterned through photolithography. Conductive electrode material 46 and diffusion barrier layer 44 are etched back to second insulating layer 40 outside of the capacitor cavity. The photoresist is removed from the capacitor cavity region and the remaining conductive electrode material 46 and barrier layer material are etched back to match the surface of the third insulating layer 40. The bottom electrode 46 and barrier layer 44 of the stack capacitor are dug in the “U” shape of the stack capacitor due to the etching back of the conductive electrode material and the diffusion barrier material.

The capacitor dielectric layer 48 is deposited conformally on the third insulating layer 40 and the capacitor cavity to cover the bottom electrode 46. And the same oxide thickness of the capacitor dielectric layer has a thickness of 20Å to 200Å, preferably having a high dielectric constant such as _{(Ba, Sr (TiO 3)} ), BaTiO 3, SrTiO 3, PbZrTiO 3, PbZrO 3, PbLaTiO 3, SrBiTaO 3 Material.

Next, another layer of conductive electrode material 50 is deposited over the capacitor dielectric layer 48 to fill the remaining space in the capacitor cavity. Top electrode 50 is planarized to define a stack capacitor structure.

DRAM cells are completed with additional conventional fabrication steps required to form a connection in the sense amplification region of the cell. These steps are not shown in the figure.

As described above, it is sometimes desirable to provide two storage capacitors that are connected one of the two to one bit line through two transistors. 6 illustrates a structural elevation of a DRAM cell structure that provides these characteristics.

As shown in FIG. 6, there are a number of switching transistors each having a source 20 and a drain 12. However, in this structure, it is this common source 20 'that two adjacent transistors SW1, SW2 share a common source 20', and are connected to the bit line 36 via the electrical contact 28. This arrangement allows access to either storage capacitor C1 or C2 through activation of SW1 or SW2.

The device top view shown in FIG. 3 can be used to illustrate the organization of the bit line 36, the word line 16, the capacitor 42, and the bit line contacts 32. The bit line contact 32 operates to connect the bit line to the source region. Each source region 20 is associated with at least one active word line. The bit line contacts allow the signal from the bit line to activate and read each storage capacitor. The portion of the device that is not formed over the insulating region in the substrate is referred to as the active area of the device. Exemplary active area 43 includes two capacitors C1 and C2, two active word lines WL2 and WL3, bit line BL2, and bit line contact 32. As shown in FIG. In the active area 43, the charge stored in C1 is opened and closed to BL2 through WL2, and is connected by the bit line contact 32. The same bit line contact connects BL2 to the WL3 gate to read the charge stored in C2.

Fabrication processes used to create high density DRAM cell structures having stacked capacitors coplanar with the bit lines and incorporated with electrical contacts have been described in detail. Therefore, it is possible to reduce the number of major photolithography steps and to reduce the aspect ratio of the bit line and capacitor conductive contacts.

Although the present invention has been shown and described above with reference to specific embodiments, it is nevertheless not intended to be limited to the details shown. In addition, various modifications may be made in the details within the same scope as the claims without departing from the spirit of the invention.

Claims (12)

i) a substrate comprising at least one transistor comprising a source, a drain, and a gate; ii) a first insulating layer having a top surface and disposed on said transistor; iii) at least one electrical contact extending from one of the source and the drain to the top surface of the first insulating layer; iv) a bit line layer comprising first and second bit lines on said first insulating layer, substantially parallel to one another and spaced to define an area therebetween; And v) at least one stacked capacitor in said area between said first and second bit lines, said stack capacitor extending through said bit line layer to said electrical contact; Semiconductor memory device comprising a. The method of claim 1, A second insulating layer between the bit line layer and the first insulating layer, and A bit wire plug extending through the second insulating layer to one of the electrical contacts The semiconductor memory device further comprising. The method of claim 2, And the second insulating layer comprises boron-phosphorus silicate glass (BPSG), tetraethosiloxane (TEOS), or any mixture thereof. The method of claim 1, Each of the bit lines comprises a side wall and a silicon nitride spacer on the side wall. The method of claim 1, And a third insulating layer over the bit line layer, wherein the stack capacitor extends through the third insulating layer and the bit line layer. The method of claim 5, And the third insulating layer comprises boron-phosphorus silicate glass (BPSG). The method of claim 1, The source and drain are formed in the substrate. The method of claim 1, And the first insulating layer comprises boron-phosphorus silicate glass (BPSG). The method of claim 1, And the contact portion comprises doped polysilicon. The method of claim 1, And the first and second bit lines comprise tungsten. In a method of fabricating a semiconductor memory device on a semiconductor substrate: a) providing a semiconductor substrate comprising at least one transistor comprising a source, a drain, and a gate; b) depositing a first insulating layer having a top surface and disposed on the transistor; c) forming at least one electrical contact extending from one of the source and the drain through the first insulating layer to the top surface of the first insulating layer; d) forming a bit line layer on said first insulating layer, said bit line layer comprising first and second bit lines disposed substantially parallel to one another and spaced therebetween to define an area therebetween; And e) forming at least one stack capacitor in said area between said first and second bit lines, said stack capacitor extending through said bit line layer to said electrical contact; How to include. The method of claim 11, a) providing at least one transistor on said semiconductor substrate, said transistor comprising a source, a drain, and a gate; b) forming sidewall spacers and caps surrounding the transistors; c) depositing a first insulating layer over the transistor; d) forming at least one contact extending from one of the source and the drain to the top surface of the first insulating layer; e) planarizing the first insulating layer and the cap to form a first top surface; f) providing and etching at least one electrical contact to the first insulating layer using photolithography to form a contact via extending from the substrate to the first top surface, the doped poly Depositing a silicon layer to fill the contact vias with doped polysilicon and planarizing the doped polysilicon layer to the first top surface; g) depositing a second insulating layer over the first top surface to form a second top surface; h) forming and etching at least one bit line contact and support contact using photolithography to extend the bit line contact via from the contact to the second top surface and the support via extending from the substrate to the second top surface. forming a support via and depositing a first metal layer to fill the bit line contacts and the support via with a metal material; i) depositing at least one bit line by depositing a first nitride layer on said first metal layer using photolithography, etching said nitride layer and said first metal layer to define said bit line, Forming a nitride sidewall spacer on at least one side; j) depositing a third insulating layer to form a third top surface; And k) using photolithography to form a set of concave stack capacitors and etching capacitor cavities-the cavities extending from the third top surface to the first top surface through the second and third insulating layers Wherein the cavity is formed between the bit lines, to deposit a diffusion barrier layer, to deposit a first electrode layer, and to remove the barrier layer and the first electrode layer from the third top surface. Etching a barrier layer and the first electrode layer to define a node electrode, depositing a capacitor dielectric layer, depositing a second electrode layer and etching the second electrode layer to define a ground electrode How to include more.