JP2002050701A - Merged capacitor and capacitor contact process for concave shaped stacked capacitor dram - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DRAM cell which eliminates critical photolithorgraphic fabrication steps by merging stacked capacitor construction with electrical contacts, and to provide a method of fabrication thereof. SOLUTION: It is sufficient to conduct in one lithography step to form electrical contacts, because the stacked capacitors are on the same plane as bit lines and the stacked capacitors are located in a insulating material provided between the bit lines. Unlike the conventional capacitor-over-bit line(COB) DRAM cells having the capacitors on the bit lines, this DRAM cell having capacitors adjacent to the bit lines eliminates the need to have dedicated contacts in the capacitor, making it possible to realize higher capacitance with lower global topography.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention generally relates to a DRAM.
It relates to a concave stacked capacitor in a cell, and more particularly to a stacked capacitor coplanar with a bit line in a DRAM cell and merged directly with an electrical contact.

[0002]

BACKGROUND OF THE INVENTION Advances in the state of the art in the semiconductor industry require increasing the memory density and performance of semiconductor devices. These goals are often dynamic
This is achieved by reducing random access memory (RAM) devices to smaller dimensions and lower operating voltages. Small devices fabricated in and on semiconductor substrates are closely spaced and their packing density has increased significantly.

[0003] Individual DRAM storage cells typically include a single metal oxide semiconductor field effect transistor (MOS-FE).
T) and a single capacitor and are widely used for storing data in the electronics industry. Single DR
The AM cell stores 1-bit data as a charge in a capacitor. Metallization in contact with a semiconductor substrate is called contact metallization. In MOS devices, polysilicon films have been a form of metallization used for gates and interconnects in MOS devices. The inability to further reduce this contact metallization (i.e., the first level interconnect) is a major obstacle to DRAM miniaturization.

As DRAM densities have increased (over 1 meg), stacked and trench capacitors,
Alternatively, thin film capacitors, such as combinations thereof, have evolved in an attempt to meet minimum space requirements. Many of these designs have become sophisticated and difficult to manufacture consistently and efficiently.

[0005]

One object is to develop a method of manufacturing capacitors and interconnects that minimizes manufacturing costs and maximizes device yield. Specifically, the challenge is to develop methods to minimize the number of photoresist masking operations and to provide maximum process overlay tolerance to maximize product yield. Generally, in DRAM fabrication, two mask / etch steps are performed to make conductor connections to bit lines and node contacts. In addition, contact holes (greater than 3) through the thick insulating layer provide a high aspect ratio, which makes the contact etching process difficult and reduces the yield of the device due to the resulting etching defects.

Therefore, the number of critical photolithography steps is reduced, and the aspect ratio of the bit line to the capacitor conductive contact is reduced,
There is a need for RAM cells and fabrication methods.

[0007]

SUMMARY OF THE INVENTION To meet these and other needs, and in view of that purpose, the present invention provides a semiconductor memory device that includes a semiconductor substrate having at least one transistor. The transistor has a source, a drain, and a gate. The device further comprises a first insulating layer having a top surface on the array of transistors. At least one electrical contact extends from one of the source and the drain to an upper surface of the first insulating layer. The bit line layer includes first and second substantially parallel bit lines on a first insulating layer, wherein the bit lines are spaced apart from the first bit line and the second bit line. And the bit line layer includes at least one stacked capacitor in the region between the first and second bit lines. Stacked capacitors extend through the bit line layers to electrical contacts.

According to the present invention, there is also provided a method for fabricating a semiconductor memory device on a semiconductor substrate, the method comprising: a) a semiconductor substrate including at least one transistor including a source, a drain, and a gate. B) depositing a first insulating layer having a top surface on the transistor; and c) passing the first insulating layer from one of the source and the drain through the first insulating layer. Forming at least one electrical contact extending to a top surface of an insulating layer; d) defining an area on the first insulating layer between the first bit line and the second bit line. Forming a bit line layer including substantially parallel first and second bit lines spaced apart from each other; e) forming the first bit line and the second bit line; The area between the Tsu DOO lines, and forming at least one stacked capacitor extends to the electrical contacts through the bit line layer.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The fabrication process used to create a high density DRAM cell structure having a stacked capacitor formed flush with the bit lines and integrated with electrical contacts will now be described in detail. . The DRAM device described in the present invention comprises an N-channel transfer gate transistor. If desired, the invention can be used to create DRAM cells consisting of P-channel transfer gate transistors. This can be achieved by creating an N-well region in the P-type semiconductor substrate and creating P-type source and drain regions between the polycide gate structures in the semiconductor substrate.

FIG. 1 shows an electrical circuit representing the essential elements of a DRAM cell. These are switching transistors, typically MOS FETs having a drain D, a source S, and a gate G. A storage capacitor C, a word line WL, and a bit line BL are associated with this transistor. Such structures are interconnected and arranged along a pattern on a substrate, accessible from outside the substrate via an array of bit lines and word lines.

FIG. 2 is a top view of a substrate 10 including such an array of DRAM cells constructed in accordance with the present invention, with which the present invention will be described. A plurality of parallel bit lines 36, BL1, BL2, BL3 are shown arranged at regular intervals from one another. A second array of word lines WL1-WL4 extending perpendicular to the array of bit lines 36 is shown below the bit line layer.
The word line layer is spaced and insulated from the bit line layer so that at the intersection of the word line and the bit line, there is no electrical contact between the lines. A plurality of storage capacitors 42 are shown in the space between the bit lines and the word lines.

In its simplest form, the switching transistor for each DRAM cell is formed in an active region 45 of the substrate 10 approximately delimited by a dashed black line. Within this active region is the drain, gate, and source of the transistor. Connector 32 extends from bit line 36 to the source of the transistor.
Capacitor 42 is connected to the drain of the transistor, as described below.

FIG. 3 shows an alternative embodiment of the present invention,
Two capacitors can be alternately connected to the same bit line, which is more common in high density DRAM cell structures. In such a case, the active region 43 indicated by a thick line extends to the second capacitor. As shown in more detail below, a second transistor having a common source structure is used to connect this second capacitor to the bit line.

Referring now to FIG. 4, there is shown a schematic elevational view of a single DRAM cell on a substrate constructed in accordance with the present invention, prior to forming a storage capacitor. A switching transistor having a source region 20, a drain region 12, and a gate structure 15 is formed on a substrate 10, which is typically a semiconductor substrate, by well-known techniques. The gate structure includes a gate electrode 14 connected to a word line 16. In general, sidewall spacers 17 of silicon nitride are also included as part of the gate structure. Thermal oxide layer 11 and doped polysilicate layer 13 can also be included as part of the substrate.

The transistor has an additional 3,000３ ，
It is covered with a first insulating layer 22 filling the area between the deposited gate structures with a thickness of between 10,000 °. The first insulating layer 22 can include an insulating material, such as borosilicate glass (BPSG). The first insulating layer 22 is planarized by chemical mechanical polishing (CMP), so that a first upper surface 27 is formed.

Still referring to FIG. 4, an electrical contact 28 is then formed by photolithography and anisotropic RIE procedures. RI, such as C ₂ F ₈ -CF ₄ -CHF ₃
The BPSG layer 22 and the oxide layer 11 are selectively removed using an E etchant, thereby forming electrical contact vias. These vias have an area of about 0.1 μm ×
0.1 μm, and are arranged at intervals of about 0.2 μm. The contact vias are then filled by depositing polysilicon doped with N-type impurities, thereby forming electrical contacts 28. The doped polysilicon is planarized by CMP to the first upper surface 27.
These electrical contacts 28 will ultimately connect directly to the storage capacitor electrodes. In this structure, the storage capacitor is a stacked capacitor structure, with the contacts connecting to its bottom electrode. Alternatively, contact 28 can be connected to bit line contact 32. Thus, the DRAM cell of the present invention provides an electrical connection from the capacitor to the substrate in a single photolithography and RIE etching step when forming the electrical contact 28.

After the electrical contacts have been formed, the first top surface 27 is covered with a second insulating layer 30 having a thickness of 200-3000 °.
Capping with This second insulating layer provides a second top surface 31. The second insulating layer can include any insulating material, such as tetraethoxysilane (TEOS) or BPSG. Next, ion implantation is performed to dope the source region 20 and the drain region 12 with a high concentration.

A bit line contact 32 is formed on the second insulating layer 30. Bit line contact vias are formed by photolithography and anisotropic reactive ion etching. The etching of the via reaches the first upper surface 27 from the second upper surface 31 through the second insulating layer 30. The via is connected to one of the electrical contacts 28 extending to the source region 20 in the substrate. The bit line contact vias are approximately 0.1 μm × 0.1 μm in area and connect to the electrical contacts between the active word lines 16.

Subsequent photolithography and anisotropic etching steps form support vias 34 outside the array area. Support vias 34 ultimately connect the bit lines to the sensitivity amplification regions of the DRAM cell. The support via 34 extends downward from the second upper surface 31 through the second insulating layer 30 and further into the first insulating layer 22. The bit line contacts 32 and the support vias 34 are both etched from the second top surface 31, but since the support vias 34 must be etched much deeper than the bit line contact vias 32, these vias are separately etched. -Etched in steps.

Still referring to FIG. 4, a conductive material is deposited inside the etched bit line contact vias 32 and support vias 34. The via is filled with a conductive material to form a conductive layer 36. The conductive layer 36
It may be 1,000 to 3,000 mm thick and may be deposited via CVD (chemical vapor deposition), LPCVD (low pressure vapor deposition) or other deposition processes known in the art. it can. The conductive material is tungsten (W), platinum (Pt), palladium (Pd), lead (P
b), iridium (Ir), gold (Au), rhodium (R
h), ruthenium (Ru), molybdenum (Mo), silver (Ag), copper (Cu), aluminum (Al), or alloys and mixtures thereof. Preferably, the conductive material is tungsten.

Still referring to FIG. 4, a nitride layer 38 having a thickness of 1 is formed on conductive layer 36 by CVD, LPCVD, or any deposition process known in the art.
Attached between 00 and 1,000. Nitride layer 38
And the conductive layer are formed by photolithography and anisotropic RI
Etched by E to form bit lines. The etched bit lines are substantially parallel and have a width of about 0.1 μm. By arranging the bit lines, a space is defined between each bit line. The space between each bit line is about 0.1 μm. Nitride sidewall spacers (shown at 41 in FIG. 2) are formed on the side surfaces of the bit lines by conventional methods.

After forming the bit lines 36 and the bit line side walls, a third insulating layer 40 is deposited as a conformal layer between and above the bit lines. The third insulating layer is B
PSG, TEOS, spin-on-glass (SOG),
Alternatively, it may be an organic polymer. The third insulating layer 40 is planarized using chemical mechanical polishing (CMP) and the capacitor cavities are formed in the insulating material between the bit lines by conventional photolithographic and anisotropic RIE processes. Is done.

FIG. 5 shows a schematic elevational view of a DRAM structure according to the present invention having a storage capacitor in place. As mentioned earlier, this capacitor is a stacked capacitor. The capacitor cavity can be formed such that its opening is flush with the top surface of bit line 36. Alternatively, the capacitor cavity can be formed such that its opening is flush with the layer deposited on bit line layer 40, as shown in FIG.
This capacitor opening is positioned in the region between the bit lines. The spacing between the bit lines determines the area of insulating material available to form a capacitor cavity. A capacitor cavity 42 is formed extending from the top surface of the device, through the bit line layer and the second insulating layer 30, and to the electrical contact 28 on the first top surface 27. This capacitor cavity 42 is substantially aligned with the electrical contact 28. The size of the capacitor cavity is determined in part by the space between the bit lines. The capacitor cavity is formed such that the insulating material is etched while the bit lines and nitride sidewalls remain intact. The dimensions of the capacitor cavity are 0.02 μm ²
~ 0.05μm ² , depth 0.1μm ~ 1.0μ
m. The dimensions of the capacitor cavity are preferably about 0.3 μm ² in area and 0.2 μm in depth.

A diffusion barrier layer 44 is deposited over the third insulating layer 40 and within the capacitor cavity. The barrier layer is preferably 200 ° thick, TiN, Ta
N, TaSiN, WN, AlN, TiAlN, GaN,
It includes conductors such as AlGaN, RuO ₂ , IrO ₂ , and Re ₂ O ₃ . A layer of conductive electrode material 46 is conformally deposited on the diffusion barrier layer. Pt, P
Any noble metal, including d, Ir, Au, Rh, Ru, Mo, alloys and combinations thereof, is included. The conductive material is
Metals such as Ag, Cu, Al, their alloys and combination metals can also be included. The conductive layers may all be composed of diffusion barrier layers. The layer of conductive electrode material has a thickness of about 100
It may be between Å and 500Å, preferably about 300Å. The conductive electrode material 46 is covered with a photoresist and is patterned by photolithography. The conductive electrode material 46 and the diffusion barrier layer 44 are etched back to the third insulating layer 40 outside the capacitor cavity. The photoresist is removed from the capacitor cavity area, and the remaining conductive electrode material 46 and barrier layer material are etched back until they match the surface of the third insulating layer 40. Due to the etch back of the conductive electrode material and the diffusion barrier material, the bottom electrode 46 and the barrier layer 44 of the stacked capacitor are recessed inside the "U" of the stacked capacitor.

A layer of capacitor dielectric 48 is conformally deposited on third insulating layer 40 and within the capacitor cavity and covers bottom electrode 46. The equivalent oxide thickness of the capacitor dielectric layer is between 20 ° and 200 ° and (Ba, Sr
(TiO ₃ )), BaTiO ₃ , SrTiO ₃ , PbZr
TiO ₃ , PbZrO ₃ , PbLaTiO ₃ , SrBiT
It is preferable to include a material having a high dielectric constant such as aO ₃ .

Next, another layer of conductive electrode material 50 is deposited over capacitor dielectric 48 to fill the remaining space in the capacitor cavity. The upper electrode 50 is planarized to define a stacked capacitor structure.

The DRAM cell is completed by the additional conventional fabrication steps required to make a connection to the sensitivity-amplified region of the cell. These steps are not shown in the drawing.

As mentioned above, it is often desirable to provide two storage capacitors connected alternately to a bit line via two transistors. FIG. 6 shows a schematic elevation view of a DRAM cell structure having this feature.

As shown in FIG. 6, there are a plurality of switching transistors each having a source 20 and a drain 12. However, in this configuration, two adjacent transistors SW1, SW2 share a common source 20 ', which is connected to bit line 36 via electrical contact 28. In this arrangement, S
Activating W1 or SW2 allows access to either of the two storage capacitors C1 and C2.

The organization of the bit lines 36, word lines 16, capacitors 42, and bit line contacts 32 can be described with reference to the top view of the device shown in FIG.
Bit line contact 32 serves to connect the bit line to the source region. Each source region 20 has at least one
Book activity associated with word line. The bit line contacts allow each storage capacitor to be activated and read with a signal from the bit line. Any device area not formed on the isolation area of the substrate is called the active area of the device. A typical active region 43 includes two capacitors (C1 and C2),
There are two active word lines (WL2 and WL3), bit line (BL2), and bit line contacts 32. In the active region 43, the charge stored in C1 is gated to BL2 through WL2 and connected by the bit line contact 32. The same bit line contact connects BL2 to WL
3 Connected to the gate to read the charge stored in C2.

In summary, the following matters are disclosed regarding the configuration of the present invention.

(1) i) a substrate including at least one transistor having a source, a drain, and a gate; ii) a first insulating layer covering the transistor and having an upper surface; At least one electrical contact extending from one side to a top surface of the first insulating layer; iv) spaced over the first insulating layer so as to define a region between the bit lines; A bit line layer including a first bit line and a second bit line that are substantially parallel; and v) in the region between the first bit line and the second bit line and passing through the bit line layer. At least one stacked capacitor extending to said electrical contact. (2) further comprising a second insulating layer between the bit line layer and the first insulating layer, wherein the bit line plug extends through the second insulating layer to one of the electrical contacts; A semiconductor memory device according to claim 1. (3) The semiconductor memory device according to (2) above, wherein the second insulating layer includes borosilicate glass, tetraethoxysiloxane, or any combination thereof. (4) The semiconductor memory device according to (1), wherein each of the bit lines includes a sidewall and a silicon nitride spacer on the sidewall. (5) The semiconductor memory device according to (1), further including a third insulating layer on the bit line layer, wherein the stacked capacitor extends through the third insulating layer and the bit line layer. (6) The semiconductor memory device according to (5), wherein the third insulating layer includes borosilicate glass. (7) The semiconductor memory device according to (1), wherein the source and the drain are formed in the substrate. (8) The semiconductor memory device according to (1), wherein the first insulating layer includes borosilicate glass. (9) The semiconductor memory device according to (1), wherein the contact includes doped polysilicon. (10) The semiconductor memory device according to (1), wherein the first and second bit lines include tungsten. (11) A method for fabricating a semiconductor memory device on a semiconductor substrate, the method comprising: a) providing a semiconductor substrate including at least one transistor having a source, a drain, and a gate; Depositing a first insulating layer having a top surface; c) forming at least one electrical contact extending from one of the source and the drain through the first insulating layer to a top surface of the first insulating layer. D) on the first insulating layer, substantially parallel first spaced apart regions defining a region between the bit lines.
Forming a bit line layer including a bit line and a second bit line; and e) passing through the bit line layer into the region between the first bit line and the second bit line. Forming at least one stacked capacitor extending to the electrical contact. (12) a) On the semiconductor substrate, a source, a drain,
Providing at least one transistor having a gate and a gate; b) forming sidewall spacers and a cap surrounding the transistor; c) depositing a first insulating layer on the transistor; d) the source. Forming at least one contact extending from at least one of the drains to a top surface of the first insulating layer; e) planarizing the first insulating layer and the cap;
F) forming contact vias extending from the substrate to the first top surface using photolithography and etching, depositing a doped polysilicon layer, and filling the contact vias with doped poly. Providing at least one electrical contact in the first insulating layer by planarizing the silicon-filled and doped polysilicon layer to the first upper surface; and g) a second insulating layer on the first upper surface. Depositing a layer to form a second top surface; and h) using photolithography and etching.
Forming a bit line contact via extending from the contact to the second upper surface and forming a support via extending from the substrate to the second upper surface, depositing a first metal layer, the bit line contact via and the support; Forming at least one bit line contact and a support contact by filling the via with a metal material; and i) depositing a first nitride layer on the first metal layer using photolithography. Forming at least one bit line by etching the nitride layer and the first metal layer to define a bit line and forming a nitride sidewall spacer on at least one side of the bit line; j) Depositing a third insulating layer to form a third top surface; and k) forming between the bit lines using photolithography. 3 of the upper surface through the second and third insulating layers first
Etching a capacitor cavity extending over the top surface of the substrate, depositing a diffusion barrier layer, depositing a first electrode layer,
Etching the barrier layer and the first electrode layer to remove the barrier layer and the first electrode layer from the third top surface, define a node electrode, deposit a capacitor dielectric layer, and deposit a second electrode layer; Forming a set of concave stacked capacitors by etching the second electrode layer and defining a ground electrode.

[Brief description of the drawings]

FIG. 1 shows an electrical equivalent of a DRAM cell.

FIG. 2 is a top view of the device according to the present invention, showing the relative positions of the active regions where the transistors are formed, the positions of the capacitors and bit lines and word lines that make up the memory device.

FIG. 3 is a top view of a device according to an alternative embodiment of the present invention, showing the relative locations of the active regions in which the transistors are formed, the locations of the capacitors and bit lines and word lines that make up the memory device.

FIG. 4 is a schematic elevation view of a memory storage device according to the present invention, showing a substrate including transistors forming the storage device during a complete device production process.

FIG. 5 shows the structure of FIG. 4 after the structure is completed.

FIG. 6 illustrates an alternative embodiment of the DRAM structure according to the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 Substrate 11 Oxide layer 12 Drain region 14 Gate electrode 16 Word line 17 Side wall spacer 20 Source region 22 First insulating layer 28 Electrical contact 30 Second insulating layer 32 Bit line contact, bit line contact via 34 Support via 36 Bit line, conductive layer 38 nitride layer 40 bit line layer 42 storage capacitor, capacitor cavity 43 active region 44 diffusion barrier layer 45 active region 46 conductive electrode material, bottom electrode 48 capacitor dielectric

 ────────────────────────────────────────────────── ─── Continuation of the front page (71) Applicant 399035836 Infineon Technologies North America Corporation Infineon Technologies North America Corp. California San Jose North First Street 1730 1730 North First Street, San Jose, CA, San Jose, USA Thomas W. Dyer United States 12569 Pleasant Valley, New York Rock led drive 110 (72) Inventor Louis El-Shu United States 12524 Fishkill, Crosby Court, New York 12524 New York David El Cote United States 0 Orono, Maine College Avenue 55 (72) Inventor Carl Jay Ladens United States 12540 La Grangeville, NY New York Drive 35 (72) Inventor Gerhard Kunkel United States 12524 Fishkill Hawthorn Court, New York 22 (72) Inventor Hong Lee United States 94087 Sunnyvale, Brahms Way, California 455 Number 230 (72) Inventor Young Rim United States 12601 Po Kipsey, New York Kingwood Drive 13 (72) Inventor Yong Jin Park South Korea 463-772 Gyeonggi-do Shibumdanji Hanshin Apartment 127-1301 F-term (reference) D31 GA09 GA28 GA30 JA15 JA17 JA32 JA36 JA37 JA38 JA39 JA40 JA43 MA05 MA06 MA20 PR03 PR10 PR21 PR36 PR40

Claims (12)

[Claims] 1. A substrate including at least one transistor having a source, a drain, and a gate; ii) a first insulating layer covering the transistor and having a top surface; and iii) one of the source and the drain. Iv) at least one electrical contact extending from the upper surface of the first insulating layer to an upper surface of the first insulating layer; and iv) substantially spaced apart over the first insulating layer and defining an area between bit lines. A bit line layer including a first bit line and a second bit line in parallel; and v) in the region between the first bit line and the second bit line, through the bit line layer A semiconductor memory device comprising at least one stacked capacitor extending to said electrical contact. 2. The method of claim 1, further comprising a second insulating layer between the bit line layer and the first insulating layer, wherein a bit line plug extends through the second insulating layer to one of the electrical contacts. 1
A semiconductor memory device according to claim 1. 3. The method according to claim 2, wherein the second insulating layer is made of borosilicate glass.
3. The semiconductor memory device of claim 2, comprising tetraethoxysiloxane, or any combination thereof. 4. The semiconductor memory device of claim 1, wherein each of said bit lines includes a sidewall and a silicon nitride spacer on said sidewall. 5. The semiconductor memory device of claim 1, further comprising a third insulating layer on the bit line layer, wherein the stacked capacitor extends through the third insulating layer and the bit line layer. 6. The semiconductor memory device according to claim 5, wherein the third insulating layer comprises borosilicate glass. 7. The semiconductor memory device according to claim 1, wherein the source and the drain are formed in the substrate. 8. The semiconductor memory device according to claim 1, wherein the first insulating layer comprises borosilicate glass. 9. The semiconductor memory device according to claim 1, wherein the contact comprises doped polysilicon. 10. The semiconductor memory device according to claim 1, wherein the first and second bit lines include tungsten. 11. A method of fabricating a semiconductor memory device on a semiconductor substrate, comprising: a) providing a semiconductor substrate including at least one transistor having a source, a drain, and a gate; and b) on the transistor. Depositing a first insulating layer having a top surface thereon; and c) at least one electrical contact extending from one of said source and said drain through said first insulating layer to a top surface of said first insulating layer. D) forming a first, substantially parallel, spaced-apart region on the first insulating layer such that an area between the bit lines is defined;
Forming a bit line layer including a bit line and a second bit line; and e) passing through the bit line layer into the region between the first bit line and the second bit line. Forming at least one stacked capacitor extending to the electrical contact. 12. A method comprising: a) providing at least one transistor having a source, a drain, and a gate on the semiconductor substrate; b) forming a sidewall spacer and a cap surrounding the transistor; c) a transistor. Depositing a first insulating layer thereon; d) forming at least one contact extending from at least one of the source and the drain to a top surface of the first insulating layer; and e) forming the first insulating layer. Flatten the insulating layer and the cap,
F) forming contact vias extending from the substrate to the first top surface using photolithography and etching, depositing a doped polysilicon layer, and filling the contact vias with doped poly. Providing at least one electrical contact in the first insulating layer by planarizing the silicon-filled and doped polysilicon layer to the first upper surface; and g) a second insulating layer on the first upper surface. Depositing a layer to form a second top surface; and h) using photolithography and etching.
Forming a bit line contact via extending from the contact to the second upper surface and forming a support via extending from the substrate to the second upper surface, depositing a first metal layer, the bit line contact via and the support; Forming at least one bit line contact and a support contact by filling the via with a metal material; and i) depositing a first nitride layer on the first metal layer using photolithography. Forming at least one bit line by etching the nitride layer and the first metal layer to define a bit line and forming a nitride sidewall spacer on at least one side of the bit line; j) Depositing a third insulating layer to form a third top surface; and k) forming between the bit lines using photolithography. 3 of the upper surface through the second and third insulating layers first
Etching a capacitor cavity extending over the top surface of the substrate, depositing a diffusion barrier layer, depositing a first electrode layer,
Etching the barrier layer and the first electrode layer to remove the barrier layer and the first electrode layer from the third top surface, define a node electrode, deposit a capacitor dielectric layer, and deposit a second electrode layer; Etching the second electrode layer to define a ground electrode to form a set of concave stacked capacitors.