CN115884594B

CN115884594B - Semiconductor structure and preparation method thereof

Info

Publication number: CN115884594B
Application number: CN202310091013.3A
Authority: CN
Inventors: 吴润平; 陈美卉; 朱磊
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2023-02-09
Filing date: 2023-02-09
Publication date: 2023-07-21
Anticipated expiration: 2043-02-09
Also published as: CN115884594A

Abstract

The embodiment of the disclosure relates to a semiconductor structure and a preparation method of the semiconductor structure, wherein the semiconductor structure comprises: a first substrate; a capacitor stack layer on the first substrate, the capacitor stack layer including a capacitor structure therein; a first transistor stack layer on the capacitor stack layer, the first transistor stack layer including a first insulating layer having a trench, a semiconductor layer including a channel region in the trench and first and second source and drain regions on top of the first insulating layer on both sides of the trench, and a word line structure covering the channel region and filling the trench; the first source drain region is coupled to the capacitor structure through the first contact plug. The embodiment of the disclosure is beneficial to improving the electrical performance of the semiconductor structure.

Description

Semiconductor structure and preparation method thereof

Technical Field

The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation method of the semiconductor structure.

Background

As the integration density of dynamic memories has advanced toward higher levels, there has been a growing demand for the arrangement of transistors in dynamic memory array structures and for the size of the transistors.

The memory generally includes a capacitor and a transistor, a drain of the transistor is connected to a bit line structure, a source of the transistor is connected to the capacitor, and a word line structure of the memory can control the opening or closing of a channel region of the transistor, thereby reading data information stored in the capacitor through the bit line structure or writing data information into the capacitor through the bit line structure for storage. In order to realize the electric signal transmission between the external element and the bit line, the word line and the capacitor, an electric connection structure such as a conductive plug is usually arranged to form electric connection with the bit line, the word line and the capacitor.

Disclosure of Invention

The embodiment of the disclosure provides a semiconductor structure and a preparation method of the semiconductor structure, which are at least beneficial to enhancing the electrical performance of the semiconductor structure.

Embodiments of the present disclosure provide a semiconductor structure, comprising: a first substrate; a capacitor stack layer on the first substrate, the capacitor stack layer including a capacitor structure therein; a first transistor stack layer on the capacitor stack layer, the first transistor stack layer including a first insulating layer having a trench, a semiconductor layer including a channel region within the trench and first and second source drain regions on top of the first insulating layer on both sides of the trench, and a word line structure covering the channel region and filling the trench; and the first source-drain region is coupled with the capacitor structure through the first contact plug.

In some embodiments, the capacitor stack layer includes: a first dielectric layer, a first electrode layer and a second dielectric layer which are sequentially laminated on the first substrate; capacitance holes in the first electrode layer and the second dielectric layer; the capacitor dielectric layer covers the side wall and the bottom of the capacitor hole, and the second electrode layer covers the capacitor dielectric layer and fills the capacitor hole; the capacitor structure comprises the first electrode layer, the capacitance medium layer and the second electrode layer, and the first source drain region is coupled with the second electrode layer through the first contact plug.

In some embodiments, the capacitor stack further comprises: a capacitive contact structure coupled to the second electrode layer; a first planarization layer covering the capacitor contact structure; the first contact plug also penetrates through the first planarization layer and is coupled with the capacitance contact structure.

In some embodiments, the semiconductor structure further comprises: and a second contact plug penetrating the first transistor stack layer, the first planarization layer, and the second dielectric layer, the second contact plug being coupled with the first electrode layer.

In some embodiments, the first transistor stack layer further includes a second planarization layer covering the first insulating layer, the semiconductor layer, and the word line structure; the semiconductor structure further includes: a bit line structure on top of the second planarization layer, the bit line structure comprising: the bit line contact plug also penetrates through the second planarization layer and is coupled with the semiconductor layer of the second source drain region.

In some embodiments, the semiconductor structure further comprises: the first rewiring layer is located on the top surface of the bit line structure and comprises a plurality of first contact pads, and the first contact pads are respectively coupled with the bit line structure, the word line structure and the second contact plugs.

In some embodiments, the semiconductor structure further comprises: a third contact plug penetrating at least a portion of the film layer in the first re-wiring layer, the bit line body being coupled with one of the first contact pads through the third contact plug; a fourth contact plug penetrating at least a portion of the film layer in the first re-wiring layer and the second planarization layer, the conductive portion in the word line structure being coupled with another one of the first contact pads through the fourth contact plug; and a fifth contact plug penetrating at least part of the film layer in the first re-wiring layer, the second contact plug being coupled with the first contact pad through the fifth contact plug.

In some embodiments, the semiconductor structure further comprises: a second substrate having opposite first and second sides, the first side having a plurality of second transistors thereon; and the second redistribution layer is positioned on the first side of the second substrate and covers the plurality of second transistors, the second redistribution layer comprises a plurality of second contact pads, the plurality of second contact pads are at least coupled with part of the second transistors, and the plurality of first contact pads and the plurality of second contact pads are correspondingly connected in a bonding mode.

In some embodiments, the semiconductor structure further comprises: and a third redistribution layer located on the second side of the second substrate, the third redistribution layer including a plurality of third contact pads, the plurality of third contact pads being coupled to at least a portion of the second transistors.

In some embodiments, the material of the semiconductor layer includes an oxide semiconductor material.

Correspondingly, the embodiment of the disclosure also provides a preparation method of the semiconductor structure, which comprises the following steps: forming a capacitor stack layer on a first substrate, the capacitor stack layer comprising a capacitor structure; forming a first transistor stack layer on the capacitor stack layer, the first transistor stack layer including a first insulating layer having a trench, a semiconductor layer including a channel region located within the trench and first and second source drain regions located on top of the first insulating layer on both sides of the trench, and a word line structure covering the channel region and filling the trench; a first via is formed through the first transistor stack layer and a first contact plug is formed within the first via, the first source drain region being coupled to the capacitor structure through the first contact plug.

In some embodiments, forming the capacitor stack layer includes: forming a first dielectric layer, a first electrode layer and a second dielectric layer which are stacked in sequence on the first substrate; etching the second dielectric layer and the first electrode layer to form a capacitor hole; forming a capacitance medium layer and a second electrode layer in the capacitance hole, wherein the capacitance medium layer covers the side wall and the bottom of the capacitance hole, and the second electrode layer covers the capacitance medium layer and fills the capacitance hole; the capacitor structure comprises the first electrode layer, the capacitance medium layer and the second electrode layer.

In some embodiments, forming the capacitor stack further comprises: forming a capacitance contact structure, wherein the capacitance contact structure is coupled with the first electrode layer; forming a first planarization layer covering the capacitor contact structure; the first through hole penetrates through the first planarization layer, and the first contact plug is coupled with the capacitance contact structure.

In some embodiments, forming the first transistor stack layer includes: forming the first insulating layer on the capacitor stack layer; etching the first insulating layer to form the trench; forming a semiconductor material layer covering the first insulating layer in a conformal manner; patterning the semiconductor material layer to form the semiconductor layer; forming the word line structure; a second planarization layer is formed overlying the first insulating layer, the semiconductor layer, and the word line structure.

In some embodiments, the method of fabricating a semiconductor structure further comprises: and forming a second through hole penetrating through the first transistor stack layer, the first planarization layer and the second dielectric layer, and forming a second contact plug in the second through hole, wherein the second contact plug is coupled with the first electrode layer.

In some embodiments, the method of fabricating a semiconductor structure further comprises: forming a bit line structure on the first transistor stack layer, the bit line structure being coupled to the second source drain region; a first redistribution layer is formed over the bit line structure, the first redistribution layer including a plurality of first contact pads coupled with the bit line structure, the word line structure, and the second contact plugs, respectively.

In some embodiments, the method of fabricating a semiconductor structure further comprises: providing a second substrate having opposite first and second sides; forming a plurality of second transistors on the first side; forming a second redistribution layer overlying the plurality of second transistors, the second redistribution layer including a plurality of second contact pads, the plurality of second contact pads being coupled to at least a portion of the second transistors; and bonding the second substrate with the first substrate so as to correspondingly connect the plurality of first contact pads with the plurality of second contact pads.

In some embodiments, the method of fabricating a semiconductor structure further comprises: thinning the second substrate from the second side; forming a third re-wiring layer on the thinned second side of the second substrate, the third re-wiring layer including a plurality of third contact pads, the plurality of third contact pads being coupled to at least a portion of the second transistors.

The technical scheme provided by the embodiment of the disclosure has at least the following advantages:

in the technical scheme of the semiconductor structure provided by the embodiment of the disclosure, the first transistor stacking layer is arranged, and the word line structure positioned in the first transistor stacking layer is positioned at the top of the capacitor stacking layer, so that the word line structure is not shielded by the capacitor structure, and when the electric signal of the word line structure is actually led out, the electric connection structure for leading out the electric signal of the word line structure can be arranged to be electrically connected with the middle part of the word line structure or the end part of the word line structure, so that the flexibility of the position of the word line structure for leading out the electric signal is improved, the transmission performance of the electric signal in the word line structure is enhanced, the driving capability of the word line structure in the semiconductor structure is enhanced, and the electric performance of the semiconductor structure is improved. In addition, the first transistor is formed in the first insulating layer, so that leakage current is greatly reduced, and the electrical performance of the semiconductor structure is further improved.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, which are not to be construed as limiting the embodiments unless specifically indicated otherwise; in order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the conventional technology, the drawings required for the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.

FIG. 1 is a schematic cross-sectional view of a semiconductor structure according to one embodiment of the present disclosure;

FIG. 2 is another schematic cross-sectional view of a semiconductor structure according to one embodiment of the present disclosure;

FIG. 3 is a simplified schematic diagram of a semiconductor structure according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a partial cross-sectional structure of another semiconductor structure according to an embodiment of the present disclosure;

FIG. 6 is a simplified schematic diagram of another semiconductor structure according to one embodiment of the present disclosure;

FIG. 7 is a simplified schematic diagram of yet another semiconductor structure provided in accordance with one embodiment of the present disclosure;

fig. 8 is a schematic structural diagram corresponding to steps of forming a first dielectric layer, a first electrode layer, and a second dielectric layer in a method for manufacturing a semiconductor structure according to another embodiment of the present disclosure;

fig. 9 is a schematic structural diagram corresponding to a step of forming a capacitor hole in a method for manufacturing a semiconductor structure according to another embodiment of the present disclosure;

fig. 10 is a schematic structural diagram corresponding to a step of forming an initial capacitance dielectric layer in a method for manufacturing a semiconductor structure according to another embodiment of the present disclosure;

fig. 11 is a schematic structural diagram corresponding to a step of forming a second electrode layer in a method for manufacturing a semiconductor structure according to another embodiment of the present disclosure;

fig. 12 is a schematic structural diagram corresponding to a step of forming a capacitor cap layer in a method for manufacturing a semiconductor structure according to another embodiment of the present disclosure;

fig. 13 is a schematic structural diagram corresponding to a step of forming a capacitor contact structure in a method for manufacturing a semiconductor structure according to another embodiment of the present disclosure;

fig. 14 is a schematic structural diagram corresponding to a step of forming a first planarization layer in a method for manufacturing a semiconductor structure according to another embodiment of the present disclosure;

Fig. 15 is a schematic structural diagram corresponding to a step of forming a first insulating layer in a method for manufacturing a semiconductor structure according to another embodiment of the present disclosure;

fig. 16 is a schematic structural diagram corresponding to a step of forming a trench in a method for manufacturing a semiconductor structure according to another embodiment of the present disclosure;

fig. 17 is a schematic structural diagram corresponding to a step of forming a semiconductor material layer in a method for manufacturing a semiconductor structure according to another embodiment of the present disclosure;

fig. 18 is a schematic structural diagram corresponding to a step of forming a word line structure in a method for manufacturing a semiconductor structure according to another embodiment of the present disclosure;

fig. 19 is a schematic structural diagram corresponding to a step of forming a second planarization layer in a method for manufacturing a semiconductor structure according to another embodiment of the present disclosure;

fig. 20 is a schematic structural diagram corresponding to a step of forming a first through hole in a method for manufacturing a semiconductor structure according to another embodiment of the present disclosure;

fig. 21 is a schematic structural diagram corresponding to a step of forming a first contact plug in a method for manufacturing a semiconductor structure according to another embodiment of the present disclosure;

fig. 22 is a schematic structural diagram corresponding to a step of forming a third through hole in a method for manufacturing a semiconductor structure according to another embodiment of the present disclosure;

Fig. 23 is a schematic structural diagram corresponding to a step of forming a bit line contact plug in a method for manufacturing a semiconductor structure according to another embodiment of the present disclosure.

Detailed Description

At present, the semiconductor structure has a problem of poor electrical performance, and analysis finds that one of the reasons for the poor electrical performance of the semiconductor structure is that in the current semiconductor structure, the capacitor stack layer is located on top of the transistor stack layer, so that the capacitor stack layer is located on top of the word line structure where the gate electrode of the transistor is electrically contacted, and the word line structure is blocked by the capacitor structure. In an actual semiconductor structure process, if an electrical signal of a word line structure needs to be led out, an electrical connection structure can only be formed at the end of the word line structure, so that the electrical signal can be transmitted from the end, and the transmission distance is possibly longer, so that the transmission capability of the electrical signal in the semiconductor structure is weaker, and further, the driving capability of the word line in the semiconductor structure is weaker, and the problem of poor electrical performance of the semiconductor structure is caused.

The embodiment of the disclosure provides a semiconductor structure, which is provided with a first transistor stacking layer and a word line structure positioned in the first transistor stacking layer, wherein the word line structure is positioned at the top of a capacitor stacking layer, so that the word line structure is not shielded by the capacitor structure, and further, when an electric signal of the word line structure is actually led out, an electric connection structure can be arranged to lead out the electric signal from the middle of the word line structure or the end part of the word line structure, the flexibility of the word line structure in leading out the electric signal position is improved, the transmission performance of the electric signal is enhanced, the driving capability of the word line structure in the semiconductor structure can be enhanced, and the electric performance of the semiconductor structure is improved.

Embodiments of the present disclosure will be described in detail below with reference to the attached drawings. However, those of ordinary skill in the art will understand that in the various embodiments of the present disclosure, numerous technical details have been set forth in order to provide a better understanding of the present disclosure. However, the technical solutions claimed in the present disclosure can be implemented without these technical details and with various changes and modifications based on the following embodiments.

Fig. 1 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the disclosure, and fig. 2 is a schematic cross-sectional view of another semiconductor structure according to an embodiment of the disclosure; FIG. 3 is a simplified schematic diagram of a semiconductor structure according to an embodiment of the present disclosure; FIG. 4 is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure; fig. 5 is a schematic diagram illustrating a partial cross-sectional structure of another semiconductor structure according to an embodiment of the disclosure.

Referring to fig. 1 to 5, a semiconductor structure includes: a first substrate 101; a capacitor stack layer on the first substrate 101, the capacitor stack layer including a capacitor structure 102 therein; a first transistor stack layer on the capacitor stack layer, the first transistor stack layer including a first insulating layer 103, a semiconductor layer 104, and a word line structure 105, the first insulating layer 103 having a trench, the semiconductor layer 104 including a channel region 1 located in the trench and first and second source drain regions 2 and 3 located on top surfaces of the first insulating layer 103 on both sides of the trench, the word line structure 105 covering the channel region 1 and filling the trench; the first source drain region 2 is coupled to the capacitor structure 102 through the first contact plug 106, which penetrates the first contact plug 106 of the first transistor stack layer.

The first transistor stack layer is used for forming a first transistor, the word line structure 105 in the first transistor stack layer is located at the top of the capacitor stack layer, so that the capacitor structure 102 cannot shade the word line structure 105, and when an electric signal of the word line structure 105 is actually led out, an electric connection structure for leading out the word line structure 105 can be electrically connected with the middle of the word line structure 105 or an end part of the word line structure 105, so that flexibility of setting the electric connection structure is improved, transmission of the electric signal in the word line structure 105 can be improved, driving capability of the word line structure 105 is enhanced, and telecommunication capability of the semiconductor structure is improved. In addition, the first transistor is formed in the first insulating layer 103, so that the leakage current is greatly reduced, and the electrical performance of the semiconductor structure is further improved.

In some embodiments, the material of the first substrate 101 is a semiconductor material. In some embodiments, the material of the first substrate 101 is silicon. In some embodiments, the first substrate 101 may also be germanium, silicon germanium, or silicon on insulator.

The channel region 1, the first source drain region 2 and the second source drain region 3 of the semiconductor layer 104 are used for forming a first transistor, wherein the channel region 1 is used as a channel of the first transistor, the word line structure 105 is in contact with the semiconductor layer 104 of the channel region 1 and is used as a word line of the first transistor for conducting the channel region 1 based on a control signal, so that charge transmission between the first source drain region 2 and the second source drain region 3 is realized, and further data writing is realized.

In some embodiments, the doping ion type of the channel region 1 may be different from the doping ion type of the second source drain region 3 and the first source drain region 2, thereby forming a junction transistor. For example, the doping ion type in the channel region 1 may be P-type, and the doping ion type in the second source drain region 3 and the first source drain region 2 may be N-type, constituting a PMOS transistor.

In some embodiments, the doping ion type of the channel region 1 may also be the same as the doping ion type of the second source drain region 3 and the first source drain region 2, forming a junction-free transistor.

The entire side and bottom surfaces of the word line structure 105 are surrounded by the semiconductor layer 104 of the channel region 1, so that the contact area between the word line structure 105 and the semiconductor layer 104 of the channel region 1 is larger, the area of the channel region 1 of the formed first transistor is larger, the control capability of the word line structure 105 on the first transistor is improved, and leakage current can be reduced. The semiconductor layers 104 of the first source drain region 2 and the second source drain region 3 are located on top of the first insulating layer 103 and located on two sides of the semiconductor layer 104 of the channel region 1, so that the semiconductor layer 104 has a saddle-shaped outline, which is beneficial for the first source drain region 2 and the second source drain region 3 to realize electrical connection with the capacitor structure 102 or the bit line structure respectively.

In some embodiments, the material of the semiconductor layer includes an oxide semiconductor material (e.g., a metal oxide semiconductor material) or a sulfide semiconductor material, which may be, for example, any of IGZO (Indium Gallium Zinc Oxide ), zinc oxide, indium gallium oxide, zinc sulfide, or the like. The IGZO has a high on-off current ratio, and in some embodiments, when the IGZO is used as the material of the semiconductor layer 104, it may be possible to implement that the first transistor has lower power consumption, so that the first transistor has higher current driving capability and low leakage current, which is beneficial to improving the electrical performance of the semiconductor structure.

The first insulating layer 103 functions to isolate the word line structure 105 and also functions to support the semiconductor layer 104 and the word line structure 105. In some embodiments, the material of the first insulating layer 103 may be silicon oxide.

In some embodiments, the word line structure 105 may include a word line body 17 and a gate dielectric layer 16 located on the sides and bottom of the word line body 17, the gate dielectric layer 16 being located between the semiconductor layer 104 of the channel region 1 and the word line body 17. In some embodiments, the word line body 17 is conductive, and the material of the word line body 17 may be a metal or a heavily doped semiconductor material, such as at least one of tungsten or titanium nitride. In some embodiments, the material of gate dielectric layer 16 may be silicon oxide or a High-K material.

In some embodiments, the capacitor stack layer includes: a first dielectric layer 11, a first electrode layer 12, and a second dielectric layer 13 sequentially stacked on a first substrate 101; a capacitance hole in the first electrode layer 12 and the second dielectric layer 13; a capacitance dielectric layer 14 and a second electrode layer 15 in the capacitance hole, the capacitance dielectric layer 14 covering the sidewall and bottom of the capacitance hole, the second electrode layer 15 covering the capacitance dielectric layer 14 and filling the capacitance hole; the capacitor structure 102 includes a first electrode layer 12, a capacitance dielectric layer 14, and a second electrode layer 15, and the first source drain region 2 is coupled to the second electrode layer 15 through a first contact plug 106. In some embodiments, the first source drain region 2 may serve as a drain of the first transistor.

In some embodiments, the number of capacitor structures 102 in the capacitor stack layer may be plural, wherein the two second electrode layers 15 may share the same first electrode layer 12, improving the integration of the semiconductor structure.

The first dielectric layer 11 and the second dielectric layer 13 function to isolate the capacitor structure 102, preventing the capacitor structure 102 from making electrical contact with other conductive elements. In some embodiments, the material of the first dielectric layer 11 may be silicon nitride, and the material of the second dielectric layer 13 may be silicon nitride.

The capacitor holes are located in the first electrode layer 12, that is, in the process of actually forming the capacitor holes, the first electrode layer 12 is etched to form the capacitor holes. To facilitate the etching process of the first electrode layer 12, in some embodiments, the material of the first electrode layer 12 may be a semiconductor conductive material, for example, silicon germanium. The second electrode layer 15 is filled in the capacitor hole, and in order to improve the electrical transmission performance of the capacitor structure 102, the material of the second electrode layer 15 may be a metal material, for example, tungsten. In some embodiments, the material of the second electrode layer 15 may also be a semiconductor material, for example, may be titanium nitride. In some embodiments, the material of the capacitive dielectric layer 14 is an insulating material, such as a high dielectric constant material.

The semiconductor layer 104 of the first source drain region 2 is opposite to the second electrode layer 15, and the first transistor is located on top of the capacitor structure 102, based on which the first contact plug 106 can be used to electrically connect the second electrode layer 15 and the first source drain region 2 in the vertical direction, so that the first transistor can store the written data into the capacitor structure 102 through the first contact plug 106, and data storage is realized.

In some embodiments, the material of the first contact plug 106 may be metal, and the metal material has a low resistance, which may enhance the transmission capability of the electrical signal. In some embodiments, the material of the first contact plug 106 may be at least one of tungsten, nickel, or copper. In some embodiments, the material of the first contact plug 106 may be a stack of titanium nitride and tungsten.

In some embodiments, the capacitor stack further comprises: a capacitance contact structure 18 coupled with the second electrode layer 15; a first planarization layer 107 covering the capacitor contact structure 18; the first contact plug 106 further penetrates through the first planarization layer 107 and is coupled to the capacitor contact structure 18.

In some embodiments, the capacitive contact structure 18 may include a first portion on top of the second electrode layer 15 in direct electrical contact with the second electrode layer 15 and a second portion covering a portion of the top surface of the second dielectric layer 13, the first contact plug 106 being in electrical contact with the second portion top surface. The width dimension of the second portion is smaller than the width dimension of the first portion such that the spacing between adjacent first portions is larger, which reduces the risk of shorting between adjacent capacitive contact structures 18.

In some embodiments, the semiconductor structure further comprises: and the capacitor cover layer 19 is positioned on the top of the second dielectric layer 13 and is used for protecting the first electrode layer. The second portion of the capacitive contact structure may be located on top of a portion of the capacitive cover layer 19, the capacitive cover layer 19 acting as a support for the capacitive contact structure.

In some embodiments, the material of the capacitive contact structure 18 may be at least one of a metallic material or a semiconductor material, for example, may be at least one of tungsten or titanium nitride.

The first planarization layer 107 covers the top surface of the second portion of the capacitor contact structure 18, and in some embodiments, if the number of capacitor contact structures 18 is plural, the first planarization layer 107 is further located between the second portions of adjacent capacitor contact structures 18, and functions to isolate the adjacent capacitor contact structures 18.

The top surface of the first planarization layer 107 is relatively flat, which provides a foundation for forming a first transistor stack layer on top of the capacitor stack layer, so that the first insulating layer 103 formed on top of the first planarization layer 107 has better uniformity and higher density, which is beneficial to improving the stability of the formed semiconductor structure.

In some embodiments, the material of the first planarization layer 107 may be silicon nitride.

Referring to fig. 2, fig. 1 and fig. 2 are schematic cross-sectional views of a semiconductor structure in different directions, and in the schematic cross-sectional view of fig. 2, a word line structure is not cut. In some embodiments, the semiconductor structure further comprises: and a second contact plug 108 penetrating the first transistor stack layer, the first planarization layer 107 and the second dielectric layer 13, the second contact plug 108 being coupled with the first electrode layer 12. The second contact plug 108 is in electrical contact with the top of the first electrode layer 12 for enabling signal transmission between the first electrode layer 12 and an external element. For example, in some embodiments, the second contact plug 108 may be disposed to be coupled with the ground terminal, such that the second electrode layer 15 is grounded, and the problem of floating of the capacitor structure 102 may be prevented.

In some embodiments, the second contact plug 108 penetrates the first insulating layer 103, the first planarizing layer 107, and the second dielectric layer 13 to make electrical contact with the top of the first electrode layer 12. In some embodiments, the material of the second contact plug 108 may be at least one of a metal material or a semiconductor material, for example, may be at least one of tungsten or titanium nitride.

With continued reference to fig. 1, in some embodiments, the first transistor stack layer further includes a second planarization layer 109, the second planarization layer 109 covering the first insulating layer 103, the semiconductor layer 104, and the word line structure 105; the semiconductor structure further includes: a bit line structure on top of the second planarization layer 109, the bit line structure comprising: bit line body 112 and bit line contact plug 111, bit line contact plug 111 is coupled with bit line body 112, bit line contact plug 111 also penetrates second planarization layer 109, and is coupled with semiconductor layer 104 of second source drain region 3. The second source drain region 3 may serve as a source of the first transistor for inputting a data signal, wherein the data signal may be transferred to the second source drain region 3 via a bit line.

The bit line structure is arranged on the top surface of the first transistor stacking layer, so that the capacitor stacking layer can not excessively shield the bit line structure, and further, when the electric connection structure of an electric signal led out of the bit line structure is actually arranged, the flexibility of the electric connection structure can be improved, for example, the electric connection structure can be arranged from the middle part of the bit line structure. In this way, in the actual signal transmission process, the transmission path of the electric signal in the bit line structure can be shortened, the transmission performance of the electric signal is improved, and the driving performance of the first transistor is further enhanced.

The second planarization layer 109 has a planar top surface to improve the structural stability of the bit line structure formed on top of the first transistor stack. In some embodiments, the material of the second planarizing layer 109 may be silicon nitride.

In some embodiments, the semiconductor structure further comprises: the second insulating layer 110, the second insulating layer 110 is located on top of the second planarization layer 109, and the bit line contact plug 111 penetrates the second insulating layer 110 and the second planarization layer 109 to be coupled with the semiconductor layer 104 of the second source drain region 3. The bit line body 112 may be located on top of the second insulating layer 110. The second insulating layer 110 serves to isolate the bit line body 112 on the one hand, and to support the bit line body 112 on the other hand. In some embodiments, the material of the second insulating layer 110 may be silicon oxide.

In some embodiments, the bit line body 112 covers the top surface of the second insulating layer 110, and is in electrical contact with the bit line contact plug 111, and the material of the bit line body 112 may be at least one of a semiconductor material or a metal, for example, at least one of titanium nitride or tungsten.

In some embodiments, the semiconductor structure further comprises: the bit line cap layer 113, the bit line cap layer 113 is located on the top surface of the bit line body 112, which on one hand serves to protect the bit line body 112, and on the other hand can isolate the top surface of the bit line body 112 from other conductive structures in the semiconductor structure. In some embodiments, the material of the bit line cap layer 113 may be silicon nitride.

In some embodiments, the number of word line structures 105 and bit line structures may be plural, wherein the plurality of word line structures 105 may extend in a first direction and the plurality of bit line structures may extend in a second direction, the first direction being different from the second direction.

It is not difficult to find that, in the embodiment of the disclosure, the semiconductor layer 104 is configured to have a saddle profile, so that the channel region 1 in the middle surrounds the side surface and the bottom surface of the word line structure 105, and the first source drain region 2 and the second source drain region 3 on two sides are respectively coupled with the capacitor structure 102 below the first transistor stack layer and the bit line structure above the first transistor stack layer, so that the structure that the bit line structure and the word line structure 105 are located at the top of the capacitor stack layer is realized.

Referring to fig. 3, the capacitor stack 6, the first transistor stack 7, and the bit line structure 8 of fig. 3 are shown in simplified form, respectively, and reference is made to fig. 1 for a specific structure. In some embodiments, the semiconductor structure further comprises: the first redistribution layer 116 is located on the top surface of the bit line structure, and the first redistribution layer 116 includes a plurality of first contact pads 117, where the plurality of first contact pads 117 are respectively coupled to the bit line structure, the word line structure 105, and the second contact plug 108 (refer to fig. 2). The first redistribution layer 116 is configured to redistribute electrical transmission paths connected to the first contact pads 117, each first contact pad 117 being coupled to a bit line structure, a word line structure 105 and a second contact plug 108, respectively, the second contact plug 108 being coupled to the first electrode layer 12, signal transmission between an external element and the bit line structure, the word line structure 105 and the first electrode layer 12 being enabled through the first contact pads 117, whereby data can be transmitted into the bit line structure and the word line structure 105. In some embodiments, one of the first contact pads 117 may be connected to the ground, so as to couple the first electrode layer 12 to the ground, thereby preventing the floating problem of the capacitor structure 102.

In some embodiments, the first redistribution layer 116 further has a wiring layer, which may be, for example, a copper wiring layer, and functions to redistribute the connections, so as to realize electrical connection between the bit line structure, the word line structure 105, and the second contact plug 108 and the first contact pad 117.

In some embodiments, the first redistribution layer 116 may include a first dielectric layer 21 and a second dielectric layer 22 stacked in sequence, where the first dielectric layer 21 contacts the top surface of the bit line structure, the wiring layer may be located in the first dielectric layer 21, and the first dielectric layer 21 may protect and isolate the wiring layer. The first contact pad 117 may be disposed in the second dielectric layer 22, the second dielectric layer 22 protecting and isolating the first contact pad 117. In some embodiments, the material of the first dielectric layer 21 may be at least one of oxide and silicon nitride; the material of the second dielectric layer 22 may be at least one of oxide and silicon nitride.

Referring to fig. 4, in some embodiments, the semiconductor structure further comprises: a third contact plug 25, the third contact plug 25 penetrating at least a portion of the film layer in the first re-wiring layer 116 (refer to fig. 3), the bit line body 112 (refer to fig. 1) being coupled with one of the first contact pads 117 through the third contact plug 25; referring to fig. 5, the semiconductor structure further includes: a fourth contact plug 26, the fourth contact plug 26 penetrating at least a portion of the film layer in the first re-wiring layer 116 (refer to fig. 3) and the second planarization layer 109 (refer to fig. 1), a conductive portion in the word line structure 105 (refer to fig. 1) being coupled with another first contact pad 117 through the fourth contact plug 26, the conductive portion may be the word line body 17; referring to fig. 3, a fifth contact plug 27, the fifth contact plug 27 penetrates at least a portion of the film layer in the first re-wiring layer 116, and the second contact plug 108 is coupled with a further first contact pad 117 through the fifth contact plug 27.

Referring to fig. 4, in some embodiments, the third contact plug 25 may penetrate the bit line cap layer 113 to make electrical contact with the top of the bit line body 112. Because the bit line cover layer 113 is located at the top and is not shielded by the capacitor structure 102, in the process of actually forming the third contact plug 25, the third contact plug 25 may be set to penetrate through the bit line cover layer 113 corresponding to the middle part of the bit line structure, so as to perform signal transmission in the middle part of the bit line structure, shorten the signal transmission path, improve the signal transmission rate and strength, and enhance the signal transmission capability of the first transistor.

In some embodiments, the third contact plug 25 may also be disposed to penetrate the bit line cap layer 113 corresponding to the end of the bit line structure, so as to perform signal transmission at the end of the bit line structure, thereby increasing the flexibility of the placement of the third contact plug 25.

Referring to fig. 5, in some embodiments, a second insulating layer 110 is further disposed in the semiconductor structure, the second insulating layer 110 is located between the bit line structure and the second planarization layer 109, and a bit line isolation structure 130 is further disposed between adjacent bit line structures, so that the fourth contact plug 26 may penetrate the bit line isolation structure 130, the second insulating layer 110, and the second planarization layer 109 to form an electrical contact with the top surface of the word line body 17. Since the top of the word line structure 105 is not shielded by the capacitor structure 102, in the process of actually forming the fourth contact plug 26, the fourth contact plug 26 may be disposed to penetrate through the bit line isolation structure 130, the second insulating layer 110 and the second planarization layer 109 opposite to the middle of the word line structure 105, so as to perform signal transmission in the middle of the word line structure 105, shorten the signal transmission path, increase the transmission rate of signals into the word line structure 105, enhance the driving capability of the word line structure 105, and further improve the electrical performance of the semiconductor structure.

In some embodiments, to simplify the manufacturing process, the fourth contact plug 26 may also be disposed to penetrate the bit line isolation structure 130, the second insulating layer 110, and the second planarization layer 109 opposite to the end of the word line structure 105 to make electrical contact with the top surface of the word line body 17.

It is understood that the third contact plug 25, the fourth contact plug 26 and the fifth contact plug 27 are respectively coupled to a first contact pad 117, so as to realize transmission of different signals.

Referring to fig. 3, in some embodiments, if the first redistribution layer 116 includes the first dielectric layer 21 and the second dielectric layer 22 stacked, the third contact plug 25, the fourth contact plug 26, and the fifth contact plug 27 may penetrate the first dielectric layer 21 and be respectively coupled with the first contact pad 117 in the second dielectric layer 22.

FIG. 6 is a simplified schematic diagram of another semiconductor structure according to one embodiment of the present disclosure; fig. 7 is a simplified schematic structural diagram of another semiconductor structure according to an embodiment of the disclosure, and fig. 7 is a schematic diagram of a first substrate 101 bonded to a second substrate 201.

Referring to fig. 6 and 7, in some embodiments, the semiconductor structure further includes: a second substrate 201, the second substrate 201 having opposite first and second sides 4 and 5, the first side 4 having a plurality of second transistors 202 thereon; and a second redistribution layer 118, the second redistribution layer 118 being located on the first side 4 of the second substrate 201 and covering the plurality of second transistors 202, the second redistribution layer 118 including a plurality of second contact pads 119, the plurality of second contact pads 119 being coupled to at least a portion of the second transistors 202, wherein the plurality of first contact pads 117 and the plurality of second contact pads 119 are correspondingly connected by bonding.

In some embodiments, the material of the second substrate 201 is a semiconductor material, and in some embodiments, the material of the second substrate 201 is silicon. In some embodiments, the second substrate 201 may also be germanium, silicon germanium, or silicon on insulator.

In some embodiments, where the first substrate 101 is used to form an array region and the second substrate 201 is used to form a peripheral region, providing the first contact pad 117 is bonded to the second contact pad 119, electrical connection of the second transistor 202 to the first transistor may be achieved.

In some embodiments, the second redistribution layer 118 also has a wiring layer therein, which may be, for example, a copper wiring layer.

In some embodiments, the second redistribution layer 118 may include a third dielectric layer 32 and a fourth dielectric layer 31 stacked in sequence, where the third dielectric layer 32 is in contact with the surface of the second substrate 201, the wiring layer may be located in the third dielectric layer 32, and the third dielectric layer 32 may protect and isolate the wiring layer. The second contact pad 119 may be disposed in a fourth dielectric layer 31, the fourth dielectric layer 31 protecting and isolating the second contact pad 119. In some embodiments, the material of the third dielectric layer 32 may be at least one of oxide and silicon nitride; the material of the fourth dielectric layer 31 may be at least one of oxide and silicon nitride.

In some embodiments, the second substrate 201 may have a second bit line structure and a second word line structure therein, wherein a source of the second transistor is electrically connected to the second bit line structure and a gate of the second transistor is electrically connected to the second word line structure. The second word line structure may be a buried word line structure located in the second substrate 201, with the second bit line structure located on top of the second word line structure. In some embodiments, the number of the second word line structures and the second bit line structures may be plural, and the extending directions of the second word line structures and the second bit line structures are different.

Referring to fig. 6, in some embodiments, the semiconductor structure further comprises: and a third re-wiring layer 120, the third re-wiring layer 120 being located on the second side 5 of the second substrate 201, the third re-wiring layer 120 comprising a plurality of third contact pads 121, the plurality of third contact pads 121 being coupled to at least a portion of the second transistors. The third contact pad 121 and the second contact pad 119 are respectively located at opposite sides of the second substrate 201, wherein the second contact pad 119 in the second redistribution layer 118 is used for forming an electrical connection between the second transistor and the first transistor, and the third contact pad 121 can implement signal transmission between the second transistor and an external element, so that the second transistor can receive an external signal and transmit the signal to the outside.

In the semiconductor structure provided in the foregoing embodiment, the word line structure 105 in the first transistor stack layer is located at the top of the capacitor stack layer, so that the capacitor structure 102 does not shade the word line structure 105, and when the electrical signal of the word line structure 105 is actually led out, the electrical connection structure for leading out the word line structure 105 may be electrically connected with the middle of the word line structure 105 or the end of the word line structure 105, so as to improve the flexibility of the electrical connection structure, further improve the transmission of the electrical signal in the word line structure 105, enhance the driving capability of the word line structure 105, and improve the telecommunication energy of the semiconductor structure.

Accordingly, the embodiment of the present disclosure further provides a method for manufacturing a semiconductor structure, which may be used to manufacture the semiconductor structure provided in the foregoing embodiment, and the method for manufacturing a semiconductor structure provided in one embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings.

Fig. 8 to 23 are schematic structural diagrams corresponding to each step in a method for manufacturing a semiconductor structure according to another embodiment of the disclosure.

The preparation method of the semiconductor structure comprises the following steps: referring to fig. 8 to 13, a capacitor stack layer including a capacitor structure 102 is formed on a first substrate 101.

In some embodiments, forming a capacitor stack layer includes:

referring to fig. 8, a first dielectric layer 11, a first electrode layer 12, and a second dielectric layer 13, which are sequentially stacked, are formed on a first substrate 101. In some embodiments, the first dielectric layer 11, the first electrode layer 12, and the second dielectric layer 13 sequentially stacked may be formed on the first substrate 101 using a deposition process, which may be one of an atomic layer deposition process or a chemical vapor deposition process.

In some embodiments, the material of the first electrode layer 12 may be a semiconductor conductive material, for example, silicon germanium. The material of the first dielectric layer 11 may be silicon nitride, and the material of the second dielectric layer 13 may be silicon nitride.

Referring to fig. 9, the second dielectric layer 13 and the first electrode layer 12 are etched to form a capacitor hole 50. In some embodiments, the method of etching the second dielectric layer 13 and the first electrode layer 12 may include: first, forming a first mask layer on the top surface of the second dielectric layer 13, and performing a patterning process on the first mask layer until the top surface of the second dielectric layer 13 is exposed to define the opening shape of the capacitor hole 50 in the first mask layer, wherein in some embodiments, the method of performing the patterning process on the first mask layer may be any one of SADP (Self-aligned Double Patterning, self-aligned dual imaging technology) or SADP (Self-Aligned Quadruple Patterning, self-aligned multiple exposure technology); and etching the second dielectric layer 13 with the top surface exposed until the top surface of the first electrode layer 12 is exposed, and continuing to etch the top surface of the first electrode layer 12 until the top surface of the first dielectric layer 11 is exposed, so as to form the capacitor hole 50.

Referring to fig. 10 to 12, a capacitance dielectric layer 14 and a second electrode layer 15 are formed in the capacitance hole 50, the capacitance dielectric layer 14 covering the sidewall and the bottom of the capacitance hole 50, the second electrode layer 15 covering the capacitance dielectric layer 14 and filling the capacitance hole 50; the capacitor structure 102 includes, among other things, a first electrode layer 12, a capacitive dielectric layer 14, and a second electrode layer 15.

Referring to fig. 10, in some embodiments, a deposition process may be used to form an initial capacitive dielectric layer 20 in the capacitive aperture 50, the initial capacitive dielectric layer 20 also being located on top of the second dielectric layer 13. In some embodiments, the deposition process may be one of an atomic layer deposition process or a chemical vapor deposition. In some embodiments, the material of the initial capacitive dielectric layer 20 may be a high dielectric constant material.

In some embodiments, a deposition process may be used to fill the remaining capacitive holes 50 with an initial second electrode layer that is higher than the open top surface of the capacitive holes 50, and that is also located on top of the initial capacitive dielectric layer 20 that is in contact with the top surface of the second dielectric layer 13. In some embodiments, the deposition process may be one of an atomic layer deposition process or a chemical vapor deposition. In some embodiments, the material of the initial second electrode layer may be at least one of a metallic material or a semiconductor material, for example, may be at least one of tungsten or titanium nitride.

Referring to fig. 11, after forming the initial second electrode layer, an etching back process is performed on the initial capacitance dielectric layer 20 (refer to fig. 10) and the initial second electrode layer, the initial capacitance dielectric layer 20, the initial second electrode layer and the initial second electrode layer above the opening of the capacitance hole 50 are removed at the top of the second dielectric layer 13, the remaining initial capacitance dielectric layer 20 and the remaining initial second electrode layer form the capacitance dielectric layer 14 and the second electrode layer 15, and the second electrode layer 15 is flush with the opening of the capacitance hole 50 (refer to fig. 10). In some embodiments, the etch back process may be any one of a planarization process or a chemical mechanical polishing process.

Referring to fig. 12, in some embodiments, the method of fabricating a semiconductor structure further includes: a capacitor cap layer 19 is formed on the top surface of the second dielectric layer 13, and the capacitor cap layer 19 may be used to protect the first electrode layer 12 and enhance isolation. In some embodiments, the material of the capacitor cap layer 19 may be silicon nitride.

Referring to fig. 13, in some embodiments, forming the capacitor stack layer further comprises: a capacitive contact structure 18 is formed, the capacitive contact structure 18 being coupled to the second electrode layer 15.

In some embodiments, a method of forming the capacitive contact structure 18 may include: forming an initial capacitance contact structure on the top surface of the second electrode layer 15, the top surface of the capacitance cover layer 19 and the side wall, wherein the initial capacitance contact structure is higher than the top surface of the capacitance cover layer 19; patterning the initial capacitance contact structure, for example, the initial capacitance contact structure may be patterned by using an SADP process or an SADP process; the patterned initial capacitive contact structure is etched to remove a portion of the initial capacitive contact structure directly opposite the top surface of the second electrode layer 15 and a portion of the initial capacitive contact structure directly opposite the top surface of the capacitive cap layer 19, to form a capacitive contact structure 18. The capacitive contact structure 18 includes a first portion in electrical contact with a portion of the top surface of the first electrode layer 12 and a second portion in contact with a portion of the top surface of the capacitive cap layer 19.

Referring to fig. 14, in some embodiments, the method of fabricating a semiconductor structure further includes: a first planarization layer 107 is formed overlying the capacitive contact structure 18. In some embodiments, a deposition process may be used to deposit an initial first planarizing layer on top of the capacitive contact structure 18, the initial first planarizing layer top surface being higher than the capacitive contact structure 18 top surface; the initial first planarization layer is subjected to a planarization process to form a first planarization layer 107.

Referring to fig. 15 to 19, after forming the capacitor stack layer, a first transistor stack layer is formed on the capacitor stack layer, the first transistor stack layer including a first insulating layer 103, a semiconductor layer 104, and a word line structure 105, the first insulating layer 103 having a trench, the semiconductor layer 104 including a channel region located within the trench and first and second source and drain regions located on top of the first insulating layer 103 on both sides of the trench, the word line structure 105 covering the channel region and filling the trench.

In some embodiments, forming a first transistor stack layer includes:

referring to fig. 15, a first insulating layer 103 is formed on the capacitor stack layer, and in some embodiments, the first insulating layer 103 may be formed using a deposition process, for example, an atomic layer deposition process may be used. In some embodiments, the material of the first insulating layer 103 may be silicon oxide, and then a thermal oxidation method may be further used to form the first insulating layer 103.

Referring to fig. 16, the first insulating layer 103 is etched to form a trench 51. In some embodiments, the first insulating layer 103 may be first subjected to a patterning process to define the opening of the trench 51, and then the patterned first insulating layer 103 is subjected to an etching process to form the trench 51. In some embodiments, trench 51 may be formed using either a dry etching process or a wet etching process.

Referring to fig. 17, a semiconductor material layer is formed to cover the first insulating layer 103 in a conformal manner, and the semiconductor material layer is patterned to form a semiconductor layer 104. In some embodiments, the semiconductor material layer may be formed using a deposition process, such as an atomic layer deposition process or a chemical vapor deposition process; the semiconductor layer 104 is formed to cover the surface of the trench 51 and the top surface of the first insulating layer 103, wherein the semiconductor layer 104 on the surface of the trench 51 may be used as the channel region 1 (refer to fig. 1) to form a channel of the first transistor, the semiconductor layer 104 on the top surface of the first insulating layer 103 is located on two sides of the semiconductor material layer of the channel region 1 and is used as the first source drain region 2 (refer to fig. 1) and the second source drain region 3 (refer to fig. 1) to form a source and a drain of the first transistor, respectively.

In some embodiments, the material of the semiconductor material layer may be an oxide semiconductor material (e.g., a metal oxide semiconductor material) or a sulfide semiconductor material, for example, may be any of IGZO, zinc oxide, indium gallium oxide, zinc sulfide, or the like.

Referring to fig. 18, a word line structure 105 is formed. In some embodiments, a method of forming the word line structure 105 may include:

a deposition process is used to form the gate dielectric layer 16 on the surface of the semiconductor layer 104 in the channel region, and in some embodiments, the gate dielectric layer 16 may be formed by using a thermal oxidation method, where the material of the gate dielectric layer 16 is silicon oxide.

And forming a word line body 17 on the surface of the gate dielectric layer 16 by adopting a deposition process, wherein the word line body 17 fills the groove 51. In some embodiments, an initial word line body may be first formed, the initial word line body filling the trench 51, and a top surface of the initial word line body being higher than the trench 51 open top; and performing an etching back process on the initial word line body to remove the initial word line body higher than the opening of the groove 51, and forming a word line body 17 by keeping the remaining initial word line body not higher than the opening of the groove 51.

In some embodiments, the material of the initial word line body may be at least one of a metal or a metal oxide, such as at least one of tungsten or titanium nitride.

Referring to fig. 19, a second planarization layer 109 is formed, the second planarization layer 109 covering the first insulating layer 103, the semiconductor layer 104, and the word line structure 105. In some embodiments, a deposition process may be used to form an initial second planarization layer on the top surface of the first insulating layer 103, the top surface of the semiconductor layer 104, and the top surface of the word line structure 105, and then a planarization process is performed on the initial second planarization layer to form the second planarization layer 109, so that the second planarization layer 109 has a flat surface. In some embodiments, the material of the second planarization layer 109 may be silicon nitride.

Referring to fig. 20 and 21, after forming the first transistor stack layer, a first via 52 penetrating the first transistor stack layer is formed, and a first contact plug 106 is formed within the first via 52, the first source drain region 2 being coupled with the capacitor structure 102 through the first contact plug 106. In some embodiments, the first planarization layer 107 is further formed before the first transistor stack layer is formed, and then the first via 52 further penetrates through the first planarization layer 107, and the first contact plug 106 is formed to be coupled with the capacitor contact structure 18.

In some embodiments, a method of forming the first via 52 may include: forming a second mask layer on the top surface of the second planarization layer 109; the second mask layer is patterned, for example, by using an SADP process or an SADP process, to define an opening of the first via 52 in the second mask layer. Next, the second planarization layer 109, the semiconductor layer 104 of the first source drain region 2, the first insulating layer 103, and the first planarization layer 107 are etched along the opening until the top surface of the capacitor contact structure 18 is exposed, thereby forming a first via 52.

Referring to fig. 21, after the first via hole 52 is formed, a first contact plug 106 is formed in the first via hole 52. In some embodiments, the material of the first contact plug 106 may be at least one of a metal or a metal oxide, for example, at least one of tungsten or titanium nitride.

Referring to fig. 2, in some embodiments, the method of fabricating a semiconductor structure further includes: a second via (not shown) is formed through the first transistor stack layer, the first planarization layer 107 and the second dielectric layer 13, and a second contact plug 108 is formed in the second via, the second contact plug 108 being coupled to the first electrode layer 12. In some embodiments, the method of forming the second via may be the same as the method of forming the first via 52, except that the second via also penetrates the second dielectric layer 13, exposing the top surface of the first electrode layer 12, and the second via also penetrates the first insulating layer. It is noted that the first via 52 also penetrates a portion of the semiconductor layer 104 (refer to fig. 1), while the second via does not penetrate the semiconductor layer 104. The second contact plug 108 formed in the second via hole is in electrical contact with the top surface of the first electrode layer 12. In some embodiments, the material of the second contact plug 108 may be at least one of a metal or a metal oxide, for example, at least one of tungsten or titanium nitride.

Referring to fig. 1 and 3, in some embodiments, the method for fabricating a semiconductor structure further includes: forming a bit line structure on the first transistor stack layer, the bit line structure being coupled to the second source drain region 3; a first re-wiring layer 116 is formed on the bit line structure, the first re-wiring layer 116 including a plurality of first contact pads 117, the plurality of first contact pads 117 being coupled with the bit line structure, the word line structure 105 and the second contact plugs 108, respectively.

In some embodiments, prior to forming the bit line structure, further comprising: a second insulating layer 110 (see fig. 1) is formed on top of the second planarizing layer 109 using a deposition process, the second insulating layer 110 isolating and supporting the bit line structure, and in some embodiments, the material of the second insulating layer 110 may be silicon oxide.

In some embodiments, a method of forming a bit line structure may include:

referring to fig. 22, a third via hole 54 penetrating the second planarization layer 109 and the second insulating layer 110 is formed using an etching process, and the third via hole 54 exposes the top surface of the semiconductor layer 104 of the second source drain region 3 (refer to fig. 1).

Referring to fig. 23, a bit line contact plug 111 is formed in the third via 54 using a deposition process, and a bit line body 112 is formed on the top surface of the second insulating layer 110, the bit line body 112 being in electrical contact with the bit line contact plug 111. In some embodiments, the material of the bit line contact plug 111 may be at least one of metal or metal oxide, for example, at least one of tungsten or titanium nitride. The material of the bit line body 112 may be at least one of metal or metal oxide, for example, at least one of tungsten or titanium nitride.

Referring to fig. 1, a bit line cap layer 113 is formed on top of the bit line body 112 using a deposition process, and in some embodiments, the material of the bit line cap layer 113 may be silicon nitride. The bit line contact structure, bit line body 112, and bit line cap 113 constitute a bit line structure.

Referring to fig. 3, in some embodiments, the first redistribution layer may include a stacked first dielectric layer 21 and second dielectric layer 22, the first dielectric layer 21 may include a wiring layer therein, the first contact pad 117 may be located in the second dielectric layer 22, and the wiring layer may be used to electrically connect the first contact pad 117 with the bit line structure, the word line structure 105, and the second contact plug 108 (refer to fig. 2).

In some embodiments, the first dielectric layer 21 may be formed first on top of the bit line structure. In some embodiments, the wiring layer in the first dielectric layer 21 may include: a third contact plug 25, a fourth contact plug 26, and a fifth contact plug 27. The bit line body 112 is coupled to one first contact pad 117 through a third contact plug 25, and the conductive portion in the word line structure 105 is coupled to the other first contact pad 117 through a fourth contact plug 26; the second contact plug 108 is coupled with a further first contact pad 117 via a fifth contact plug 27.

Referring to fig. 4, in some embodiments, a third contact plug 25 may be formed through the bit line cap layer 113 in electrical contact with the top of the bit line body 112, and the third contact plug 25 also penetrates through the first dielectric layer 21. Because the bit line cover layer 113 is located at the top and is not shielded by the capacitor structure 102, in the process of forming the third contact plug 25, the third contact plug 25 can be arranged to penetrate through the bit line cover layer 113 corresponding to the middle part of the bit line structure, so as to perform signal transmission in the middle part of the bit line structure, shorten the signal transmission path, improve the signal transmission rate and strength, and enhance the signal transmission capability of the first transistor.

In some embodiments, if the number of bit line structures is multiple, then it may further include: a bit line isolation structure 130 (refer to fig. 5) is formed between adjacent bit line structures.

Referring to fig. 3 and 5, the fourth contact plug 26 may electrically contact the word line body 17 through the bit line isolation structure 130, and the fourth contact plug 26 also penetrates the first dielectric layer 21. Since the top of the word line structure 105 is not shielded by the capacitor structure 102, in the process of forming the fourth contact plug 26, the fourth contact plug 26 may be disposed to penetrate through the bit line isolation structure 130, the second insulating layer 110 and the second planarization layer 109 opposite to the middle of the word line structure 105 (refer to fig. 1), so as to perform signal transmission in the middle of the word line structure 105, shorten the signal transmission path, increase the transmission rate of signals into the bit line structure, enhance the driving capability of the word line structure 105, and further improve the electrical performance of the semiconductor structure.

In some embodiments, the fifth contact plug 27 may electrically contact the top of the second contact plug 108 through the bit line isolation structure 130, the bit line body 112, and the second insulating layer 110, and also through the first dielectric layer 21.

Referring to fig. 3, in some embodiments, a method of forming the first dielectric layer 21 may include: a deposition process is used to form a first dielectric layer 21 on top of the bit line structure, and the material of the first dielectric layer 21 may be at least one of oxide and silicon nitride.

After the first dielectric layer 21 is formed, a third contact plug 25, a fourth contact plug 26, and a fifth contact plug 27 are formed in the first dielectric layer 21. In some embodiments, the materials of the third contact plug 25, the fourth contact plug 26, and the fifth contact plug 27 may be at least one of metal oxide or metal, for example, at least one of titanium nitride or tungsten.

After the first dielectric layer 21 is formed, a second dielectric layer 22 is formed on the top surface of the first dielectric layer 21, and the second dielectric layer 22 is formed in the same manner as the first dielectric layer 21. In some embodiments, the material of the second dielectric layer 22 may include at least one of an oxide and silicon nitride.

After forming the second dielectric layer 22, the first contact pad 117 is formed, and in some embodiments, the second dielectric layer 22 may be etched to form a plurality of fourth vias (not shown) in the second dielectric layer 22, the fourth vias exposing the third contact plug 25, the fourth contact plug 26, and the fifth contact plug surface. The first contact pad 117 is then formed in the fourth via using an electroplating process, and in some embodiments, the material of the first contact pad 117 may include any of copper, aluminum, tin, or gold.

Referring to fig. 6 and 7, in some embodiments, the method of fabricating a semiconductor structure further includes: providing a second substrate 201, the second substrate 201 having opposite first and second sides 4, 5; forming a plurality of second transistors 202 on the first side 4; forming a second redistribution layer 118 overlying the plurality of second transistors 202, the second redistribution layer 118 including a plurality of second contact pads 119, the plurality of second contact pads 119 being coupled to at least a portion of the second transistors 202; the second substrate 201 is bonded to the first substrate 101 such that the plurality of first contact pads 117 are correspondingly connected to the plurality of second contact pads 119.

In some embodiments, where the first substrate 101 is used to form an array region and the second substrate 201 is used to form a peripheral region, providing the first contact pad 117 is bonded to the second contact pad 119, electrical connection of the second transistor to the first transistor may be achieved.

In some embodiments, the second redistribution layer 118 may include a third dielectric layer 32 and a fourth dielectric layer 31 stacked in sequence, where the third dielectric layer 32 is in contact with the surface of the second substrate 201, the wiring layer may be located in the third dielectric layer 32, and the third dielectric layer 32 may protect and isolate the wiring layer. The second contact pad 119 may be disposed in a fourth dielectric layer 31, the fourth dielectric layer 31 protecting and isolating the second contact pad 119.

In some embodiments, the method of forming the third dielectric layer 32, the fourth dielectric layer 31, and the second contact pad 119 may refer to the description of forming the first dielectric layer 21 and the second dielectric layer 22 above. In some embodiments, the material of the third dielectric layer 32 may be at least one of oxide and silicon nitride; the material of the fourth dielectric layer 31 may be at least one of oxide and silicon nitride. The material of the second contact pad 119 includes any one of copper, aluminum, tin, or gold.

The first contact pad 117 and the second contact pad 119 are correspondingly connected, and the second transistor 202 and the first transistor can be coupled.

In some embodiments, the method of fabricating a semiconductor structure further comprises: thinning the second substrate 201 from the second side 5; a third re-wiring layer 120 is formed on the second side 5 of the thinned second substrate 201, the third re-wiring layer 120 comprising a plurality of third contact pads 121, the plurality of third contact pads 121 being coupled to at least part of the second transistors. In some embodiments, the method of forming the third re-wiring layer 120 may refer to the method of forming the first re-wiring layer 116 or the method of forming the second re-wiring layer 118 described above.

The third contact pad 121 may enable signal transmission of the second transistor 202 with an external element, so that the second transistor 202 may receive an external signal and transmit the signal to the outside. In some embodiments, the material of the third contact pad 121 includes any of copper, aluminum, tin, or gold.

In the method for manufacturing a semiconductor structure provided in the foregoing embodiments, the first transistor stack layer is formed on top of the capacitor stack layer, so that the capacitor structure 102 does not shade the word line structure 105, and when the electrical connection structure for leading out the word line structure 105 is actually formed, the electrical connection structure may be electrically connected with the middle of the word line structure 105 or the end of the word line structure 105, so as to improve the flexibility of the electrical connection structure, further improve the transmission of electrical signals in the word line structure 105, enhance the driving capability of the word line structure 105, and improve the electrical performance of the semiconductor structure.

It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of implementing the disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the disclosure, and the scope of the disclosure should be assessed accordingly to that of the appended claims.

Claims

1. A semiconductor structure, comprising:

a first substrate;

a capacitor stack layer on the first substrate, the capacitor stack layer including a capacitor structure therein;

a first transistor stack layer on the capacitor stack layer, the first transistor stack layer including a first insulating layer having a trench, a semiconductor layer including a channel region within the trench and first and second source drain regions on top of the first insulating layer on both sides of the trench, and a word line structure covering the channel region and filling the trench;

and the first source-drain region is coupled with the capacitor structure through the first contact plug.

2. The semiconductor structure of claim 1, wherein the capacitor stack layer comprises:

a first dielectric layer, a first electrode layer and a second dielectric layer which are sequentially laminated on the first substrate;

capacitance holes in the first electrode layer and the second dielectric layer;

the capacitor dielectric layer covers the side wall and the bottom of the capacitor hole, and the second electrode layer covers the capacitor dielectric layer and fills the capacitor hole;

the capacitor structure comprises the first electrode layer, the capacitance medium layer and the second electrode layer, and the first source drain region is coupled with the second electrode layer through the first contact plug.

3. The semiconductor structure of claim 2, wherein the capacitor stack layer further comprises:

a capacitive contact structure coupled to the second electrode layer;

a first planarization layer covering the capacitor contact structure;

the first contact plug also penetrates through the first planarization layer and is coupled with the capacitance contact structure.

4. The semiconductor structure of claim 3, further comprising: and a second contact plug penetrating the first transistor stack layer, the first planarization layer, and the second dielectric layer, the second contact plug being coupled with the first electrode layer.

5. The semiconductor structure of claim 4, wherein the first transistor stack layer further comprises a second planarization layer covering the first insulating layer, the semiconductor layer, and the word line structure; the semiconductor structure further includes: a bit line structure on top of the second planarization layer, the bit line structure comprising: the bit line contact plug also penetrates through the second planarization layer and is coupled with the semiconductor layer of the second source drain region.

6. The semiconductor structure of claim 5, further comprising: the first rewiring layer is located on the top surface of the bit line structure and comprises a plurality of first contact pads, and the first contact pads are respectively coupled with the bit line structure, the word line structure and the second contact plugs.

7. The semiconductor structure of claim 6, further comprising:

a third contact plug penetrating at least a portion of the film layer in the first re-wiring layer, the bit line body being coupled with one of the first contact pads through the third contact plug;

A fourth contact plug penetrating at least a portion of the film layer in the first re-wiring layer and the second planarization layer, the conductive portion in the word line structure being coupled with another one of the first contact pads through the fourth contact plug;

and a fifth contact plug penetrating at least part of the film layer in the first re-wiring layer, the second contact plug being coupled with the first contact pad through the fifth contact plug.

8. The semiconductor structure of claim 6, further comprising:

a second substrate having opposite first and second sides, the first side having a plurality of second transistors thereon; and the second redistribution layer is positioned on the first side of the second substrate and covers the plurality of second transistors, the second redistribution layer comprises a plurality of second contact pads, the plurality of second contact pads are at least coupled with part of the second transistors, and the plurality of first contact pads and the plurality of second contact pads are correspondingly connected in a bonding mode.

9. The semiconductor structure of claim 8, further comprising: and a third redistribution layer located on the second side of the second substrate, the third redistribution layer including a plurality of third contact pads, the plurality of third contact pads being coupled to at least a portion of the second transistors.

10. The semiconductor structure of claim 1, wherein the material of the semiconductor layer comprises an oxide semiconductor material.

11. A method of fabricating a semiconductor structure, comprising:

forming a capacitor stack layer on a first substrate, the capacitor stack layer comprising a capacitor structure;

forming a first transistor stack layer on the capacitor stack layer, the first transistor stack layer including a first insulating layer having a trench, a semiconductor layer including a channel region located within the trench and first and second source drain regions located on top of the first insulating layer on both sides of the trench, and a word line structure covering the channel region and filling the trench;

a first via is formed through the first transistor stack layer and a first contact plug is formed within the first via, the first source drain region being coupled to the capacitor structure through the first contact plug.

12. The method of fabricating a semiconductor structure of claim 11, wherein forming the capacitor stack layer comprises:

forming a first dielectric layer, a first electrode layer and a second dielectric layer which are stacked in sequence on the first substrate;

Etching the second dielectric layer and the first electrode layer to form a capacitor hole;

forming a capacitance medium layer and a second electrode layer in the capacitance hole, wherein the capacitance medium layer covers the side wall and the bottom of the capacitance hole, and the second electrode layer covers the capacitance medium layer and fills the capacitance hole;

the capacitor structure comprises the first electrode layer, the capacitance medium layer and the second electrode layer.

13. The method of fabricating a semiconductor structure of claim 12, wherein forming the capacitor stack layer further comprises:

forming a capacitance contact structure, wherein the capacitance contact structure is coupled with the second electrode layer;

forming a first planarization layer covering the capacitor contact structure;

the first through hole penetrates through the first planarization layer, and the first contact plug is coupled with the capacitance contact structure.

14. The method of manufacturing a semiconductor structure of claim 13, wherein forming the first transistor stack layer comprises:

forming the first insulating layer on the capacitor stack layer;

etching the first insulating layer to form the trench;

Forming a semiconductor material layer covering the first insulating layer in a conformal manner;

patterning the semiconductor material layer to form the semiconductor layer;

forming the word line structure;

a second planarization layer is formed overlying the first insulating layer, the semiconductor layer, and the word line structure.

15. The method of fabricating a semiconductor structure of claim 14, further comprising:

and forming a second through hole penetrating through the first transistor stack layer, the first planarization layer and the second dielectric layer, and forming a second contact plug in the second through hole, wherein the second contact plug is coupled with the first electrode layer.

16. The method of fabricating a semiconductor structure of claim 15, further comprising:

forming a bit line structure on the first transistor stack layer, the bit line structure being coupled to the second source drain region;

a first redistribution layer is formed over the bit line structure, the first redistribution layer including a plurality of first contact pads coupled with the bit line structure, the word line structure, and the second contact plugs, respectively.

17. The method of fabricating a semiconductor structure of claim 16, further comprising:

providing a second substrate having opposite first and second sides;

forming a plurality of second transistors on the first side;

forming a second redistribution layer overlying the plurality of second transistors, the second redistribution layer including a plurality of second contact pads, the plurality of second contact pads being coupled to at least a portion of the second transistors;

and bonding the second substrate with the first substrate so as to correspondingly connect the plurality of first contact pads with the plurality of second contact pads.

18. The method of fabricating a semiconductor structure of claim 17, further comprising:

thinning the second substrate from the second side;

forming a third re-wiring layer on the thinned second side of the second substrate, the third re-wiring layer including a plurality of third contact pads, the plurality of third contact pads being coupled to at least a portion of the second transistors.