KR20020001144A - Method of manufacturing a semiconductor device - Google Patents
Method of manufacturing a semiconductor device Download PDFInfo
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- KR20020001144A KR20020001144A KR1020000035355A KR20000035355A KR20020001144A KR 20020001144 A KR20020001144 A KR 20020001144A KR 1020000035355 A KR1020000035355 A KR 1020000035355A KR 20000035355 A KR20000035355 A KR 20000035355A KR 20020001144 A KR20020001144 A KR 20020001144A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 238000000034 method Methods 0.000 claims abstract description 66
- 239000011229 interlayer Substances 0.000 claims abstract description 39
- 239000010410 layer Substances 0.000 claims abstract description 32
- 125000006850 spacer group Chemical group 0.000 claims abstract description 28
- 229910020286 SiOxNy Inorganic materials 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 14
- 239000010703 silicon Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000007789 gas Substances 0.000 claims description 23
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 claims description 18
- 239000012495 reaction gas Substances 0.000 claims description 18
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 17
- 238000001312 dry etching Methods 0.000 claims description 15
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- 238000010438 heat treatment Methods 0.000 claims description 11
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 11
- 150000004767 nitrides Chemical class 0.000 claims description 9
- 238000009832 plasma treatment Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 4
- -1 NH 4 0H Chemical compound 0.000 claims description 3
- 230000032683 aging Effects 0.000 claims description 3
- 230000002209 hydrophobic effect Effects 0.000 claims description 3
- 239000011261 inert gas Substances 0.000 claims description 3
- 238000005121 nitriding Methods 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 abstract description 6
- 239000003990 capacitor Substances 0.000 abstract description 2
- 238000000137 annealing Methods 0.000 abstract 1
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 9
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 229910004205 SiNX Inorganic materials 0.000 description 3
- 230000002265 prevention Effects 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 208000030623 Low phospholipid-associated cholelithiasis Diseases 0.000 description 1
- 229910019897 RuOx Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910008482 TiSiN Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 230000001502 supplementing effect Effects 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 게이트 배선 및 비트라인과 같은 금속 배선 간의 기생 커패시턴스를 감소시키고 금속 배선 간의 크로스 토크를 방지할 수 있는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of reducing parasitic capacitance between metal wirings such as gate wirings and bit lines and preventing cross talk between metal wirings.
반도체 소자가 고집적화 됨에 따라 금속 배선간의 크로스 토크(Cross Talk)를 방지하고, 동작속도를 빠르게 하기 위하여, 비저항이 낮은 구리금속 배선을 사용하거나, 금속 배선간에 유전율이 낮은 절연막을 사용하는 것이 반도체 소자 제조에 있어 중요한 기술로 대두되고 있으며, 많은 연구가 이루어지고 있다. 또한 금속배선 사이에 형성된 절연막의 유전율 감소 뿐 아니라 금속 배선 형성 전에 적용된 층간 절연막의 유전율 감소를 통해 기생 캐패시턴스를 감소시켜 소자의 속도를 향상시키는 것 또한 매우 중요하다. 그러나, 이러한 금속 배선을 형성하기 전에 형성하는 저유전율 층간 절연막의 적용에 대한 연구는 이루어지지 않고 있다.As semiconductor devices are highly integrated, in order to prevent cross talk between metal wires and to increase the operation speed, it is necessary to use low-resistance copper metal wires or to use insulating films having low dielectric constant between metal wires. Has emerged as an important technology in the field, and much research has been done. In addition, it is also important to improve the speed of the device by reducing the parasitic capacitance by decreasing the dielectric constant of the insulating film formed between the metal wirings and the dielectric constant of the interlayer insulating film applied before the metal wiring is formed. However, research on the application of the low dielectric constant interlayer insulating film formed before forming such a metal wiring has not been conducted.
층간 절연막의 유전율 감소를 이루기 위해서는 첫 번째로 자기 정렬 콘택 식각 방지막(SAC etch barrier)의 저유전율화 및 균일한 층덮힘성(Step coverage)을 확보해야 하고, 두 번째로 SAC 식각 방지막과 층간 절연막과의 충분한 건식 식각 선택비를 확보해야 하며, 세 번째로 층간 절연막의 저유전율화 및 400℃ 이상의 열 안정성 확보 등이 필요하다.In order to reduce the dielectric constant of the interlayer insulating film, firstly, the low dielectric constant and uniform step coverage of the self-aligned contact etch barrier must be ensured, and second, the SAC etch barrier and the interlayer insulating film must be secured. Sufficient dry etching selectivity should be secured, and thirdly, low dielectric constant of interlayer insulating film and thermal stability over 400 ° C should be secured.
이와 같이 층간 절연막의 유전율을 감소시키기 위해서는 실리콘 질화막(SiNx)과 층간 절연막을 저유전율의 막으로 형성하는 방법이 있다. 여기서실리콘 질화막은 게이트 배선 및 비트 라인(Bit Line) 형성 후, 후속 콘택을 형성하는 자기 정렬 콘택(SAC) 식각(Etch) 공정에서 방지막(Barrier Layer)으로 사용되는 막이며, 층간 절연막은 게이트 배선 및 비트 라인 사이의 굴곡을 매립 및 평탄화 하기 위한 막이다.Thus, in order to reduce the dielectric constant of the interlayer insulating film, there is a method of forming a silicon nitride film (SiNx) and an interlayer insulating film as a low dielectric constant film. Here, the silicon nitride film is a film used as a barrier layer in a self-aligned contact (SAC) etching process to form a subsequent contact after the formation of the gate wiring and the bit line, and the interlayer insulating film is a gate wiring and It is a film for embedding and planarizing the bending between the bit lines.
특히 게이트 배선 및 비트 라인 사이에는 셀 트랜지스터 동작을 위한 콘택이 형성되는데, 금속 배선을 형성하기 전에 SAC 방지막을 포함하는 층간 절연막에서 기생 캐패시턴스 발생원인의 약 80%는 SAC 방지막에 의한 것이고, 나머지는 평탄화용 절연막에 기인한 것이다. 따라서 SAC 방지막으로 주로 사용되는 유전율 7의 실리콘 질화막(SiNx)층의 유전율을 감소시키는 것이 중요하다. 이를 위해 유전율 4의 실리콘 산화막을 사용하는 방법이 있으나, 기존의 산화막을 그대로 사용하는 경우, 배선간 층간 절연막으로 사용되는 실리콘 산화막과의 SAC 에치 선택 비가 확보되지 않아 적용할 수 없다.In particular, a contact for cell transistor operation is formed between the gate wiring and the bit line. Before forming the metal wiring, about 80% of the causes of parasitic capacitance in the interlayer insulating film including the SAC prevention film are caused by the SAC prevention film, and the rest is planarized. This is due to the insulating film for solvent. Therefore, it is important to reduce the dielectric constant of the silicon nitride film (SiNx) layer having a dielectric constant of 7, which is mainly used as the SAC prevention film. To this end, there is a method of using a silicon oxide film having a dielectric constant of 4, but if the existing oxide film is used as it is, it cannot be applied because the SAC etch selectivity with the silicon oxide film used as the interlayer insulating film between wires is not secured.
도 1을 참조하면, 반도체 기판(1) 상에 다수의 패턴화 된 게이트(2)와 후속 SAC 식각시 게이트(2) 상부가 손상되는 것을 막기 위한 마스크 절연막(3)을 형성하고, 전체구조 상에 SAC 식각 방지막으로 기존의 LPCVD SiNx막 대신에 유전율이 낮은 LPCVD SiO2막을 형성한 후 전면 건식식각으로 스페이서 절연막(4)을 형성한다. 전면 건식식각으로 스페이서 절연막(4)을 형성하면서 접합부(5)를 노출시킨 후 저유전율 층간 절연막(6)으로 평탄화 한 후 SAC 식각 공정을 실시한 상태를 나타내었다. 도시한 바와 같이, SAC 식각 공정에서 스페이서 절연막(4)과 다공정 저유전율층간 절연막(6) 사이의 건식 식각 선택비가 부족하여, 게이트 배선이 손상을 받게 된다.Referring to FIG. 1, a mask insulating layer 3 is formed on a semiconductor substrate 1 to prevent damage to a plurality of patterned gates 2 and an upper portion of a gate 2 during subsequent SAC etching. An LPAC SiO 2 film having a low dielectric constant is formed instead of the conventional LPCVD SiN x film as a SAC etch film, and then a spacer insulating film 4 is formed by dry etching over the entire surface. A state in which the SAC etching process was performed after exposing the junction part 5 while forming the spacer insulating film 4 by the entire dry etching, and then planarizing the low dielectric constant interlayer insulating film 6 was performed. As shown, the dry etching selectivity between the spacer insulating film 4 and the multi-step low dielectric constant interlayer insulating film 6 is insufficient in the SAC etching process, resulting in damage to the gate wiring.
도 2를 참조하면, 도 1에 도시한 구조에서 스페이서 절연막(24)을 기존의 LPCVD SiNx막 대신에 플라즈마 화학 기상 증착법(PECVD)으로 형성한 유전율이 낮은 SiOxNy막을 이용해 형성하고, 전면 건식 식각으로 접합부(25)를 노출시킨 후 저유전율 층간 절연막(26)으로 평탄화 한 후 SAC 식각 공정을 실시한 상태를 도시하고 있다. 도시한 바와 같이, PECVD SiOxNy막을 이용해 형성한 스페이서 절연막(24)은 열악한 층덮힘성에 기인하여, 패턴 사이가 좁은 셀 영역(27)과 패턴 사이가 넓은 주변 회로 영역(8)에서의 증착 두께가 달라, 전면 건식식각에 의한 정션 부위 노출 공정에서 스페이서 절연막(24)의 두께가 얇게 형성된 셀 영역의 접합부(25)가 손상받게 된다.Referring to FIG. 2, in the structure shown in FIG. 1, a spacer insulating film 24 is formed using a low dielectric constant SiOxNy film formed by plasma chemical vapor deposition (PECVD) instead of a conventional LPCVD SiNx film, and is bonded by dry etching. A state in which the SAC etching process is performed after exposing (25) and planarizing with the low dielectric constant interlayer insulating film 26 is shown. As shown, the spacer insulating film 24 formed using the PECVD SiOxNy film has a different deposition thickness in the cell region 27 with a narrow pattern and the peripheral circuit region 8 with a wide pattern due to poor layer coverage. In the step of exposing the junction region by dry etching, the junction 25 of the cell region having a thin thickness of the spacer insulating layer 24 is damaged.
플라즈마 화학기상 증착법(PECVD : Plasma Enhanced Chemical Vapor deposition)에 의한 SiOxNy 막을 적용하는 경우에도 유전율은 6이하로 감소시킬 수 있으나, 패턴사이가 좁은 셀 영역에서는 얇게 증착 되어, 균일한 층덮힘성을 얻을 수 없으며, 또한 20:1 정도 이상의 층간 절연막과의 식각 선택비를 확보하기에도 부족하다. 이러한 부족한 식각 선택 비를 보충하고, 층간 절연막의 유전율을 낮추기 위한 방법으로, 실리콘 산화막과의 식각 선택비가 매우 뛰어난 폴리머 계열의 저유전율 절연막을 사용하는 방법이 있으나, 현재 알려진 폴리머 계열의 저유전율 막은 400℃ 이상의 고온에서 막 특성이 열화되고, 막 자체가 분해되어, 400℃ 이상의 열 공정을 진행해야 하는 메탈 전 공정에 적용하기에는 많은 문제점이 있다.Even when the SiOxNy film by plasma enhanced chemical vapor deposition (PECVD) is applied, the dielectric constant can be reduced to 6 or less, but it is thinly deposited in a narrow cell region between patterns, so that uniform layer coverage cannot be obtained. In addition, the etching selectivity with the interlayer insulating film of about 20: 1 or more is insufficient. As a method for supplementing the insufficient etching selectivity and lowering the dielectric constant of the interlayer insulating film, there is a method of using a polymer dielectric low dielectric constant film having an excellent etching selectivity with a silicon oxide film. There is a lot of problems to apply to all metal processes in which the film properties deteriorate at a high temperature of more than ℃, the film itself is decomposed, and a thermal process of 400 ℃ or more is to be performed.
따라서, 본 발명은 기생 커패시턴스를 유발할 수 있는 모든 절연막을 저유전율 값을 가지는 물질로 형성함과 동시에 게이트 측벽의 스페이서 및 층간 절연막의 충분한 건식식각 선택비를 확보하여 SAC 식각 공정시 게이트 전극이 손상되는 것을 방지하고 소자의 동작속도를 증가시켜 반도체 소자의 성능을 향상시킬 수 있는 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.Therefore, the present invention forms all insulating films capable of causing parasitic capacitance with a material having a low dielectric constant and at the same time ensures a sufficient dry etching selectivity of the spacers and the interlayer insulating films on the sidewalls of the gate to damage the gate electrodes during the SAC etching process. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can prevent the increase and increase the operating speed of the device to improve the performance of the semiconductor device.
도 1 및 도 2는 종래의 반도체 소자의 제조 방법을 설명하기 위하여 도시한 단면도.1 and 2 are cross-sectional views illustrating a conventional method for manufacturing a semiconductor device.
도 3a 내지 도 3e는 본 발명에 따른 반도체 소자의 제조 방법을 설명하기 위하여 순차적으로 도시한 단면도.3A to 3E are cross-sectional views sequentially shown to explain a method of manufacturing a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>
1, 21, 41 : 반도체 기판 2, 22,42 : 게이트1, 21, 41: semiconductor substrate 2, 22, 42: gate
3, 23,43 : 마스크 절연막 4, 24, 44 : 스페이서 절연막3, 23, 43: mask insulating film 4, 24, 44: spacer insulating film
5, 25, 45 : 접합부 6, 26, 46 : 층간 절연막5, 25, 45: junction 6, 26, 46: interlayer insulating film
27, 47 : 좁은 셀 영역 28, 48 : 넓은 셀 영역27, 47: narrow cell area 28, 48: wide cell area
49 : 실리콘 에피층 50 : 비트 라인49 silicon epi layer 50 bit line
11, 31, 51 : 소자 분리막11, 31, 51: device isolation film
본 발명에 따른 반도체 소자의 층간 절연막 형성 방법은 상부에 마스크 절연막을 갖는 게이트 및 접합부를 반도체 기판에 형성하는 단계, 게이트 및 마스크 절연막의 측벽에 SiOxNy 스페이서 절연막을 형성하는 단계, 접합부 상에 실리콘 에피층을 형성하는 단계, 전체구조 상에 다공성 산화막으로 층간 절연막을 형성하는 단계, 실리콘 에피층이 노출되도록 자기 정렬 콘택 식각공정을 실시하여 콘택홀을 형성하는 단계, 및 다공성 층간 절연막을 열처리하는 단계를 포함하여 이루어진다.A method of forming an interlayer insulating film of a semiconductor device according to the present invention includes forming a gate and a junction portion having a mask insulating film thereon in a semiconductor substrate, forming a SiOxNy spacer insulating film on sidewalls of the gate and mask insulating film, and forming a silicon epilayer on the junction portion. Forming a contact hole by forming an interlayer insulating film with a porous oxide film on the entire structure, performing a self-aligned contact etching process to expose the silicon epilayer, and heat-treating the porous interlayer insulating film. It is done by
상기의 단계에서, 게이트의 상부를 보호하는 마스크 절연막은 1 내지 760mTorr의 압력범위 및 350 내지 800℃의 온도에서 SiH4, TEOS, O2, O3및 N2O와 같은 반응가스를 이용하여 약 100Å의 두께로 형성한다. 또한, 마스크 절연막은 반응가스에 NH3가스를 첨가하여 질화막 또는 질화 산화막으로 형성할 수도 있다.In the above step, the mask insulating film to protect the upper portion of the gate is about to use a reaction gas such as SiH 4 , TEOS, O 2 , O 3 and N 2 O at a pressure range of 1 to 760 mTorr and a temperature of 350 to 800 ℃ It is formed to a thickness of 100Å. The mask insulating film may be formed of a nitride film or an oxide nitride film by adding NH 3 gas to the reaction gas.
자기 정렬 콘택 식각공정시 게이트의 측벽을 보호하는 SiOxNy 스페이서 절연막은 저압 화학 기상 증착(LPCVD)법으로 SiOxNy막을 증착한 후 전면 식각 공정으로 형성한다. SiOxNy 스페이서 절연막을 형성하는 첫 번째 방법은 450 내지 900℃의 온도 및 0.01 내지 760Torr의 저압범위에서 SiH4, SiH2Cl2, TEOS, O2, NH3및 N2O와 같은 반응가스를 이용하여 약 50Å의 두께로 형성한다. 두 번째 방법은 전체 구조상에 LPCVD법에 의하여 균일한 층덮힘성을 가진 SiOx막을 450 내지 900℃의 온도 및 0.01 내지 760Torr의 저압범위에서 SiH4, SiH2Cl2, TEOS, O2, O3및 N2O 가스와 같은 반응가스를 이용하여 약 50Å의 두께로 형성한다. 이후, NH3, N2, N2O 및 H2가스 중 적어도 어느 하나의 가스 분위기에서 약 400℃의 온도로 약 5초 동안 열처리를 실시하여 SiOxNy막을 형성한다. 세 번째 방법은, 전체 구조상에 LPCVD법에 의하여 균일한 층덮힘성을 가진 SiOx막을 450 내지 900℃의 온도 및 0.01 내지 760Torr의 저압범위에서 SiH4, SiH2Cl2, TEOS, O2, O3및 N2O 가스와 같은 반응가스를 이용하여 약 50Å의 두께로 형성한다. 이후, 약 100℃의 온도 및 NH3, N2, N2O 및 H2가스 중 적어도 어나 하나의 가스 분위기에서 약 100W의 전력으로 약 20초 동안 플라즈마 처리하고 도핑하여 SiOxNy막을 형성한다. 네 번째 방법은, 전체 구조상에 SiOxNy막을 500 내지 800℃의 온도 및 0.01 내지 100Torr의 저압범위에서 SiH4, SiH2Cl2, TEOS, O2, O3, N2O, NH3및 N2가스와 같은 반응가스를 이용하여 약 100W의 전력의PECVD법으로 약 50Å의 두께로 형성한다. 스페이서 절연막 형성하는 SiOxNy막은 층간 절연막과의 건식식각 비가 5:1 내지 10:1 범위이고, 4 내지 6 사이의 유전율 값을 갖는다.The SiOxNy spacer insulating layer which protects the sidewall of the gate during the self-aligned contact etching process is formed by depositing the SiOxNy layer by low pressure chemical vapor deposition (LPCVD) method and then forming the entire surface by etching. The first method of forming a SiOxNy spacer insulating film using a reaction gas such as SiH 4 , SiH 2 Cl 2 , TEOS, O 2 , NH 3 and N 2 O at a temperature of 450 to 900 ℃ and low pressure range of 0.01 to 760 Torr It is formed to a thickness of about 50Å. In the second method, a SiOx film having a uniform layer covering property by the LPCVD method over the entire structure was formed at SiH 4 , SiH 2 Cl 2 , TEOS, O 2 , O 3 and N at a temperature of 450 to 900 ° C. and a low pressure range of 0.01 to 760 Torr. Using a reaction gas such as 2 O gas to form a thickness of about 50 kPa. Thereafter, heat treatment is performed at a temperature of about 400 ° C. for about 5 seconds in a gas atmosphere of at least one of NH 3 , N 2 , N 2 O, and H 2 gases to form an SiO x N y film. In the third method, a SiOx film having a uniform layer covering property by the LPCVD method over the entire structure was formed at SiH 4 , SiH 2 Cl 2 , TEOS, O 2 , O 3 and at a temperature of 450 to 900 ° C. and a low pressure range of 0.01 to 760 Torr. Using a reaction gas such as N 2 O gas to form a thickness of about 50 kPa. Thereafter, plasma treatment and doping for about 20 seconds at a temperature of about 100 ° C. and at least one of NH 3 , N 2 , N 2 O, and H 2 gases at a power of about 100 W to form an SiO x N y film. Fourth method, the SiH 4 , SiH 2 Cl 2 , TEOS, O 2 , O 3 , N 2 O, NH 3 and N 2 gas in the SiOxNy film over the whole structure at a temperature of 500 to 800 ℃ and low pressure range of 0.01 to 100 Torr Using a reaction gas, such as a thickness of about 50 kW by a PECVD method of about 100W. The SiOxNy film forming the spacer insulating film has a dry etching ratio with the interlayer insulating film in the range of 5: 1 to 10: 1, and has a dielectric constant value between 4 and 6.
스페이서 절연막과 다공성 층간 절연막의 선택 식각비를 확보하기 위한 실리콘 에피층은 400 내지 900℃의 온도 범위 및 0.00001 내지 100Torr의 압력에서 SiH4, SiH2Cl2, HCl 및 H2가스와 같은 반응가스를 이용하여 약 500Å의 두께로 형성한다.The silicon epitaxial layer for securing the selective etch ratio of the spacer insulating film and the porous interlayer insulating film is a reaction gas such as SiH 4 , SiH 2 Cl 2 , HCl and H 2 gas at a temperature range of 400 to 900 ° C. and a pressure of 0.00001 to 100 Torr. It is formed to a thickness of about 500Å.
다공성 층간 절연막은 약 100rpm의 속도로 회전하는 반도체 기판에 TEOS, HC1, NH40H, IPA(Isopropyl Alcohol) 등이 함유된 용액을 스핀 도포(spin coating)하고, NH3및 H2O가 함유된 한 분위기에서 에이징(Aging) 처리한 후, 소수성 처리를 거친 다음 150 내지 350℃의 온도에서 약 30초 동안 베이킹(Baking)하고, 300 내지 500℃의 온도범위에서 불활성 가스 분위기로 약 1분 동안 열처리하여 약 1000Å의 두께로 형성한다.The porous interlayer insulating film is spin coated with a solution containing TEOS, HC1, NH 4 0H, IPA (Isopropyl Alcohol), etc., on a semiconductor substrate rotating at a speed of about 100 rpm, and contains NH 3 and H 2 O. Aging treatment in one atmosphere, followed by hydrophobic treatment, baking for about 30 seconds at a temperature of 150 to 350 ℃, heat treatment for about 1 minute in an inert gas atmosphere at a temperature range of 300 to 500 ℃ To form a thickness of about 1000Å.
층간 절연막에 흡착된 수분을 제거하기 위한 열처리는 200 내지 800℃의 온도 범위 및 0.001 내지 760Torr의 압력에서 실시하거나, 200 내지 600℃의 온도 범위 및 0.001 내지 100Torr의 압력에서 약 100W의 전력으로 플라즈마 처리를 한다.Heat treatment for removing moisture adsorbed to the interlayer insulating film is carried out at a temperature range of 200 to 800 ° C. and a pressure of 0.001 to 760 Torr, or plasma treatment at a power range of about 100 W at a temperature range of 200 to 600 ° C. and a pressure of 0.001 to 100 Torr. Do
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 더욱 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.
도 3a 내지 3e는 본 발명에 따른 반도체 소자의 제조 방법을 설명하기 위하여 순차적으로 도시한 단면도이다.3A to 3E are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device according to the present invention.
도 3a를 참조하면, 소자 분리막(51)이 형성된 반도체 기판(41) 상에 게이트(42) 및 접합부(45)로 이루어진 트랜지스터를 형성한다. 게이트(42)의 상부에는 마스크 절연막(43)이 형성되는데, 마스크 절연막(43)은 후속 자기 정렬 콘택 식각공정에서 게이트(42)가 식각되지 않도록 보호하기 위하여 형성되며, 0.01 내지 760Torr의 압력범위 및 350 내지 800℃의 온도에서 SiH4, TEOS, O2, O3및 N2O와 같은 반응가스를 이용하여 약 100Å의 두께로 형성한다. 마스크 절연막(42)은 NH3가스를 첨가하여 질화막 또는 질화 산화막으로 형성하기도 한다.Referring to FIG. 3A, a transistor including a gate 42 and a junction 45 is formed on a semiconductor substrate 41 on which an isolation layer 51 is formed. A mask insulating film 43 is formed on the gate 42. The mask insulating film 43 is formed to protect the gate 42 from being etched in a subsequent self-aligned contact etching process, and has a pressure range of 0.01 to 760 Torr. It is formed to a thickness of about 100 kPa using a reaction gas such as SiH 4 , TEOS, O 2 , O 3 and N 2 O at a temperature of 350 to 800 ℃. The mask insulating film 42 may be formed of a nitride film or an oxide nitride film by adding NH 3 gas.
도 3b를 참조하면, 게이트(42) 측벽에 스페이서(44)를 형성한다. 스페이서(44)는 SiOxNy막으로 형성하며 자기 정렬 콘택 식각시 게이트(42)의 측벽이 식각되는 것을 방지하는 SAC 식각 방지막(Self-Aligned Contact Etch Barrier)으로 사용된다.Referring to FIG. 3B, spacers 44 are formed on sidewalls of the gate 42. The spacer 44 is formed of a SiO x N y layer and is used as a self-aligned contact etch barrier that prevents sidewalls of the gate 42 from being etched during self-aligned contact etching.
이하에서는 스페이서(44)를 형성하는 방법을 설명한다.Hereinafter, a method of forming the spacer 44 will be described.
첫 번째로, 전체 구조상에 SiOxNy막을 450 내지 900℃의 온도 및 0.01 내지 760Torr의 저압범위에서 SiH4, SiH2Cl2, TEOS, O2, NH3및 N2O 가스와 같은 반응가스를 이용하여 저압 화학 기상 증착(LPCVD)법으로 약 50Å의 두께로 형성한다. LPCVD SiOxNy막은 층덮힘성이 우수하여 패턴 간격이 좁은 셀 영역(47)과 패턴 간격이 넓은 셀 영역(48)에서 균일한 두께로 형성된다. 형성된 SiOxNy막을 전면 건식식각 공정으로 게이트(42)의 측벽에만 남기고 나머지 부분을 제거하여 스페이서(44)를 형성한다.First, the SiOxNy film was formed on the overall structure by using reaction gases such as SiH 4 , SiH 2 Cl 2 , TEOS, O 2 , NH 3 and N 2 O gas at a temperature of 450 to 900 ° C. and a low pressure range of 0.01 to 760 Torr. It is formed to a thickness of about 50 kPa by low pressure chemical vapor deposition (LPCVD). The LPCVD SiOxNy film has excellent layer covering properties and is formed to have a uniform thickness in the cell region 47 having a narrow pattern interval and the cell region 48 having a large pattern interval. The spacers 44 are formed by leaving the formed SiO x N y film only on the sidewall of the gate 42 by the entire dry etching process.
두 번째로, 전체 구조상에 LPCVD법에 의하여 균일한 층덮힘성을 가진 SiOx막을 450 내지 900℃의 온도 및 0.01 내지 760Torr의 저압범위에서 SiH4, SiH2Cl2, TEOS, O2, O3및 N2O 가스와 같은 반응가스를 이용하여 약 50Å의 두께로 형성한다. 이후, NH3, N2, N2O 및 H2가스 중 적어도 어느 하나의 가스 분위기에서 약 400℃의 온도로 약 5초 동안 열처리를 실시하여 SiOxNy막을 형성한다. 형성된 SiOxNy막을 전면 건식식각 공정으로 게이트(42)의 측벽에만 남기고 나머지 부분을 제거하여 스페이서(44)를 형성한다.Secondly, a SiOx film having a uniform layer covering property on the entire structure by the LPCVD method was prepared at SiH 4 , SiH 2 Cl 2 , TEOS, O 2 , O 3 and N at a temperature of 450 to 900 ° C. and a low pressure range of 0.01 to 760 Torr. Using a reaction gas such as 2 O gas to form a thickness of about 50 kPa. Thereafter, heat treatment is performed at a temperature of about 400 ° C. for about 5 seconds in a gas atmosphere of at least one of NH 3 , N 2 , N 2 O, and H 2 gases to form an SiO x N y film. The spacers 44 are formed by leaving the formed SiO x N y film only on the sidewall of the gate 42 by the entire dry etching process and removing the remaining portions.
세 번째로, 전체 구조상에 LPCVD법에 의하여 균일한 층덮힘성을 가진 SiOx막을 450 내지 900℃의 온도 및 0.01 내지 760Torr의 저압범위에서 SiH4, SiH2Cl2, TEOS, O2, O3및 N2O 가스와 같은 반응가스를 이용하여 약 50Å의 두께로 형성한다. 이후, 약 100℃의 온도 및 NH3, N2, N2O 및 H2가스 중 적어도 어나 하나의 가스 분위기에서 약 100W의 전력으로 약 20초 동안 플라즈마 처리하고 도핑하여 SiOxNy막을 형성한다. 형성된 SiOxNy막을 전면 건식식각 공정으로 게이트(42)의 측벽에만 남기고 나머지 부분을 제거하여 스페이서(44)를 형성한다.Thirdly, a SiOx film having a uniform layer covering property on the entire structure by the LPCVD method was SiH 4 , SiH 2 Cl 2 , TEOS, O 2 , O 3 and N at a temperature of 450 to 900 ° C. and a low pressure range of 0.01 to 760 Torr. Using a reaction gas such as 2 O gas to form a thickness of about 50 kPa. Thereafter, plasma treatment and doping for about 20 seconds at a temperature of about 100 ° C. and at least one of NH 3 , N 2 , N 2 O, and H 2 gases at a power of about 100 W to form an SiO x N y film. The spacers 44 are formed by leaving the formed SiO x N y film only on the sidewall of the gate 42 by the entire dry etching process.
네 번째로, 전체 구조상에 SiOxNy막을 500 내지 800℃의 온도 및 0.01 내지 100Torr의 저압범위에서 SiH4, SiH2Cl2, TEOS, O2, O3, N2O, NH3및 N2가스와 같은반응가스를 이용하여 약 100W의 전력의 PECVD법으로 약 50Å의 두께로 형성한다. 이후 전면 건식식각 공정으로 게이트(42)의 측벽에만 SiOxNy막을 남기고 나머지 부분을 제거하여 스페이서(44)를 형성한다.Fourthly, the SiOxNy film was formed on the entire structure with SiH 4 , SiH 2 Cl 2 , TEOS, O 2 , O 3 , N 2 O, NH 3 and N 2 gas at a temperature of 500 to 800 ° C. and a low pressure range of 0.01 to 100 Torr. Using the same reaction gas to form a thickness of about 50 kW by PECVD method of about 100W. Afterwards, the spacer 44 is formed by leaving a SiOxNy film on only the sidewall of the gate 42 and removing the remaining portion by the front dry etching process.
SiOxNy막의 유전율은 기존의 질화막에 비하여 낮은 4 내지 6 사이의 유전율 값을 가지며 후속 공정에 형성될 층간 절연 산화막과의 건식식각 비가 5:1 내지 10:1 범위의 특성을 갖는다.The dielectric constant of the SiO x N y film has a lower dielectric constant value than that of the conventional nitride film and has a dry etching ratio with the interlayer insulating oxide film to be formed in a subsequent process in a range of 5: 1 to 10: 1.
도 3c를 참조하면, 스페이서(44)를 형성한 후 노출된 접합부(45) 상에 실리콘 에피층(49)을 형성한다. 실리콘 에피층(49)은 400 내지 900℃의 온도 범위 및 0.001mTorr 내지 100Torr의 저압범위에서 SiH4, SiH2Cl2, HCl 및 H2가스와 같은 반응가스를 이용하여 약 500Å의 두께로 형성한다. 실리콘 에피층(49)은 후속 SAC 식각 공정시 SAC 식각 깊이를 감소시켜 SAC 식각 공정시 스페이서(44)와 후속 공정에서 평탄화를 위해 형성하는 층간 절연막과의 충분한 건식식각 선택비를 확보해 주는 역할을 한다.Referring to FIG. 3C, after forming the spacers 44, a silicon epitaxial layer 49 is formed on the exposed junction 45. The silicon epi layer 49 is formed to a thickness of about 500 kPa using a reaction gas such as SiH 4 , SiH 2 Cl 2 , HCl and H 2 gas in a temperature range of 400 to 900 ° C. and a low pressure range of 0.001 mTorr to 100 Torr. . The silicon epitaxial layer 49 reduces the SAC etching depth during the subsequent SAC etching process, thereby ensuring sufficient dry etching selectivity between the spacer 44 during the SAC etching process and the interlayer insulating layer formed for planarization in the subsequent process. do.
도 3d를 참조하면, 전체구조 상에 유전율이 낮고 열안정성이 우수한 다공성 산화막으로 층간 절연막(46)을 형성하여 평탄화를 이룬 후 접합부(45)가 노출되는 콘택을 형성하기 위하여 자기 정렬 콘택 식각공정을 실시하고 열처리를 한다.Referring to FIG. 3D, a self-aligned contact etching process is performed to form a contact through which the junction 45 is exposed after the planarization of the interlayer insulating film 46 by using a porous oxide film having a low dielectric constant and excellent thermal stability over the entire structure. And heat treatment.
층간 절연막(46)은 다음과 같은 방법으로 형성된다. 먼저, 분당 약 100회의 속도로 회전하는 반도체 기판에 TEOS, HC1, NH40H, IPA(Isopropyl Alcohol) 등이 함유된 용액을 스핀 도포(spin coating)하고, NH3및 H2O가 함유된 분위기에서에이징(Aging) 처리한다. 이후 소수성 처리를 거친 다음 150 내지 350℃의 온도에서 약 30초 동안 베이킹(Baking)하고, 300 내지 500℃의 온도범위에서 불활성(Inert) 가스 분위기로 약 1분 동안 열처리하여 약 1000Å의 두께의 층간 절연막(46)을 형성한다.The interlayer insulating film 46 is formed in the following manner. First, spin coating a solution containing TEOS, HC1, NH 4 0H, IPA (Isopropyl Alcohol), or the like onto a semiconductor substrate rotating at a speed of about 100 times per minute, and then atmosphere containing NH 3 and H 2 O. Aging After the hydrophobic treatment, and then baked for about 30 seconds at a temperature of 150 to 350 ℃, heat treatment for about 1 minute in an inert gas atmosphere at a temperature range of 300 to 500 ℃ by an interlayer having a thickness of about 1000Å An insulating film 46 is formed.
열처리 공정은 콘택을 형성하는 공정에서 층간 절연막(46)으로 흡수된 수분을 제거하기 위하여 실시하는데, 첫 번째 방법으로는 200 내지 800℃의 온도 범위 및 0.001 내지 760Torr의 압력에서 실시하는 방법과, 두 번째 방법으로는 200 내지 600℃의 온도 범위 및 0.001 내지 100Torr의 압력에서 약 100W의 전력으로 플라즈마 처리를 실시하는 방법이 있다.The heat treatment process is performed to remove moisture absorbed by the interlayer insulating film 46 in the process of forming a contact. The first method is a method performed at a temperature range of 200 to 800 ° C. and a pressure of 0.001 to 760 Torr. As a first method, there is a method of performing a plasma treatment with a power of about 100 W in a temperature range of 200 to 600 ° C. and a pressure of 0.001 to 100 Torr.
도 3e를 참조하면, 콘택을 포함한 층간 절연막(46) 상에 증착공정 및 패터닝 공정으로 비트 라인(50)을 형성한다. 비트 라인(50)은 W, Cu, Au, Ag, Ru, RuOx, Ti, TiN, Ta, TaN, TiSiN 및 WNx 중 적어도 어느 하나를 이용하여 형성한다.Referring to FIG. 3E, the bit line 50 is formed on the interlayer insulating layer 46 including the contact by a deposition process and a patterning process. The bit line 50 is formed using at least one of W, Cu, Au, Ag, Ru, RuOx, Ti, TiN, Ta, TaN, TiSiN, and WNx.
상술한 바와 같이, 본 발명은 층덮힘성을 고려하면서 유전율이 낮은 절연막을 이용하고, 실리콘 에피층으로 스페이서 절연막과 층간 절연막의 식각 선택비를 보상하므로써 소자의 기생 커패시터와 크로스 토크를 감소시키고 소자의 전기적 특성 및 동작속도를 향상시키는 효과가 있다.As described above, the present invention uses an insulating film having a low dielectric constant while considering layer covering properties, and reduces parasitic capacitors and crosstalk of the device by compensating the etch selectivity of the spacer insulating film and the interlayer insulating film with the silicon epilayer, and reduces the electrical It has the effect of improving the characteristics and operation speed.
Claims (15)
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20030040058A (en) * | 2001-11-15 | 2003-05-22 | 미쓰비시덴키 가부시키가이샤 | Semiconductor device and method of manufacturing same |
| KR100510915B1 (en) * | 2003-07-18 | 2005-08-26 | 매그나칩 반도체 유한회사 | Method of forming a dielectric layer in a semiconductor device |
| KR100724217B1 (en) * | 2005-12-28 | 2007-05-31 | 동부일렉트로닉스 주식회사 | Method for forming sin layer on a copper line process |
| KR100772680B1 (en) * | 2006-11-13 | 2007-11-02 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
| KR100780632B1 (en) * | 2006-02-28 | 2007-11-29 | 주식회사 하이닉스반도체 | Method for contact plug of semiconductor device |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20030040058A (en) * | 2001-11-15 | 2003-05-22 | 미쓰비시덴키 가부시키가이샤 | Semiconductor device and method of manufacturing same |
| KR100510915B1 (en) * | 2003-07-18 | 2005-08-26 | 매그나칩 반도체 유한회사 | Method of forming a dielectric layer in a semiconductor device |
| US6946381B2 (en) | 2003-07-18 | 2005-09-20 | Hynix Semiconductor Inc. | Method of forming insulating film in semiconductor device |
| KR100724217B1 (en) * | 2005-12-28 | 2007-05-31 | 동부일렉트로닉스 주식회사 | Method for forming sin layer on a copper line process |
| KR100780632B1 (en) * | 2006-02-28 | 2007-11-29 | 주식회사 하이닉스반도체 | Method for contact plug of semiconductor device |
| KR100772680B1 (en) * | 2006-11-13 | 2007-11-02 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
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