KR100341847B1 - Method of forming a bit line in a semiconductor device - Google Patents
Method of forming a bit line in a semiconductor device Download PDFInfo
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- KR100341847B1 KR100341847B1 KR1019990049507A KR19990049507A KR100341847B1 KR 100341847 B1 KR100341847 B1 KR 100341847B1 KR 1019990049507 A KR1019990049507 A KR 1019990049507A KR 19990049507 A KR19990049507 A KR 19990049507A KR 100341847 B1 KR100341847 B1 KR 100341847B1
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- Prior art keywords
- bit line
- tungsten
- insulating film
- film
- nitride
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- 238000000034 method Methods 0.000 title claims abstract description 48
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 239000010937 tungsten Substances 0.000 claims abstract description 51
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 51
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 41
- -1 Tungsten nitride Chemical class 0.000 claims abstract description 15
- 239000012298 atmosphere Substances 0.000 claims abstract description 8
- 238000010438 heat treatment Methods 0.000 claims abstract description 7
- 239000012299 nitrogen atmosphere Substances 0.000 claims abstract description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 6
- 238000009832 plasma treatment Methods 0.000 claims abstract description 6
- 238000005121 nitriding Methods 0.000 claims abstract description 5
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 claims description 21
- 238000000151 deposition Methods 0.000 claims description 14
- 239000011229 interlayer Substances 0.000 claims description 13
- 230000004888 barrier function Effects 0.000 claims description 10
- 238000009792 diffusion process Methods 0.000 claims description 10
- 239000003292 glue Substances 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 125000006850 spacer group Chemical group 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 5
- 229910001873 dinitrogen Inorganic materials 0.000 claims description 4
- BSYNRYMUTXBXSQ-UHFFFAOYSA-N Aspirin Chemical compound CC(=O)OC1=CC=CC=C1C(O)=O BSYNRYMUTXBXSQ-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 239000012159 carrier gas Substances 0.000 claims 1
- 230000003647 oxidation Effects 0.000 abstract description 7
- 238000007254 oxidation reaction Methods 0.000 abstract description 7
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 239000003990 capacitor Substances 0.000 abstract 1
- 229910052757 nitrogen Inorganic materials 0.000 abstract 1
- 238000000206 photolithography Methods 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 229910004205 SiNX Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000003064 anti-oxidating effect Effects 0.000 description 1
- 239000003963 antioxidant agent Substances 0.000 description 1
- 230000003078 antioxidant effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
Abstract
본 발명은 반도체 소자의 제조 공정에서 비트라인으로 텅스텐을 적용할 때, 후속 공정인 캐패시터 형성시의 열 공정등에 의해 발생하는 텅스텐 비트라인의 산화 현상을 억제하기 위하여, 텅스텐 비트라인을 형성한 후 질소 분위기에서의 열처리 혹은 질소 분위기에서의 플라즈마 처리와 같은 질화 처리를 통해 텅스텐 비트라인 측벽을 변화시켜 텅스텐 질화막을 형성하므로, 후속 열공정에 의한 텅스텐 비트라인의 산화 및 리프팅 현상을 억제할 수 있어 소자 제품의 수율 및 신뢰성을 향상시킬 수 있는 반도체 소자의 비트라인 형성 방법에 관하여 기술된다.In the present invention, when the tungsten is applied to the bit line in the semiconductor device manufacturing process, nitrogen is formed after the tungsten bit line is formed in order to suppress oxidation of the tungsten bit line caused by the thermal process during the formation of the capacitor, which is a subsequent process. Tungsten nitride layer is formed by changing the tungsten bit line sidewall through nitriding treatment such as heat treatment in atmosphere or plasma treatment in nitrogen atmosphere, thereby suppressing oxidation and lifting phenomenon of tungsten bit line by subsequent thermal process. A method of forming a bit line of a semiconductor device capable of improving the yield and the reliability thereof is described.
Description
본 발명은 반도체 소자의 비트라인 형성 방법에 관한 것으로, 특히 반도체 소자의 제조 공정에서 비트라인으로 텅스텐을 적용할 때, 후속 열공정에 의한 텅스텐 비트라인의 산화 및 리프팅 현상을 억제하여 소자 제품의 수율 및 신뢰성을 향상시킬 수 있는 반도체 소자의 비트라인 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a bit line of a semiconductor device. In particular, when tungsten is applied to a bit line in a semiconductor device manufacturing process, the yield and yield of device products are suppressed by suppressing oxidation and lifting of the tungsten bit line by subsequent thermal processes. And a bit line forming method of a semiconductor device capable of improving reliability.
일반적으로, 반도체 소자가 고집적화 되면서 단위 셀이 차지하는 면적 또한 줄어들고 있는 추세이며, 이에 따라 비트라인의 폭이 좁아져 전기적 저항이 증가하는 문제점이 발생된다. 이를 해결하기 위하여 비트라인 물질로 저항이 비교적 작은 텅스텐을 사용하고 있는 추세이다.In general, as the semiconductor devices are highly integrated, the area occupied by the unit cells is also decreasing. Accordingly, the width of the bit lines is narrowed, thereby increasing the electrical resistance. In order to solve this problem, tungsten has a relatively low resistance as a bit line material.
종래 반도체 소자의 비트라인 형성 방법을 도 1a 내지 도 1c를 참조하여 설명하면 다음과 같다.A method of forming a bit line of a conventional semiconductor device will now be described with reference to FIGS. 1A to 1C.
도 1a를 참조하면, 반도체 소자를 구성하기 위한 여러 요소가 구비된 반도체 기판(11) 상에 층간 절연막(12)을 형성한다. 도시하지는 않았지만, 통상의 공정으로 층간 절연막(12)에 비트라인용 콘택홀을 형성하고, 이 콘택홀 내에 비트라인 콘택 플러그를 형성한다. 이러한 층간 절연막(12) 상에 글루막(glue layer; 13), 확산 방지막(14), 텅스텐막(15), 제 1 절연막(16) 및 제 2 절연막(17)을 순차적으로 형성한다.Referring to FIG. 1A, an interlayer insulating layer 12 is formed on a semiconductor substrate 11 having various elements for forming a semiconductor device. Although not shown, a bit line contact hole is formed in the interlayer insulating film 12 by a normal process, and a bit line contact plug is formed in this contact hole. On this interlayer insulating film 12, a glue layer 13, a diffusion barrier 14, a tungsten film 15, a first insulating film 16 and a second insulating film 17 are sequentially formed.
상기에서, 글루층(13)은 타이타늄(Ti)을 증착하여 형성하며, 확산 방지막(14)은 타이타늄 나이트라이드(TiN)를 증착하여 형성한다. 제 1 절연막(16)은 실리콘 옥시 나이트라이드(SiON)를 증착하여 형성하며, 제 2 절연막(17)은 실리콘 나이트라이드(SiNx)를 증착하여 형성한다. 제 1 및 제 2 절연막(16 및 17)은 후속 포토리소그라피 공정 및 식각 공정을 위해 형성한다.In the above, the glue layer 13 is formed by depositing titanium (Ti), and the diffusion barrier 14 is formed by depositing titanium nitride (TiN). The first insulating layer 16 is formed by depositing silicon oxynitride (SiON), and the second insulating layer 17 is formed by depositing silicon nitride (SiNx). The first and second insulating films 16 and 17 are formed for subsequent photolithography and etching processes.
도 1b를 참조하면, 포토리소그라피 공정 및 식각 공정을 통해 제 2 절연막(17), 제 1 절연막(16), 텅스텐막(15), 확산 방지막(14) 및 글루막(13)을 순차적으로 식각하고, 이로 인하여 텅스텐 비트라인(150)이 형성된다.Referring to FIG. 1B, the second insulating film 17, the first insulating film 16, the tungsten film 15, the diffusion barrier 14, and the glue film 13 are sequentially etched through a photolithography process and an etching process. As a result, the tungsten bit line 150 is formed.
도 1c를 참조하면, 텅스텐 비트라인(150)을 포함한 전체 상부면에 절연막을 증착한 후, 전면 식각공정을 통해 스페이서 절연막(18)을 형성하여 텅스텐 비트라인(150) 형성 공정을 완료한다.Referring to FIG. 1C, after the insulating film is deposited on the entire upper surface including the tungsten bit line 150, the spacer insulating film 18 is formed through the entire surface etching process to complete the process of forming the tungsten bit line 150.
상술한 종래 방법으로 텅스텐 비트라인 구조를 형성한 후에 후속 열공정이 산소 분위기에서 진행될 경우, 텅스텐의 취약한 산화 특성으로 인하여 텅스텐 비트라인(15)의 산화와 리프팅 현상이 일어나 비트라인의 저항 증가 및 후속 공정 진행을 어렵게 한다. 이로 인하여 차세대 반도체 소자 개발을 불가능하게 한다.After the formation of the tungsten bit line structure by the conventional method described above, if the subsequent thermal process is performed in an oxygen atmosphere, oxidation and lifting of the tungsten bit line 15 may occur due to the weak oxidation property of the tungsten, thereby increasing the resistance of the bit line and subsequent processes. Make progress difficult This makes it impossible to develop next-generation semiconductor devices.
따라서, 본 발명은 반도체 소자의 제조 공정에서 비트라인으로 텅스텐을 적용할 때, 후속 열공정에 의한 텅스텐 비트라인의 산화 및 리프팅 현상을 억제하여 소자 제품의 수율 및 신뢰성을 향상시킬 수 있는 반도체 소자의 비트라인 형성 방법을 제공함에 그 목적이 있다.Accordingly, the present invention is to provide a semiconductor device that can improve the yield and reliability of the device product by suppressing the oxidation and lifting of the tungsten bit line by the subsequent thermal process when applying tungsten to the bit line in the semiconductor device manufacturing process It is an object of the present invention to provide a bit line forming method.
이러한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 비트라인 형성방법은 반도체 소자를 구성하기 위한 여러 요소가 구비되고, 층간 절연막이 형성된 반도체 기판이 제공되는 단계; 상기 층간 절연막 상에 글루막, 확산 방지막, 텅스텐막, 제 1 절연막 및 제 2 절연막을 순차적으로 형성한 후, 상기 막들을 상기 층간 절연막이 노출되도록 패터닝하여 텅스텐 비트라인을 형성하는 단계; 질화 처리를 통해 상기 텅스텐 비트라인의 노출된 측벽을 변화시켜 텅스텐 질화막을 형성하는 단계; 및 상기 텅스텐 비트라인의 측벽에 스페이서 절연막을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a bit line of a semiconductor device, the method including: providing a semiconductor substrate having various elements for constituting the semiconductor device, and having an interlayer insulating film formed thereon; Sequentially forming a glue film, a diffusion barrier film, a tungsten film, a first insulating film, and a second insulating film on the interlayer insulating film, and patterning the films to expose the interlayer insulating film to form a tungsten bit line; Changing the exposed sidewalls of the tungsten bitline through nitriding to form a tungsten nitride film; And forming a spacer insulating film on sidewalls of the tungsten bit line.
도 1a 내지 도 1c는 종래 반도체 소자의 비트라인 형성 방법을 설명하기 위한 소자의 단면도.1A to 1C are cross-sectional views of a device for explaining a method of forming a bit line of a conventional semiconductor device.
도 2a 내지 도 2d는 본 발명에 따른 반도체 소자의 비트라인 형성 방법을 설명하기 위한 소자의 단면도.2A to 2D are cross-sectional views of a device for explaining a method of forming a bit line of a semiconductor device according to the present invention.
〈도면의 주요 부분에 대한 부호 설명〉<Description of Signs of Major Parts of Drawings>
11, 21: 반도체 기판 12, 22: 층간 절연막11, 21: semiconductor substrate 12, 22: interlayer insulating film
13, 23: 글루막 14, 24: 확산 방지막13, 23: glue film 14, 24: diffusion barrier film
15, 25: 텅스텐막 16, 26: 제 1 절연막15, 25: tungsten film 16, 26: first insulating film
17, 27: 제 2 절연막 18, 28: 스페이서 절연막17, 27: second insulating film 18, 28: spacer insulating film
150, 250: 텅스텐 비트라인 200: 텅스텐 질화막150, 250: tungsten bit line 200: tungsten nitride film
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명에 따른 반도체 소자의 비트라인 형성 방법을 설명하기 위한 소자의 단면도이다.2A to 2D are cross-sectional views of devices for describing a method of forming a bit line of a semiconductor device according to the present invention.
도 2a를 참조하면, 반도체 소자를 구성하기 위한 여러 요소가 구비된 반도체 기판(21) 상에 층간 절연막(22)을 형성한다. 도시하지는 않았지만, 통상의 공정으로 층간 절연막(22)에 비트라인용 콘택홀을 형성하고, 이 콘택홀 내에 비트라인 콘택 플러그를 형성한다. 이러한 층간 절연막(22) 상에 글루막(glue layer; 23), 확산 방지막(24), 텅스텐막(25), 제 1 절연막(26) 및 제 2 절연막(27)을 순차적으로 형성한다.Referring to FIG. 2A, an interlayer insulating layer 22 is formed on a semiconductor substrate 21 having various elements for forming a semiconductor device. Although not shown, a bit line contact hole is formed in the interlayer insulating film 22 by a normal process, and a bit line contact plug is formed in this contact hole. A glue layer 23, a diffusion barrier 24, a tungsten film 25, a first insulating film 26, and a second insulating film 27 are sequentially formed on the interlayer insulating film 22.
상기에서, 글루층(23)은 타이타늄(Ti)을 증착하여 형성하며, 확산 방지막(24)은 타이타늄 나이트라이드(TiN)를 증착하여 형성한다. 제 1 절연막(26)은 실리콘 옥시 나이트라이드(SiON)를 증착하여 형성하며, 제 2 절연막(27)은 실리콘 나이트라이드(SiNx)를 증착하여 형성한다. 제 1 및 제 2 절연막(26 및 27)은 후속 포토리소그라피 공정 및 식각 공정을 위해 형성한다. 제 2 절연막(27)은 실리콘 옥시 나이트라이드로 형성할 수 있다.In the above, the glue layer 23 is formed by depositing titanium (Ti), the diffusion barrier layer 24 is formed by depositing titanium nitride (TiN). The first insulating layer 26 is formed by depositing silicon oxynitride (SiON), and the second insulating layer 27 is formed by depositing silicon nitride (SiNx). The first and second insulating films 26 and 27 are formed for subsequent photolithography and etching processes. The second insulating layer 27 may be formed of silicon oxy nitride.
도 2b를 참조하면, 포토리소그라피 공정 및 식각 공정을 통해 제 2 절연막(27), 제 1 절연막(26), 텅스텐막(25), 확산 방지막(24) 및 글루막(23)을 순차적으로 식각하고, 이로 인하여 텅스텐 비트라인(250)이 형성된다.Referring to FIG. 2B, the second insulating layer 27, the first insulating layer 26, the tungsten layer 25, the diffusion barrier layer 24, and the glue layer 23 are sequentially etched through a photolithography process and an etching process. As a result, the tungsten bit line 250 is formed.
도 2c를 참조하면, 질화 처리를 통해 텅스텐 비트라인(250)의 노출된 측벽을 변화시켜 텅스텐 질화막(WNx; 200)을 형성한다.Referring to FIG. 2C, the exposed sidewall of the tungsten bit line 250 is changed through nitriding to form a tungsten nitride layer (WNx) 200.
상기에서, 텅스텐 질화막(200)은 질소 분위기에서의 열처리 혹은 질소 분위기에서의 플라즈마 처리와 같은 질화 처리를 통해 10 내지 100Å 두께로 형성되며, WNx의 조성은 "x"가 0.1 내지 0.5 사이이다.In the above, the tungsten nitride film 200 is formed to a thickness of 10 to 100 microseconds through a nitriding treatment such as heat treatment in a nitrogen atmosphere or plasma treatment in a nitrogen atmosphere, and the composition of WNx is "x" of 0.1 to 0.5.
열처리 공정은 반응로(Furnace) 타입 또는 급속 열(Rapid Thermal)공정 타입을 이용하여 N2, NH3및 NF3중 적어도 어느 하나의 질소 가스 분위기에서 500 내지 1000℃의 온도로 30초 내지 120분간 실시한다.The heat treatment process is performed for 30 seconds to 120 minutes at a temperature of 500 to 1000 ° C. in a nitrogen gas atmosphere of at least one of N 2 , NH 3 and NF 3 using a furnace type or rapid thermal process type. Conduct.
플라즈마 처리 공정은 직류(DC), 라디오 주파수(Radio Frequency), 전자자기공명(Electron Cyclotron Resonance), 헬리콘(Helicon) 플라즈마 중 어느 하나의 플라즈마를 사용하여 Ar, He 및 H2중 어느 하나를 운반 가스와, N2, NH3및 NF3중 적어도 어느 하나의 질소 가스 분위기에서 100 내지 500℃의 온도로 30초 내지 120분간 실시한다.The plasma treatment process uses any one of a direct current (DC), a radio frequency (Radio Frequency), an electromagnetic resonance (Electron Cyclotron Resonance), a Helicon (Helicon) plasma to transport any one of Ar, He and H 2 carried out with gas, N 2, NH 3, and NF 3 of at least one of a nitrogen gas atmosphere at a temperature of 100 to 500 ℃ 30 seconds to 120 minutes.
상기와 같이 형성된 텅스텐 질화막(200)은 비저항이 100 내지 300μΩ㎝로 비교적 낮아 텅스텐 비트라인(250)의 전기적 특성을 열화시키지 않으면서, 산화 저항 특성이 양호하여 후속 열공정이 산소 분위기에서 진행될 경우, 산소와 텅스텐의 반응을 억제하는 산화 방지막 역할을 한다.The tungsten nitride film 200 formed as described above has a relatively low resistivity of 100 to 300 μΩcm and does not deteriorate the electrical properties of the tungsten bit line 250, and the oxidation resistance is good so that the subsequent thermal process proceeds in an oxygen atmosphere. It acts as an antioxidant to suppress the reaction of and tungsten.
도 2d를 참조하면, 텅스텐 비트라인(250)을 포함한 전체 상부면에 절연막을 증착한 후, 전면 식각공정을 통해 스페이서 절연막(28)을 형성하여 텅스텐 비트라인(250) 형성 공정을 완료한다.Referring to FIG. 2D, after the insulating film is deposited on the entire upper surface including the tungsten bit line 250, the spacer insulating film 28 is formed through the entire surface etching process to complete the process of forming the tungsten bit line 250.
상기에서, 스페이서 절연막(28)은 실리콘 나이트라이드 혹은 실리콘 옥시 나이트라이드를 증착하여 형성된다.In the above, the spacer insulating film 28 is formed by depositing silicon nitride or silicon oxy nitride.
상술한 바와 같이, 본 발명은 텅스텐 비트라인 형성 후 질소 분위기 열처리 또는 질소 분위기 플라즈마 처리를 실시하여 노출된 텅스텐 비트라인 측벽을 텅스텐 질화막으로 변화시키므로, 후속 산소 분위기의 열처리시 발생되는 텅스텐 비트라인의 산화 및 리프팅 현상을 방지 할 수 있다. 또한, 텅스텐 질화막은 비저항이 낮아 텅스텐 비트라인의 전기적 특성을 열화 시키지 않으면서 텅스텐 비트라인의 산화 방지막 역할을 한다. 따라서, 본 발명은 비트라인의 전기적 특성을 향상시킬 수 있을 뿐만 아니라 소자 제품의 수율 및 신뢰성을 향상시킬 수 있고, 차세대 반도체 소자의 개발에 기여할 수 있다.As described above, the present invention changes the exposed tungsten bit line sidewalls to a tungsten nitride film by performing nitrogen atmosphere heat treatment or nitrogen atmosphere plasma treatment after the formation of the tungsten bit line, thereby oxidizing the tungsten bit line generated during the subsequent heat treatment of the oxygen atmosphere. And can prevent the lifting phenomenon. In addition, the tungsten nitride film has a low specific resistance and serves as an anti-oxidation film of the tungsten bit line without deteriorating the electrical characteristics of the tungsten bit line. Therefore, the present invention can not only improve the electrical characteristics of the bit line, but also improve the yield and reliability of device products, and contribute to the development of next-generation semiconductor devices.
Claims (7)
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