KR100356477B1 - Method of forming a capacitor in a semiconductor device - Google Patents
Method of forming a capacitor in a semiconductor device Download PDFInfo
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- KR100356477B1 KR100356477B1 KR1019990025758A KR19990025758A KR100356477B1 KR 100356477 B1 KR100356477 B1 KR 100356477B1 KR 1019990025758 A KR1019990025758 A KR 1019990025758A KR 19990025758 A KR19990025758 A KR 19990025758A KR 100356477 B1 KR100356477 B1 KR 100356477B1
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- Prior art keywords
- film
- forming
- capacitor
- polysilicon layer
- semiconductor device
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- 238000000034 method Methods 0.000 title claims abstract description 42
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 239000003990 capacitor Substances 0.000 title claims abstract description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 19
- 229920005591 polysilicon Polymers 0.000 claims abstract description 19
- 238000003860 storage Methods 0.000 claims abstract description 15
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 6
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 4
- 238000005121 nitriding Methods 0.000 claims abstract description 4
- 239000000758 substrate Substances 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 2
- 238000011065 in-situ storage Methods 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 239000007789 gas Substances 0.000 abstract description 8
- 229910052760 oxygen Inorganic materials 0.000 abstract description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 4
- 239000001301 oxygen Substances 0.000 abstract description 4
- 238000006243 chemical reaction Methods 0.000 abstract description 3
- 150000004767 nitrides Chemical class 0.000 abstract description 3
- 238000000151 deposition Methods 0.000 abstract description 2
- 229910002651 NO3 Inorganic materials 0.000 abstract 1
- NHNBFGGVMKEFGY-UHFFFAOYSA-N Nitrate Chemical compound [O-][N+]([O-])=O NHNBFGGVMKEFGY-UHFFFAOYSA-N 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 14
- 239000011229 interlayer Substances 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H01L28/60—
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Formation Of Insulating Films (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 반도체 소자의 캐패시터 형성방법에 관한 것으로 특히, Ta2O5유전체를 사용하는 반도체 소자의 캐패시터 형성방법이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a capacitor of a semiconductor device, and more particularly, to a method of forming a capacitor of a semiconductor device using a Ta 2 O 5 dielectric.
종래 하부 전하저장전극인 폴리실리콘층과 Ta2O5유전체막과의 실리콘 산화막 형성을 억제하기 위하여 고온에서 급속 열 질화공정을 실시하였다. 그러나, 고온 열공정은 하부층의 열 버젯(Thermal budget) 문제가 발생하고, Ta2O5유전체막 증착 후 후속 열공에 의해 상기 질화된 폴리실리콘 표면이 Ta2O5유전체막의 산소와 반응하여 누설 전류를 발생시키는 문제가 있다.In order to suppress the formation of a silicon oxide film between a polysilicon layer, which is a lower charge storage electrode, and a Ta 2 O 5 dielectric film, a rapid thermal nitriding process was performed at a high temperature. However, the hot tear Chung thermal Budget (Thermal budget) problem of the underlying layer occurs and, Ta 2 O 5 dielectric which the nitrided polysilicon surface by subsequent tear film after depositing Ta 2 O 5 dielectric layer react with oxygen by the leakage current There is a problem that occurs.
상기한 문제점을 해소하도록 본 발명은 하부 전하저장전극으로 사용되는 폴리실리콘층을 NH3또는 N2가스를 이용한 저온 플라즈마 공정으로 질화 시킨 후 질화막이 형성된 상기 폴리실리콘층을 O2또는 N2O 가스 분위기에서 플라즈마 공정을 재 실시하므로 상기 폴리실리콘층에 SiON막을 형성한다. 상기 SiON막은 Ta2O5유전 체막의 산소반응에 의한 누설 전류를 감소시켜 소자의 전기적 특성을 향상 시킨다.In order to solve the above problems, the present invention is to nitrate the polysilicon layer used as the lower charge storage electrode in a low-temperature plasma process using NH 3 or N 2 gas and then the polysilicon layer formed with a nitride film is O 2 or N 2 O gas Since the plasma process is performed again in the atmosphere, a SiON film is formed on the polysilicon layer. The SiON film improves the electrical characteristics of the device by reducing the leakage current by the oxygen reaction of the Ta 2 O 5 dielectric film.
Description
본 발명은 반도체 소자의 캐패시터 형성방법에 관한 것으로 특히, Ta2O5유전체를 사용하는 반도체 소자의 캐패시터 형성방법이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a capacitor of a semiconductor device, and more particularly, to a method of forming a capacitor of a semiconductor device using a Ta 2 O 5 dielectric.
종래 Ta2O5유전체를 사용하는 반도체 소자의 캐패시터 형성방법을 설명하면 다음과 같다.A method of forming a capacitor of a semiconductor device using a conventional Ta 2 O 5 dielectric is as follows.
일반적으로 접합부가 형성된 반도체 기판상에 층간 산화막을 형성한 후 접합부가 노출되도록 콘택홀을 형성한다. 그후 콘택홀을 매립하는 하부전하저장전극용 폴리실리콘층 형성한 후 패터닝하여 하부 전하저장전극을 형성한다.Generally, after forming an interlayer oxide film on a semiconductor substrate on which a junction is formed, a contact hole is formed to expose the junction. Thereafter, a polysilicon layer for lower charge storage electrodes filling contact holes is formed and then patterned to form lower charge storage electrodes.
그후, 전체 상부면에 Ta2O5유전체막 및 상부 전하저장전극을 형성하여 캐패시터를 형성한다.After that, a Ta 2 O 5 dielectric film and an upper charge storage electrode are formed on the entire upper surface to form a capacitor.
이때, Ta2O5유전체막 형성시 하부 전하저장전극용 폴리실리콘층과 반응하여 SiO2막 형성을 억제하기 위하여 800 ℃ 이상의 NH3가스를 이용한 급속 열 질화 공정을 실시하여 상기 폴리실리콘층을 질화 시킨다.In this case, in order to suppress the formation of SiO 2 film by reacting with the polysilicon layer for the lower charge storage electrode when forming the Ta 2 O 5 dielectric film, a rapid thermal nitriding process using NH 3 gas of 800 ° C. or more is performed to nitride the polysilicon layer. Let's do it.
그러나, 800℃ 이상의 고온 공정에서 하부 층의 열 버젯(Thermal Budget) 문제가 발생되고, Ta2O5유전체막 증착 후 후속 열공에 의해 상기 질화된 폴리실리콘 표면이 Ta2O5유전체막의 산소와 반응하여 누설 전류가 발생되는 등의 문제가 있다.However, the thermal budget problem of the lower layer occurs at a high temperature process of 800 ° C. or higher, and the nitrided polysilicon surface reacts with oxygen of the Ta 2 O 5 dielectric film by subsequent thermal holes after Ta 2 O 5 dielectric film deposition. There is such a problem that leakage current is generated.
따라서, 본 발명은 하부 전하저장전극으로 사용되는 폴리실리콘층을 1 차 및 2 차에 걸친 플라즈마 공정으로 반도체 소자의 하부층의 열 버젯 문제와, 유전체막과의 반응에 의한 누설 전류를 감소 시킬 수 있는 반도체 소자의 캐패시터 형성방법을 제공하는데 그 목적이 있다.Accordingly, the present invention can reduce the thermal budget problem of the lower layer of the semiconductor device and the leakage current due to the reaction with the dielectric film by using the polysilicon layer used as the lower charge storage electrode in the first and second plasma processes. It is an object of the present invention to provide a method for forming a capacitor of a semiconductor device.
상기한 목적을 달성하기 위한 본 발명은 반도체 소자를 형성하기 위한 여러 요소가 형성된 기판상에 하부 전하저장전극인 폴리실리콘층을 형성하는 단계와, 1 차 플라즈마 공정으로 상기 폴리실리콘층을 질화 시킨 후 2차 플라즈마 공정으로 상기 질화된 폴리실리콘층을 산화 시키는 공정을 순차적으로 실시하는 단계와, 전체 상부면에 Ta2O5유전체막을 형성한 후 열공정을 실시하는 단계와, 전체 상부면에 상부 전하저장전극을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.The present invention for achieving the above object is to form a polysilicon layer, which is a lower charge storage electrode on a substrate on which a number of elements for forming a semiconductor device, and after nitriding the polysilicon layer by a first plasma process Sequentially performing the step of oxidizing the nitrided polysilicon layer by a secondary plasma process, forming a Ta 2 O 5 dielectric film on an entire upper surface, and then performing a thermal process, and an upper charge on the entire upper surface And forming a storage electrode.
도 1a 내지 도 1c는 본 발명에 따른 반도체 소자의 캐패시터 형성방법을 설명하기 위한 소자의 단면도.1A to 1C are cross-sectional views of a device for explaining a method of forming a capacitor of a semiconductor device according to the present invention.
〈도면의 주요 부분에 대한 부호 설명〉<Description of Signs of Major Parts of Drawings>
10 : 실리콘기판 11 : 접합부10 silicon substrate 11: junction
12 : 층간 절연막 13 : 폴리실리콘층12: interlayer insulation film 13: polysilicon layer
14 : Si3N4막 15 : SiON막14: Si 3 N 4 film 15: SiON film
16 : Ta2O5유전체막 17 : 상부 전하저장전극16: Ta 2 O 5 dielectric film 17: upper charge storage electrode
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1c는 본 발명에 따른 반도체 소자의 캐패시터 형성방법을 설명하기 위한 소자의 단면도이다.1A to 1C are cross-sectional views of devices for explaining a method of forming a capacitor of a semiconductor device according to the present invention.
도 1a를 참조하면, 접합부(11)가 형성된 반도체 기판상(10)에 층간 절연막(12)을 형성한 후 접합부(11)가 노출되도록 콘택홀을 형성한다. 그후 콘택홀을 매립하는 하부전하저장전극용 폴리실리콘층(13)을 형성한 후 1차 플라즈마 공정을 실시하여 폴리실리콘층(13)을 질화 시켜 폴리실리콘층(13) 표면에 Si3N4막(14)을 형성한다.Referring to FIG. 1A, an interlayer insulating layer 12 is formed on a semiconductor substrate 10 on which a junction 11 is formed, and then contact holes are formed to expose the junction 11. Thereafter, a polysilicon layer 13 for lower charge storage electrodes filling contact holes is formed, and then a first plasma process is performed to nitride the polysilicon layer 13 to form a Si 3 N 4 film on the surface of the polysilicon layer 13. (14) is formed.
상기 1차 플라즈마 공정은 챔버내 압력을 1 내지 2 Torr 유지하고, 400 내지 500℃ 온도의 서브 히터(Sub Heater)에서 100 내지 200 Watt의 고주파 전력으로1 내지 5 slm 양의 NH3또는 N2가스를 이용하여 1 내지 3 분간 실시한다.The first plasma process maintains the pressure in the chamber at 1 to 2 Torr and the NH 3 or N 2 gas in an amount of 1 to 5 slm at a high frequency power of 100 to 200 Watt in a sub heater having a temperature of 400 to 500 ° C. 1 to 3 minutes using.
도 1b는 2차 플라즈마 공정으로 Si3N4막(14)을 산화시켜 SiON막(15)을 형성한 상태의 단면도이다.FIG. 1B is a cross-sectional view of a state in which a Si 3 N 4 film 14 is oxidized to form a SiON film 15 by a secondary plasma process.
상기 2차 플라그마 공정은 챔버내의 압력을 수십 내지 수백 Torr 로 유지하고, 10 내지 100 sccm 농도의 O2가스를 이용하여 100 내지 500℃ 온도의 서브 히터에서 50 내지 400 Watt의 고주파 전력으로 1 내지 2 분간 실시한다. 이때 고주파 인가시 서브 히터느 그라운드(Ground)로 하고, 샤워 헤드(Shower Head)를 전극으로 한다.The secondary plasma process maintains the pressure in the chamber at several tens to several hundred Torr, and uses 1 to 100 high frequency power at 50 to 400 Watts in a sub heater having a temperature of 100 to 500 ° C. using O 2 gas at a concentration of 10 to 100 sccm. Run for 2 minutes. At this time, when applying high frequency, the sub heater is set to ground, and the shower head is used as an electrode.
또한, 상기 1차 및 2차 플라즈마 공정은 인-시튜(In-situ) 방법으로 실시한다.In addition, the primary and secondary plasma processes are carried out by an in-situ method.
도 1c는 전체상부면에 Ta2O5유전체막(16)을 형성한 후 열공정 및 상부 전하저장전극(17)을 형성하여 캐패시터를 완성한 상태의 단면도이다.FIG. 1C is a cross-sectional view of a state in which a capacitor is completed by forming a Ta 2 O 5 dielectric film 16 on an entire upper surface thereof, followed by a thermal process and an upper charge storage electrode 17.
Ta2O5유전체막(16)은 웨이퍼 온도를 300 내지 500℃로 하고, 0.1 내지 2 torr 의 반응로 압력과, 10 내지 500sccm 의 산소 및 0.005 내지 2cc 의 소오스 가스를 이용하여 50 내지 300 Watt의 고주파 전력 환경에서 저압 화학 기상증착 방법으로 형성한다.The Ta 2 O 5 dielectric film 16 has a wafer temperature of 300 to 500 ° C., a reaction temperature of 0.1 to 2 torr, 50 to 300 Watts using 10 to 500 sccm of oxygen and 0.005 to 2 cc of source gas. Formed by low pressure chemical vapor deposition in high frequency power environment.
상기 열공정은 N2O 가스 분위기 및 300 내지 500℃ 의 온도에서 플라즈마를 이용하여 열공정을 실시한 후 O2또는 N2O 분위기 및 750 내지 900℃ 의 노에서 열처리 (Furnace Anneal) 또는 급속 열산화 공정으로 실시한다.The thermal process is a thermal process using a plasma in a N 2 O gas atmosphere and a temperature of 300 to 500 ℃ and then heat treatment (Furnace Anneal) or rapid thermal oxidation process in a furnace of O 2 or N 2 O atmosphere and 750 to 900 ℃ To be carried out.
상부 전하저장전극(17)은 600 내지 700℃에서 TiN막으로 이루어 진다.The upper charge storage electrode 17 is made of a TiN film at 600 to 700 ° C.
상술한 바와 같이 하부 전하저장전극으로 사용되는 텅스텐 또는 TiN막은 고온에서 산화성이 강하여 유전체막인 Ta2O5사용시 고온의 N2O 또는 O2열공정을 적용하기 어려웠다.As described above, the tungsten or TiN film used as the lower charge storage electrode is highly oxidizable at high temperature, and thus it is difficult to apply a high temperature N 2 O or O 2 thermal process when using a dielectric film Ta 2 O 5 .
상술한 문제점을 해소되도록 본 발명은 전자 빔 처리 공정을 N2O 가스를 이용한 저온 열공정 후에 진행하므로 텅스텐이 산화 되지 않고 Ta2O5유전체막을 결정화 시킬 수 있다. 따라서, 보다 얇고 누설 전류가 낮은 Ta2O5유전체막 캐패시터를 형성할 수 있으므로 소자의 단차가 줄여들어 안정적인 금속 배선 공정을 진행 할 수 있고, 소자의 수율 및 동작 신뢰도가 향상된다.In order to solve the above problems, the present invention proceeds after the low temperature thermal process using the N 2 O gas, so that the tungsten is not oxidized and the Ta 2 O 5 dielectric film can be crystallized. Accordingly, a thinner Ta 2 O 5 dielectric film capacitor can be formed, thereby reducing the step height of the device, thereby enabling a stable metallization process, and improving the yield and operation reliability of the device.
Claims (4)
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| KR1019990025758A KR100356477B1 (en) | 1999-06-30 | 1999-06-30 | Method of forming a capacitor in a semiconductor device |
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| KR20010004979A (en) | 2001-01-15 |
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