KR20010109679A - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
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- KR20010109679A KR20010109679A KR1020000030083A KR20000030083A KR20010109679A KR 20010109679 A KR20010109679 A KR 20010109679A KR 1020000030083 A KR1020000030083 A KR 1020000030083A KR 20000030083 A KR20000030083 A KR 20000030083A KR 20010109679 A KR20010109679 A KR 20010109679A
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- silicon wafer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 44
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 44
- 239000010703 silicon Substances 0.000 claims abstract description 44
- 238000000034 method Methods 0.000 claims abstract description 23
- 239000012535 impurity Substances 0.000 claims abstract description 21
- 238000005247 gettering Methods 0.000 claims abstract description 14
- 238000000137 annealing Methods 0.000 claims abstract description 12
- 238000005468 ion implantation Methods 0.000 claims abstract description 11
- 230000000694 effects Effects 0.000 claims abstract description 9
- 238000000227 grinding Methods 0.000 claims abstract description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 4
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- 230000000630 rising effect Effects 0.000 claims 2
- 230000007547 defect Effects 0.000 abstract description 19
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 229910052751 metal Inorganic materials 0.000 description 13
- 239000002184 metal Substances 0.000 description 13
- 238000010438 heat treatment Methods 0.000 description 5
- 239000013078 crystal Substances 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- High Energy & Nuclear Physics (AREA)
- Power Engineering (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Element Separation (AREA)
Abstract
본 발명은 실리콘 웨이퍼 형성시 발생하는 결함 및 불순물들을 실리콘 웨이퍼 하부에서의 게터링 이온주입 효과를 이용하여 상기 결함 및 불순물들을 제거함으로써, 반도체 소자의 수율을 극대화 할수 있는 반도체 소자의 제조방법을 개시한다.The present invention discloses a method of manufacturing a semiconductor device capable of maximizing the yield of a semiconductor device by removing defects and impurities generated during formation of a silicon wafer by using a gettering ion implantation effect under the silicon wafer. .
개시된 본 발명은 실리콘 웨이퍼를 제공하는 단계; 실리콘 웨이퍼의 하부에 게터링 효과를 얻기 위하여 불순물을 이온주입하는 단계: 상기 이온주입된 실리콘 웨이퍼상에 고온 급속 어닐링 또는 스파이크 어닐링을 진행하여 반도체 소자를 형성하는 단계; 및 백 그라인딩 공정을 통해 게터링층을 포함한 실리콘 웨이퍼의 일부를 제거하는 단계로 구성하여 이루어지는 것을 특징으로 한다.The disclosed subject matter provides a silicon wafer; Implanting impurities into a lower portion of the silicon wafer to obtain a gettering effect: forming a semiconductor device by performing high temperature rapid annealing or spike annealing on the ion implanted silicon wafer; And removing a part of the silicon wafer including the gettering layer through a back grinding process.
Description
본 발명은 반도체 메모리 소자의 제조방법에 관한 것으로, 보다 구체적으로는, 실리콘 웨이퍼 형성시 그 하부에 생성되는 각종 결함 및 금속 불순물을 제거하는 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly, to a method for removing various defects and metal impurities generated under the silicon wafer.
일반적으로, 반도체 소자가 직접화 됨에 따라 소스/드레인 간의 채널 길이 및 접합의 깊이/폭이 감소하고, 웰 구조도 다양화 되고있다. 그런데, 단 결정 성장및 규소봉 절단 과정을 통해 형성되는 최초 695 ~ 725 마이크로 두께를 갖는 실리콘 웨이퍼 하부에는 각종 결함 및 금속 불순물들이 포함되어 있어, 반도체 소자 제조의 열공정 진행동안 상기 각종 결함 및 금속 불순물들로 인해 반도체 소자의 수율에 미치는 영항이 증가하고 있다.In general, as semiconductor devices become direct, the channel length between the source / drain and the depth / width of the junction are reduced, and the well structure is diversified. However, various defects and metal impurities are included in the lower portion of the silicon wafer having the first 695 to 725 micro thickness formed through the single crystal growth and the silicon rod cutting process. Due to this, the influence on the yield of semiconductor devices is increasing.
이에따라, 실리콘 웨이퍼 내에 결함 및 금속 불순물들이 생기지 않는 일정한 영역, 즉 디너디드 영역(Denuded Zone)의 하부에 상기의 각종 결함 및 금속 불순물들이 형성되는데, 반도체 소자의 고직접화에 따라 후속의 열공정 진행동안 디너디드 영역 부분에도 상기의 결함이 발생하여 이미 형성된 웰 및 접합부분에서 누설의 원인으로 작용된다.Accordingly, the above-mentioned various defects and metal impurities are formed in a predetermined region where defects and metal impurities do not occur in the silicon wafer, that is, under the denuded zone. The above defects also occur during the portion of the dinner area, which acts as a cause of leakage in the wells and junctions already formed.
도 1을 참조하면, 공지의 방법에 의해, 반도체 기판(1)상에 소자 분리막(2)과 게이트 전극(3), 그리고 스페이서(4) 및 소스/드레인 접합영역(5)이 형성된 상태에서 후속의 고온 열처리 공정을 진행하면서 실리콘 웨이퍼(1) 하부에 존재하는 각종 결함 및 금속 불순물들(6)이 운동에너지를 얻어 반도체 기판(1) 표면까지 확산되는 경향을 보인다. 따라서, 디너디드 영역 하부층에 형성되는 상기 각종의 결함 및 금속 불순물들(6)이 소스/드레인 접합영역(5)에 영향을 미친다.Referring to FIG. 1, a device isolation film 2, a gate electrode 3, and a spacer 4 and a source / drain junction region 5 are formed on a semiconductor substrate 1 by a known method. During the high temperature heat treatment process, various defects and metal impurities 6 existing under the silicon wafer 1 tend to obtain kinetic energy and diffuse to the surface of the semiconductor substrate 1. Therefore, the various defects and metal impurities 6 formed in the underlying layer of the dinner region affect the source / drain junction region 5.
상기와 같이 단 결정 성장 및 규소봉 절단 과정을 통해 형성되는 최초 695 ~ 725 마이크로 두께를 갖는 실리콘 웨이퍼 하부에는 각종의 결함 및 금속 불순물들이 존재한다. 이러한 각종의 결함 및 금속 불순물들은 반도체 소자 제조 공정 중에 고온 열처리 공정 진행시 운동에너지를 얻어 이미 형성되어 있는 웰(도시되어 있지않음) 및 접합영역(5)에 영향을 주어 누설의 원인이 되며, 이로 인해 반도체 소자의 수율에 미치는 영향이 크다.As described above, various defects and metal impurities exist in the lower portion of the silicon wafer having the initial thickness of 695 to 725 micro, which is formed through single crystal growth and silicon rod cutting. These various defects and metal impurities obtain kinetic energy during the high temperature heat treatment process during the semiconductor device manufacturing process, affecting the wells (not shown) and the junction region 5 already formed, which causes leakage. Due to the large impact on the yield of the semiconductor device.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로, 실리콘 웨이퍼 형성시 그 하부에 이온주입을 수행하여 불안정한 층을 만들어 줌으로써, 반도체 소자 제조 과정에서의 고온 열처리 공정 진행시 각종의 결함 및 금속 불순물들을 포획하여 디너디드 영역으로의 확산을 억제하는 것을 그 목적으로 한다.Accordingly, the present invention has been made to solve the above problems, by forming an unstable layer by performing ion implantation in the lower portion when forming a silicon wafer, various defects during the high temperature heat treatment process in the semiconductor device manufacturing process The purpose is to trap metal impurities and suppress diffusion into the dinner area.
도 1은 종래의 반도체 소자의 제조방법을 설명하기 위한 단면도.1 is a cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.
도 2a 내지 도 2d는 본 발명의 반도체 소자의 제조방법을 설명하기 위한 단면도.2A to 2D are cross-sectional views illustrating a method for manufacturing a semiconductor device of the present invention.
* 도면의 주요 부분에 대한 부호설명* Explanation of code for main part of drawing
10 : 실리콘 웨이퍼10 silicon wafer
10a : 이온주입된 실리콘 웨이퍼10a: ion implanted silicon wafer
11 : 게터링층11: gettering layer
12 : 각종의 결함 및 금속 불순물12: various defects and metal impurities
상기와 같은 목적을 달성하기 위하여, 본 발명은 실리콘 웨이퍼를 제공하는 단계; 실리콘 웨이퍼의 하부에 게터링 효과를 얻기 위하여 불순물을 이온주입하는 단계: 상기 이온주입된 실리콘 웨이퍼상에 고온 급속 어닐링 또는 스파이크 어닐링을 진행하여 반도체 소자를 형성하는 단계; 및 백 그라인딩 공정을 통해 게터링층을 포함한 실리콘 웨이퍼의 일부를 제거하는 단계로 구성하여 이루어지는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a step of providing a silicon wafer; Implanting impurities into a lower portion of the silicon wafer to obtain a gettering effect: forming a semiconductor device by performing high temperature rapid annealing or spike annealing on the ion implanted silicon wafer; And removing a part of the silicon wafer including the gettering layer through a back grinding process.
상기 불순물은 바람직하게 확산성이 작은 비소로 이온주입을 하고, 상기 실리콘 웨이퍼 하부의 이온주입은 하부표면으로 부터 200 ~ 295 마이크로미터 범위로 주입한다.The impurity is preferably implanted with arsenic having a small diffusivity, and the implant is implanted in the range of 200 to 295 micrometers from the lower surface of the silicon wafer.
또한 상기 고온급속 어닐링의 경우 상승온도 100 ~ 150℃/sec로 850 ~ 1150℃에서 1 ~ 15초간 진행하고, 스파이크 어닐링의 경우, 상승온도 100 ~ 200℃/sec로 850 ~ 1150 ℃에서 0 ~ 1초간 진행한다.In addition, the high temperature rapid annealing proceeds for 1 to 15 seconds at 850 to 1150 ° C. at an elevated temperature of 100 to 150 ° C./sec, and 0 to 1 at 850 to 1150 ° C. at an elevated temperature of 100 to 200 ° C./sec for spike annealing. Proceed for seconds.
(실시예)(Example)
이하, 첨부한 도면으로 본 발명의 바람직한 실시예를 상세히 설명한다.Hereinafter, preferred embodiments of the present invention will be described in detail with the accompanying drawings.
도 2a 내지 도 2d는 본 발명의 반도체 소자의 제조방법에 관한 것으로, 먼저 도 2a를 참조하면, 단결정 성장 및 규소봉 절단공정을 통해 형성된 실리콘 웨이퍼(10)의 하부에 게터링 효과를 얻기 위한 불안정한 층을 형성하기 위하여 확산성이 작은 비소(As75)를 이온주입한다. 상기 이온주입은 백사이드 블랭킷(Backside Blanket) 이온주입 공정으로 실시하되, 실리콘 웨이퍼(10)상에 반도체 소자를 제조하기 전에 수행하고, 상기 실리콘 웨이퍼 하부의 이온주입은 상부 표면으로부터 약 200 ~ 295 마이크로미터 이상의 깊이로 이온주입을 수행한다. 또한, 상기 실리콘 웨이퍼 영역상에서 특정 영역만 불안정한 층을 형성하고자 하는 경우에는 블럭킹 (Blocking) 마스크 공정을 수행하여 일정 영역에만 이온주입 공정을 수행할 수도 있다.2A to 2D are related to the method of manufacturing a semiconductor device of the present invention. Referring first to FIG. 2A, unstable to obtain a gettering effect on a lower portion of a silicon wafer 10 formed through a single crystal growth and silicon rod cutting process. In order to form a layer, arsenic (As75) having low diffusivity is ion implanted. The ion implantation is performed by a backside blanket ion implantation process, before fabricating the semiconductor device on the silicon wafer 10, and the ion implantation of the silicon wafer is performed at about 200 to 295 micrometers from the upper surface. Ion implantation is performed to the above depth. In addition, in the case where it is desired to form an unstable layer only in a specific region on the silicon wafer region, a blocking mask process may be performed to perform an ion implantation process only in a predetermined region.
도 2b를 참조하면, 상기 이온 주입된 실리콘 웨이퍼(10a) 하부에 이온주입 공정에 의해 발생할 수도 있는 부수적인 결함 및 불순물들을 제거하기 위해 고온 급속 어닐링(RTA) 또는 스파이크(Spike) 어닐링 공정을 수행하여 상기 이온주입된 영역을 결정화하여 불안정한 층을 형성 시킨다. 이때 상기 결정화된 불안정한 층이 게터링층(11) 역할을 한다.Referring to FIG. 2B, a high temperature rapid annealing (RTA) or spike annealing process is performed to remove ancillary defects and impurities that may be caused by an ion implantation process under the ion implanted silicon wafer 10a. The ion implanted region is crystallized to form an unstable layer. At this time, the crystallized unstable layer serves as the gettering layer 11.
그 다음으로 도 2c를 참조하면, 상기 결과물을 갖는 실리콘 웨이퍼(10a)상에 통상적인 반도체 소자를 제조하기 위한 고온공정이 진행되면, 상기 실리콘 웨이퍼(10a) 하부에 이미 형성되어 있는 각종의 결함 및 금속 불순물들(12)이 운동에너지를 얻는다. 하지만, 상기 운동에너지를 갖는 각종의 결함 및 금속 불순물들(12)은 이미 형성되어 있는 게터링층(11)에 포획되어 상기 실리콘 웨이퍼(10a) 상부로의 확산이 억제되고, 동시에 상기 결함의 이동속도가 감소된다.Next, referring to FIG. 2C, when a high temperature process for manufacturing a conventional semiconductor device is performed on the silicon wafer 10a having the resultant, various defects already formed under the silicon wafer 10a and Metal impurities 12 obtain kinetic energy. However, the various defects and metal impurities 12 having the kinetic energy are trapped in the gettering layer 11 already formed, and the diffusion of the defects to the upper portion of the silicon wafer 10a is suppressed, and at the same time, the movement of the defects Speed is reduced.
도 2d를 참조하면, 상기 실리콘 웨이퍼(10a)상에 반도체 제조공정이 완료된 후에 공지된 방식인 백 그라인딩(Back Grinding) 공정을 수행하여 실리콘 웨이퍼중 약 400 마이크로 미터 정도의 게터링층(11)을 포함한 부분을 제거한다.Referring to FIG. 2D, after the semiconductor manufacturing process is completed on the silicon wafer 10a, a back grinding process, which is a known method, is performed to obtain a gettering layer 11 of about 400 micrometers in the silicon wafer. Remove the part that contains it.
상기 최초의 실리콘 웨이퍼의 두께는 695 ~ 725 마이크로미터 정도이고, 반도체 소자의 제조공정이 완료된 후에는 백 그라인딩 공정을 통해 최종 두께가 200 ~ 295 마이크로미터 정도가 된다.The first silicon wafer has a thickness of about 695 to 725 micrometers, and after the semiconductor device manufacturing process is completed, the final thickness is about 200 to 295 micrometers through a back grinding process.
본 발명의 다른 실시예를 살펴보면, 상기 실리콘 웨이퍼 하부의 이온주입을 수행함으로써, 약한 데미지(Soft-Soft Damage)의 효과를 주어 고유의 게터링 효과를 최대로 극대화 하여, 상기 실리콘 웨이퍼 하부에 형성되어 있는 금속 불순물 및 각종의 결함을 포획한다.Looking at another embodiment of the present invention, by performing ion implantation in the lower portion of the silicon wafer, the effect of the soft damage (Soft-Soft Damage) to maximize the inherent gettering effect is formed on the lower portion of the silicon wafer Captures metallic impurities and various defects.
위에서 자세히 설명된 바와 같이, 본 발명의 반도체 소자의 제조방법은, 반도체 소자 제조 과정에서의 고온 열처리 공정 전 상기 실리콘 웨이퍼 하부에 게터링 효과를 얻을수 있는 이온주입을 함으로써, 후속 공정인 고온 열처리 공정에서 상기 실리콘 웨이퍼 형성시 발생하는 각종의 결함 및 금속 불순물들이 실리콘 웨이퍼 상부층으로의 확산을 억제하여 실리콘 웨이퍼의 악화를 방지한다.As described in detail above, the manufacturing method of the semiconductor device of the present invention, in the subsequent high-temperature heat treatment process by ion implantation to obtain a gettering effect on the lower portion of the silicon wafer before the high temperature heat treatment process in the semiconductor device manufacturing process Various defects and metal impurities generated during the formation of the silicon wafer are suppressed from spreading to the upper surface of the silicon wafer to prevent deterioration of the silicon wafer.
따라서, 반도체 메모리 소자의 수율을 극대화 할 수 있는 효과가 있다.Therefore, there is an effect that can maximize the yield of the semiconductor memory device.
한편, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시 할 수 있다.In addition, this invention can be implemented in various changes in the range which does not deviate from the summary.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100698981B1 (en) * | 2004-03-25 | 2007-03-26 | 엘피다 메모리, 아이엔씨. | Semiconductor device and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100698981B1 (en) * | 2004-03-25 | 2007-03-26 | 엘피다 메모리, 아이엔씨. | Semiconductor device and manufacturing method thereof |
| US7666761B2 (en) | 2004-03-25 | 2010-02-23 | Elpida Memory, Inc. | Semiconductor device and manufacturing method thereof |
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