KR20010096352A - Semiconductor Memory Device And Manufacturing Thereof - Google Patents

Abstract

PURPOSE: A semiconductor memory device and a fabrication method thereof are provided to prevent oxidation of a bit line by forming a process between the bit line and a silicon oxide layer to form a contact hole. CONSTITUTION: An active region is formed on a semiconductor substrate. A gate electrode is formed by etching a gate oxide layer and a gate electrode layer laminated on the active region. An interlayer dielectric(25) and the first antioxidation layer(30) are laminated sequentially on the whole surface of the above structure. A bit line contact hole(35) connected with the active region or the gate electrode is formed by etching the interlayer dielectric(25) and the first antioxidation layer(30). A bit line(40) is laminated within the bit line contact hole(35). The bit line(40) is connected with the active region or the gate electrode(20). The second antioxidation layer(45) is formed on the bit line(40). A spacer(50) is formed on a side of the bit line(40). A contact hole spacer(60) is formed on an inner wall of the bit line contact hole(35) in order to prevent oxidation of the bit line(40).

Description

Semiconductor memory device and manufacturing method thereof {Semiconductor Memory Device And Manufacturing Thereof}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device of a semiconductor device, and more particularly, to form a contact hole by applying an anti-oxidation film between a bit line and a silicon oxide film used as a planarization layer below the bit line on a semiconductor substrate, so that the bit line is formed of oxygen and The present invention relates to a method of manufacturing a semiconductor memory device in which a low resistance material is used in a state in which a reaction is prevented, thereby improving the yield of the device and preventing the speed decrease due to wiring.

In general, semiconductor memory devices play a leading role in high integration with the development of semiconductor manufacturing technology, and the size of memory cells is correspondingly reduced as the design rules of the memory devices become smaller. On the other hand, due to the high integration of semiconductor memory devices, the size of the entire chip increases according to the degree of integration.

As the size of the semiconductor chip increases, the length of the lines used for wiring increases, leading to a decrease in the overall speed performance of the chip, which in turn serves as a limiting factor for high integration.

In order to solve this problem, a low resistance material is applied to the lines used for wiring. Therefore, low resistance silicides or metal materials such as TiSi ₂ , CoSi _2, W, TiN, Ta, and TaN, which have low resistance, are used instead of tungsten silicide (WSi ₂ ), which is widely used in bit lines in semiconductor memory devices. The method of applying to wiring is invented.

In addition, in using a COB (Capacitor On Bit Line) structure in order to increase the capacity of a capacitor in a semiconductor memory process, a high temperature process is essentially used for a process of forming an electrode or a dielectric of a capacitor.

Moreover, the heat processing used for vapor deposition and planarization of the insulating film used as an interlayer insulation film may also be performed by a high temperature process.

However, when the low resistance material is used for the bit line and the subsequent high temperature process is performed, it reacts very well with oxygen during the heat treatment process, and cracks and lifting due to the high temperature process due to the volume expansion occurring therein A defect such as (Lifting) occurs.

In addition, compared to other materials used in silicon semiconductors, the coefficient of thermal expansion of the metal is relatively very large, resulting in a failure due to the stress caused by the volume expansion, which can not proceed to the subsequent process.

In order to solve this problem, as shown in Figure 1, to apply a low-resistance bit line, a conventional bit line forming method will be described.

After the device isolation film 2 is formed on the semiconductor substrate 1 by a device isolation process, the gate electrode 3 is formed on the upper surface thereof.

Then, the interlayer insulating film 4 is laminated on the resultant, the contact hole is formed by masking etching, a polysilicon layer or a metal layer is embedded in the contact hole 5, and the antioxidant film 7 is laminated. After etching, the bit line 6 is formed. Then, a spacer is formed in the side portion of the bit line 6.

However, even in the case of the bit line capped with an anti-oxidation film on the bit line 6 of FIG. 1, there is an uncapped portion between the silicon oxide film used as the planarization layer under the bit line 6, and thus There is a problem in that a defect occurs in the high temperature process can not continue the subsequent process. In addition, there is a problem that acts as a cause of the secondary pollution to the equipment or wafer due to this.

The present invention has been made in view of the above-mentioned problems, and since the contact hole is formed between the bit line and the silicon oxide film used as the planarization layer below the bit line on the semiconductor substrate, the bit line reacts with oxygen. Since the low-resistance material is used in the prevented state, the object is to improve the yield of the device and to prevent the speed decrease by the wiring.

1 is a view showing the structure of a conventional memory device,

2 (a) to 2 (d) illustrate a method of manufacturing a semiconductor memory device according to an embodiment of the present invention.

3 is a block diagram illustrating a memory device of a semiconductor device according to another embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

10: semiconductor substrate 15: device isolation film

20 gate electrode 25 interlayer insulating film

30: first antioxidant film 35: bit line contact window

40: bit line 45: second antioxidant film

50 spacer 60 contact window spacer

This object includes an active region formed by separating the device isolation film on the semiconductor substrate; A gate electrode formed by laminating and etching a gate oxide layer and a gate electrode layer on the active region; An interlayer insulating film and a first antioxidant film sequentially stacked on the gate electrode; A bit line contact window formed by etching the interlayer insulating layer and the first antioxidant layer and connected to the active region or the gate electrode; A bit line embedded in the bit line contact window and electrically connected to an active region or a gate electrode; It is achieved by providing a semiconductor memory device comprising a second antioxidant film formed on the bit line.

In addition, the bit line preferably uses a low resistance silicide or a metal material selected from any one of TiSi ₂ , CoSi _2, W, TiN, Ta, or TaN.

A contact window spacer is formed on an inner wall surface of the bit line contact window.

In addition, another object of the present invention, forming a device isolation film to separate the active region in the device isolation film forming process on the semiconductor substrate; Stacking the gate oxide layer and the gate electrode layer after the step and masking etching to form a gate electrode; Sequentially depositing an interlayer insulating layer and a first antioxidant layer on the resultant, and forming a bit line contact window connected to the active region by a photolithography process; Stacking a metal layer and a second anti-oxidation layer in the bit line contact window and patterning the photoresist to form a resistive bit line; It is achieved by providing a semiconductor memory manufacturing method comprising the step of forming a spacer on the side of the bit line by laminating an etch stop layer on the resultant.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

First, referring to the configuration according to the present invention, as shown in FIG. 2 (d), the active region 17 is separated into the device isolation film 15 by the device isolation process on the semiconductor substrate 10; A gate electrode 20 formed by laminating and etching a gate oxide layer and a gate electrode layer on the active region 17; An interlayer insulating film 25 and a first antioxidant film 30 sequentially stacked on the gate electrode 20; A bit line contact window 35 formed by etching the interlayer insulating layer 25 and the first antioxidant layer 30 and connected to the active region 17 or the gate electrode 20; A bit line 40 embedded in the bit line contact window 35 and electrically connected to the active region 17 or the gate electrode 20; And a second antioxidant layer 45 formed on the bit line 35.

In addition, the bit line 40 may be formed of a low resistance silicide or metal material selected from any one of TiSi ₂ , CoSi _2, W, TiN, Ta _, and TaN.

In addition, it is preferable to form a contact window spacer 60 on the inner wall surface of the bit line contact window 35.

Hereinafter, look at the manufacturing method according to an embodiment of the present invention.

As shown in FIG. 2A, an active region 17 separated from the device isolation layer 15 is formed on the semiconductor substrate 10 by a device isolation process.

The device isolation layer 15 may be formed using a shallow trench isolation (STI) process. However, if necessary, the device isolation layer 15 may be formed using another process.

Subsequently, the gate oxide layer and the gate electrode layer are sequentially stacked and then masked and etched to form the gate electrode 20.

As shown in FIG. 2 (b), the interlayer insulating film 25 is planarized on the resultant, the first antioxidant film 30 is sequentially stacked, and then the bit is connected to the active region 17 by a photolithography process. The line contact window 35 is formed.

At this time, the planarization is to heat-treat the silicon oxide film or to planarize using CMP polishing (Chemical Mechanical Polishing).

As shown in FIG. 2 (c), a conductive metal layer and a second antioxidant layer 45 are stacked in the bit line contact window 35, and then patterned by a photolithography process to form a low resistance bit line 40. To form.

When the bit line 40 is formed by etching the metal layer, over etching is performed to simultaneously etch the first antioxidant layer 30.

The bit line 40 preferably uses a low resistance silicide or metal material selected from any one of TiSi ₂ , CoSi _2, W, TiN, Ta, or TaN.

The second antioxidant film 45 is to form a silicon nitride film that can prevent the diffusion of oxygen.

As shown in FIG. 2 (d), after the etch stop layer is deposited on the entire surface of the resultant body, the spacer 50 is formed on the side surface of the bit line 40 by anisotropic etching.

In this case, the spacer 50 is deposited at a low pressure to improve step coverage, so that the metal bit line is formed as a result of the first and second antioxidant layers 30 and 45 and the antioxidant spacer ( 50) to be completely capped. This means that the metal bit line 40 is safely protected in a subsequent process, so that the subsequent device process can be easily performed.

3 is a view showing another embodiment according to the present invention, since the spacer 60 is formed on the inner wall surface of the bit line contact window 35, the bit line 40 is oxidized through the bit line contact window 35. To prevent it.

As described above, when the semiconductor memory device and the manufacturing method thereof according to the present invention are used, a contact hole is formed on a semiconductor substrate by applying an anti-oxidation film between the bit line and the silicon oxide film used as the planarization layer below the bit line. Therefore, it is a very useful and effective invention to improve the yield of the device because the low resistance material is used while preventing the bit line from reacting with oxygen.

In addition, since it is possible to solve the problem of the failure of the subsequent process in forming the bit line, it is possible to use a variety of low-resistance bit line has the advantage of improving the speed of the semiconductor memory device.

Claims (6)

An active region formed on the semiconductor substrate; A gate electrode formed by laminating a gate oxide layer and a gate electrode layer on the active region and then etching the gate electrode layer; An interlayer insulating film and a first antioxidant film sequentially stacked on the resultant material; A bit line contact window formed to etch the interlayer insulating layer and the first antioxidant layer to the active region or the gate electrode; A bit line stacked in the bit line contact window and electrically connected to an active region or a gate electrode; And a second antioxidant layer formed on the bit line. The semiconductor memory device of claim 1, wherein the bit line uses a low resistance silicide or a metal material selected from any one of TiSi ₂ , CoSi _2, W, TiN, Ta _, and TaN. 2. The semiconductor memory device according to claim 1, wherein a contact window spacer is formed on an inner wall surface of the bit line contact window. The semiconductor memory device according to claim 1, wherein the first and second antioxidant films are silicon nitride films. Forming a device isolation film on the semiconductor substrate to separate the active region through a device isolation film formation process; Stacking the gate oxide layer and the gate electrode layer after the step and masking etching to form a gate electrode; Sequentially depositing an interlayer insulating layer and a first antioxidant layer on the resultant, and forming a bit line contact window connected to the active region by a photolithography process; Stacking a metal layer and a second anti-oxidation layer in the bit line contact window and patterning the photoresist layer to form a low resistance bit line; Stacking an etch stop layer on the resultant to form a spacer on the side of the bit line. 6. The method of claim 5, further comprising forming a contact window spacer on an inner wall surface of the bit line contact window.