KR20010096346A - Method For Polishing The Semiconductor Device Using The Buffer Oxide Layer - Google Patents
Method For Polishing The Semiconductor Device Using The Buffer Oxide Layer Download PDFInfo
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- KR20010096346A KR20010096346A KR1020000020443A KR20000020443A KR20010096346A KR 20010096346 A KR20010096346 A KR 20010096346A KR 1020000020443 A KR1020000020443 A KR 1020000020443A KR 20000020443 A KR20000020443 A KR 20000020443A KR 20010096346 A KR20010096346 A KR 20010096346A
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- 238000000034 method Methods 0.000 title claims abstract description 32
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000005498 polishing Methods 0.000 title claims abstract description 9
- 239000011229 interlayer Substances 0.000 claims abstract description 43
- 239000010410 layer Substances 0.000 claims abstract description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 16
- 229920005591 polysilicon Polymers 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 150000004767 nitrides Chemical class 0.000 claims abstract description 9
- 125000006850 spacer group Chemical group 0.000 claims abstract description 6
- 238000010438 heat treatment Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- 238000007517 polishing process Methods 0.000 claims description 7
- 238000010030 laminating Methods 0.000 claims description 4
- 230000000873 masking effect Effects 0.000 claims description 4
- 238000000151 deposition Methods 0.000 abstract description 2
- 239000000126 substance Substances 0.000 abstract description 2
- 238000000137 annealing Methods 0.000 abstract 1
- 238000000059 patterning Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 230000005856 abnormality Effects 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
Description
본 발명은 반도체소자의 게이트를 형성한 후 층간절연막을 적층하여 평탄화하는 공정에 관한 것으로서, 특히, 반도체기판에 적층된 층간절연막 상에 버퍼산화막을 적층한 후에 평탄화공정을 진행하므로, 층간절연막에 디슁이 발생되는 것을 방지하여 워드라인의 파손을 예방하도록 하는 버퍼산화막을 이용한 반도체소자 평탄화방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a process of stacking and planarizing an interlayer insulating film after forming a gate of a semiconductor device. In particular, the planarization process is performed after laminating a buffer oxide film on an interlayer insulating film stacked on a semiconductor substrate. The present invention relates to a method of planarizing a semiconductor device using a buffer oxide film to prevent the occurrence of damage to the word line.
일반적으로, 워드라인(Word Line)과 비트라인(Bit Line)의 층간절연막을 사용되는 BPSG(Boro-Phosphosilicalte Glass)절연막은 열처리에 의하여 유동성을 갖으므로 후속 공정에서 층간절연막을 평탄화하는 과정에서 심하게 연마되어지는 과도 디슁부위가 발생되어져서 워드라인의 파손을 야기하는 문제를 지닌다.In general, the BPSG (Boro-Phosphosilicalte Glass) insulating film using the interlayer insulating film of Word Line and Bit Line has fluidity by heat treatment, so it is severely polished in the process of planarizing the interlayer insulating film in a subsequent process. Excessive dedigging parts are generated, which causes the problem of word line breakage.
도 1(a) 내지 도 1(e)는 종래의 반도체소자의 층간절연막을 평탄화하는 공정을 순차적으로 보인 도면이다.1 (a) to 1 (e) are diagrams sequentially showing a process of planarizing an interlayer insulating film of a conventional semiconductor device.
도 1(a)에 도시된 바와 같이, 반도체기판(1) 상의 셀영역(Cell Region)과 페리영역(Peripherial Region) 상에 게이트산화막(2), 폴리실리콘층(3), 폴리실리사이드층(4), 마스크산화막(5) 및 마스크질화막(6)을 적층한 후, 마스킹 식각 공정을 거쳐 식각하고, 양측면에 스페이서막(7)을 적층하여서 게이트(A)를 형성하도록 한다.As shown in FIG. 1A, a gate oxide film 2, a polysilicon layer 3, and a polysilicide layer 4 are formed on a cell region and a peripheral region on the semiconductor substrate 1. ), The mask oxide film 5 and the mask nitride film 6 are laminated, and then etched through a masking etching process, and the spacer film 7 is laminated on both sides to form the gate A. FIG.
도 1(b)에 도시된 바와 같이, 상기 결과물 상에 BPSG로 된 층간절연막(8)을적층하도록 한다.As shown in Fig. 1 (b), an interlayer insulating film 8 made of BPSG is laminated on the resultant product.
이 때, 상기 결과물에 열공정을 가하는 경우, "a"로 표시된 층간절연막(8)의 적층 상태가 열공정으로 인하여 흘러내려서 "b"로 표시된 표면 상태로 형성되어지게 된다.At this time, when the thermal process is applied to the resultant, the lamination state of the interlayer insulating film 8 denoted by "a " flows down due to the thermal process to form a surface state denoted by " b ".
그리고, 도 1(c)에 도시된 바와 같이, 상기 층간절연막(8)을 CMP연마 (Chemical Mechanical Polishing)공정으로 평탄화하도록 한다.As shown in FIG. 1C, the interlayer insulating film 8 is planarized by a CMP polishing (Chemical Mechanical Polishing) process.
그리고, 도 1(d)에 도시된 바와 같이, 상기 셀영역의 게이트(A)를 노출하도록 감광막을 적층하여 식각으로 콘택홀(11)을 형성한 후, 플러그 폴리실리콘층(9)을 매립하도록 한다.As shown in FIG. 1 (d), the photoresist layer is stacked to expose the gate A of the cell region to form a contact hole 11 by etching, and then the plug polysilicon layer 9 is embedded. do.
그런 후에 도 1(e)에 도시된 바와 같이, 상기 플러그 폴리실리콘층(9)을 CMP공정으로 평탄화하도록 한다.Thereafter, as shown in FIG. 1E, the plug polysilicon layer 9 is planarized by a CMP process.
그러나, 상기한 바와 같이, 종래에는 반도체기판 게이트(A)를 형성하고, 층간절연막(8)을 적층한 후, 열공정을 진행하는 경우, 층간절연막이 "b"로 표시된 상태로 흘러내리게 되어 도 1(c)에 도시된, 후속 층간절연막 평탄화공정에서 페리영역의 층간절연막에 "c"로 표시된 두께 만큼의 디슁(Dishing)이 발생하게 된다.However, as described above, when the semiconductor substrate gate A is formed, the interlayer insulating film 8 is laminated, and the thermal process is performed, the interlayer insulating film may flow down in the state indicated by "b". In the subsequent interlayer insulating film planarization process shown in 1 (c), dishing occurs as much as the thickness indicated by "c" in the interlayer insulating film of the ferry region.
그로 인하여 후속공정에서 플러그 폴리실리콘층(9)을 CMP연마공정으로 평탄화하는 경우 도 1(e)에 도시된 바와같이, 페리영역의 게이트(A)가 파손되어 배선 간의 전기적인 브릿지(Bridge)를 유발하여 소자의 전기적인 특성을 악화하는 문제점을 지닌다.Therefore, when the plug polysilicon layer 9 is planarized by the CMP polishing process in a subsequent process, as shown in FIG. 1 (e), the gate A of the ferry region is broken, and the electrical bridge between the wirings is broken. Causing deterioration of the electrical characteristics of the device.
한편, 도 2는 종래의 반도체소자의 평탄화방법을 인하여 워드라인에 이상이발생한 상태를 보인 도면으로서, 페리영역에 적층된 층간절연막의 과도식각으로 인하여 워드라인이 파손된 상태를 보이고 있다.Meanwhile, FIG. 2 is a diagram showing a state in which an abnormality occurs in a word line due to a conventional planarization method of a semiconductor device, and shows a state in which a word line is damaged due to excessive etching of an interlayer insulating layer stacked in a ferry region.
본 발명은 이러한 점을 감안하여 안출한 것으로서, 반도체기판 상에 게이트산화막 및 폴리실리콘층등을 식각하여 게이트를 형성한 후, 층간절연막을 증착하고, 연속하여 열에 의하여 층간절연막이 흘러내리는 것을 방지하기 위하여 버퍼산화막을 적층한 후에 평탄화공정을 진행하므로, 디슁이 발생되는 것을 방지하여 워드라인의 파손을 예방하는 것이 목적이다.SUMMARY OF THE INVENTION The present invention has been made in view of this point, and after forming a gate by etching a gate oxide film, a polysilicon layer, etc. on a semiconductor substrate, depositing an interlayer insulating film, and subsequently preventing the interlayer insulating film from flowing down by heat. Since the planarization process is performed after laminating the buffer oxide film, the purpose is to prevent the occurrence of digging and to prevent breakage of the word line.
도 1(a) 내지 도 1(e)는 종래의 반도체소자의 층간절연막을 평탄화하는 공정을 순차적으로 보인 도면이고,1 (a) to 1 (e) are diagrams sequentially showing a process of planarizing an interlayer insulating film of a conventional semiconductor device;
도 2은 종래의 반도체소자의 평탄화방법을 인하여 워드라인에 이상이 발생한 상태를 보인 도면이고,2 is a view illustrating a state in which an abnormality occurs in a word line due to a conventional planarization method of a semiconductor device.
도 3(a) 내지 도 3(e)는 본 발명에 따른 반도체소자의 층간절연막을 평탄화하는 방법을 순차적으로 보인 도면이다.3 (a) to 3 (e) are diagrams sequentially illustrating a method of planarizing an interlayer insulating film of a semiconductor device according to the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
10 : 반도체기판 15 : 게이트산화막10: semiconductor substrate 15: gate oxide film
20 : 폴리실리콘층 25 : 폴리실리사이드층20 polysilicon layer 25 polysilicide layer
30 : 마스크산화막 35 : 마스크질화막30 mask oxide film 35 mask nitride film
40 : 스페이서막 45 : 층간절연막40 spacer film 45 interlayer insulating film
50 : 버퍼산화막 55 : 콘택홀50: buffer oxide film 55: contact hole
60 : 폴리실리콘층60: polysilicon layer
이러한 목적은 반도체기판 상에 게이트산화막, 폴리실리콘층, 폴리실리사이드층, 마스크산화막 및 마스크질화막을 적층하여 식각한 후, 스페이서막을 적층하여 게이트를 형성하는 단계와; 상기 결과물 상에 층간절연막을 적층하고, 연속하여 그 상부면에 버퍼산화막을 적층한 후 열처리하는 단계와; 상기 버퍼산화막 및 층간절연막을 CMP연마공정으로 평탄화하는 단계와; 상기 결과물에서 플러그 마스킹공정으로 셀영역의 게이트를 개방하도록 콘택홀을 형성한 후, 플러그 폴리실리콘층을 적층하는 단계와; 상기 결과물을 CMP연마공정으로 평탄화하는 단계를 포함하여 이루어진 버퍼산화막을 이용한 반도체소자 평탄화방법을 제공함으로써 달성된다.The object is to stack and etch a gate oxide film, a polysilicon layer, a polysilicide layer, a mask oxide film, and a mask nitride film on a semiconductor substrate, and then stack a spacer film to form a gate; Stacking an interlayer insulating film on the resultant, successively laminating a buffer oxide film on an upper surface thereof, and then performing heat treatment; Planarizing the buffer oxide film and the interlayer dielectric film by a CMP polishing process; Forming a contact hole to open the gate of the cell region by a plug masking process in the resultant, and then stacking a plug polysilicon layer; It is achieved by providing a method of planarizing a semiconductor device using a buffer oxide film comprising the step of planarizing the result by a CMP polishing process.
그리고, 상기 버퍼산화막은, 층간절연막과 연마선택비가 1.5 : 1 이상되는산화막으로서, 100 ∼ 2000Å의 두께로 적층하도록 한다.The buffer oxide film is an oxide film having an interlayer insulating film and a polishing selectivity of 1.5: 1 or more, and laminated at a thickness of 100 to 2000 GPa.
상기 버퍼산화막과 층간절연막을 열처리할 때, 650 ∼ 900℃의 온도범위에서 열처리하는 것이 바람직 하다.When the heat treatment of the buffer oxide film and the interlayer insulating film, it is preferable to heat treatment at a temperature range of 650 ~ 900 ℃.
상기 버퍼산화막과 층간절연막을 CMP연마를 할 때, 게이트의 마스크질화막 상에 잔류되는 층간절연막이 500 ∼ 3500Å인 것이 바람직 하다.When CMP polishing the buffer oxide film and the interlayer insulating film, the interlayer insulating film remaining on the mask nitride film of the gate is preferably 500 to 3500 kV.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 일실시예에 대해 상세하게 설명하고자 한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.
도 3(a)에 도시된 바와 같이, 반도체기판(10) 상에 게이트산화막(15), 폴리실리콘층(20), 폴리실리사이드층(25), 마스크산화막(30) 및 마스크질화막(35)을 적층하여 식각한 후, 스페이서막(40)을 적층하여 게이트(B)를 형성하도록 한다.As shown in FIG. 3A, the gate oxide film 15, the polysilicon layer 20, the polysilicide layer 25, the mask oxide film 30, and the mask nitride film 35 are formed on the semiconductor substrate 10. After lamination and etching, the spacer layer 40 is laminated to form the gate B.
도 3(b)에 도시된 바와 같이, 상기 결과물 상에 층간절연막(45)을 적층하고, 연속하여 그 상부면에 버퍼산화막(50)을 적층한 후, 열처리하도록 한다.As shown in FIG. 3 (b), an interlayer insulating film 45 is stacked on the resultant, and a buffer oxide film 50 is successively stacked on the upper surface thereof, and then heat treated.
상기 버퍼산화막(50)은, 층간절연막과 연마선택비가 1.5 : 1 이상되는 산화막으로서, 100 ∼ 2000Å의 두께로 적층하도록 한다.The buffer oxide film 50 is an oxide film having an interlayer insulating film and a polishing selectivity of 1.5: 1 or more, and laminated at a thickness of 100 to 2000 GPa.
한편, 상기 버퍼산화막(50)과 층간절연막(45)을 열처리할 때, 650 ∼ 900℃의 온도범위에서 열처리하도록 한다.Meanwhile, when the buffer oxide film 50 and the interlayer insulating film 45 are heat treated, the heat treatment is performed at a temperature range of 650 to 900 ° C.
도 3(c)에 도시된 바와 같이, 상기 버퍼산화막(50) 및 층간절연막(45)을 CMP연마공정으로 평탄화하도록 한다.As shown in FIG. 3 (c), the buffer oxide film 50 and the interlayer dielectric film 45 are planarized by a CMP polishing process.
상기 버퍼산화막(50)과 층간절연막(45)을 CMP연마를 할 때, 게이트(A)의 마스크질화막(35) 상에 잔류되는 층간절연막(45)이 500 ∼ 3500Å정도의 두께가 되도록 한다.When CMP polishing the buffer oxide film 50 and the interlayer insulating film 45, the interlayer insulating film 45 remaining on the mask nitride film 35 of the gate A is made to have a thickness of about 500 to 3500 kPa.
이 때, 종래에는 버퍼산화막(50)을 증착하지 않은 경우, 점선으로 나타낸 "d"로 표시된 두께 만큼의 차이를 가지면서 디슁이 발생되는 반면에 본 발명에서는 버퍼산화막(50)으로 인하여 열처리공정에서 층간절연막(45)이 흘러내리지 않게 되어서 디슁이 발생하지 않게 된다.At this time, when the buffer oxide film 50 is not deposited in the related art, dichroic is generated while having a difference of the thickness indicated by the dotted line “d”, whereas in the present invention, the buffer oxide film 50 is used in the heat treatment process. The interlayer insulating film 45 does not flow down, so that desing does not occur.
도 3(d)에 도시된 바와 같이, 상기 결과물에서 플러그 마스킹공정으로 셀영역의 게이트(A)를 개방하도록 콘택홀(50)을 형성한 후, 플러그 폴리실리콘층(60)을 적층하도록 한다.As shown in FIG. 3 (d), after forming the contact hole 50 to open the gate A of the cell region by the plug masking process, the plug polysilicon layer 60 is laminated.
도 3(e)에 도시된 바와 같이, 상기 결과물을 CMP연마공정으로 평탄화하도록 한다.As shown in FIG. 3 (e), the resultant is planarized by a CMP polishing process.
상기한 바와 같이, 본 발명에 따른 버퍼산화막을 이용한 반도체소자 평탄화방법을 이용하게 되면, 반도체기판 상에 게이트산화막 및 폴리실리콘층등을 증착하여 식각으로 게이트를 형성한 후, 층간절연막을 증착하고, 연속하여 열에 의하여 층간절연막이 흘러내리는 것을 방지하기 위하여 버퍼산화막을 적층한 후 평탄화공정을 진행하므로 층간절연막에 디슁(Over dishing)이 발생되는 것을 방지하여 워드라인의 파손을 예방하도록 하는 매우 유용하고 효과적인 발명이다.As described above, when the semiconductor device planarization method using the buffer oxide film according to the present invention is used, a gate oxide film and a polysilicon layer are deposited on the semiconductor substrate to form a gate by etching, and then an interlayer insulating film is deposited. In order to prevent the interlayer insulating film from flowing down by heat in succession, a buffer oxide film is laminated and then a planarization process is performed. Thus, over dishing is prevented from occurring in the interlayer insulating film to prevent word line breakage. Invention.
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| KR1020000020443A KR20010096346A (en) | 2000-04-18 | 2000-04-18 | Method For Polishing The Semiconductor Device Using The Buffer Oxide Layer |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100906641B1 (en) * | 2002-12-27 | 2009-07-07 | 주식회사 하이닉스반도체 | Method of fabricating for semiconductor device with landing plug |
| CN106356295A (en) * | 2015-07-16 | 2017-01-25 | 中芯国际集成电路制造(上海)有限公司 | Chemical mechanical polishing method of interlayer dielectric layer, and device and electronic equipment with interlayer dielectric layer |
| CN106356300A (en) * | 2015-07-16 | 2017-01-25 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor apparatus and manufacturing method thereof and electronic device |
-
2000
- 2000-04-18 KR KR1020000020443A patent/KR20010096346A/en not_active Application Discontinuation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100906641B1 (en) * | 2002-12-27 | 2009-07-07 | 주식회사 하이닉스반도체 | Method of fabricating for semiconductor device with landing plug |
| CN106356295A (en) * | 2015-07-16 | 2017-01-25 | 中芯国际集成电路制造(上海)有限公司 | Chemical mechanical polishing method of interlayer dielectric layer, and device and electronic equipment with interlayer dielectric layer |
| CN106356300A (en) * | 2015-07-16 | 2017-01-25 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor apparatus and manufacturing method thereof and electronic device |
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