KR20010082842A - Liquid crystal display - Google Patents

Abstract

PURPOSE: A liquid crystal display is to secure nonuniformity of a large scaled liquid crystal display device using a fluidic self assembly (FSA) technology and improve a yield of the device. CONSTITUTION: A switching area and a pixel area are defined in a substrate. The substrate includes a groove in which a plurality of incline planes are formed. A nano block(200) is packaged in the groove and has side planes corresponding to the incline planes. At least one switching element and a plurality of pads are formed on the top face. The plurality of pads applies a signal to respective switching elements. A gate interconnection(150) crossing across the nano block horizontally is in contact with the first pad of the nano block. The first and the second data interconnections(160a,160b) crossing across the nano block vertically are in contact with the second and the third pads. A connecting interconnection(164) is formed in a discontinuous portion of the first and the second data interconnections. A pixel electrode(170) formed in the pixel area is in contact with the fourth pad.

Description

Liquid crystal display

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device, and more particularly, to a large area liquid crystal display device manufactured by using a fluid self assembly (FSA) technique in manufacturing a large area liquid crystal display device.

In general, the driving principle of the liquid crystal display device uses the optical anisotropy and polarization of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Accordingly, when the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal due to optical anisotropy to express image information.

Currently, thin film transistors fabricated using semiconductor processes and active matrix LCDs (AM-LCDs) in which pixel electrodes connected to the thin film transistors are arranged in a matrix manner have the highest resolution and moving picture performance. I am getting it.

In general, the structure of a liquid crystal panel, which is a basic component of a liquid crystal display, is as follows.

1 is a cross-sectional view showing a cross section of a general liquid crystal panel.

In the liquid crystal panel 20, two substrates 2 and 4 having various kinds of elements are formed to correspond to each other, and the liquid crystal layer 10 is interposed between the two substrates 2 and 4. have.

The liquid crystal panel 20 includes an upper substrate 4 having a color filter representing a color and a lower substrate 2 having a switching circuit capable of converting a molecular arrangement direction of the liquid crystal layer 10.

The upper substrate 4 includes a color filter layer 8 for implementing colors and a common electrode 12 covering the color filter layer 8. The common electrode 12 serves as one electrode for applying a voltage to the liquid crystal 10. The lower substrate 2 has a thin film transistor S serving as a switching function and a pixel electrode 14 serving as an electrode for receiving a signal from the thin film transistor S and applying a voltage to the liquid crystal 10. It is composed of

The portion where the pixel electrode 14 is formed is called the pixel portion P. FIG.

In order to prevent leakage of the liquid crystal 10 injected between the upper substrate 4 and the lower substrate 2, sealants (sealant) is formed at the edges of the upper substrate 4 and the lower substrate 2. It is sealed with).

The operation and configuration of the lower substrate 2 will be described in detail with reference to FIG. 2, which shows a plan view of the lower substrate 2 shown in FIG. 1.

The pixel electrode 14 is formed on the lower substrate 2, and the data line 24 and the gate line 22 are formed in the vertical and horizontal alignment directions of the pixel electrode 14, respectively.

In the active matrix liquid crystal display device, a thin film transistor S, which is a switching element for applying a voltage to the pixel electrode 14, is formed at one portion of the pixel electrode 14. The thin film transistor S includes a gate electrode 26, source and drain electrodes 28 and 30, and the gate electrode 26 is connected to the gate wiring 22, and the source electrode 28 Is connected to the data line 24.

In addition, the drain electrode 30 is electrically connected to the pixel electrode 14 through a contact hole (not shown).

The operation of the active matrix liquid crystal display device described above is as follows.

When a voltage is applied to the gate electrode 26 of the switching thin film transistor, the data signal is applied to the pixel electrode 14, and when the signal is not applied to the gate electrode 26, the data signal is applied to the pixel electrode 14. It doesn't work.

In general, the manufacturing process of the lower substrate is often determined by what material is used for each device to be made or designed according to the specification.

For example, in the past, the small liquid crystal display was not a problem, but in the case of a large area of 18 inches or more and a high resolution (eg SXGA, UXGA, etc.) liquid crystal display, the material used for the gate wiring and the data wiring is inherent The resistance value is an important factor in determining the superiority of the image quality. Therefore, in the case of a large area / high resolution liquid crystal display device, it is preferable to use a metal having a low resistance such as aluminum or an aluminum alloy as the material of the gate wiring and the data wiring.

Hereinafter, a manufacturing process of a conventional active matrix liquid crystal display will be described in detail with reference to FIGS. 3A to 3E.

In general, the structure of a thin film transistor used in a liquid crystal display is an inverted staggered structure. This is because the structure is the simplest and the performance is excellent.

In addition, the reverse staggered thin film transistor is divided into a back channel etch (EB) and an etch stopper (ES) according to a method of forming a channel portion, and a back channel etch type structure having a simple manufacturing process. The manufacturing process of the liquid crystal display element to which is applied is demonstrated.

First, cleaning is performed to remove foreign matters or organic substances on the substrate 1 and to improve the adhesion between the metal thin film of the gate material to be deposited and the glass substrate, and then the metal film is deposited by sputtering.

3A is a step of forming a gate electrode 30 and a storage electrode 32 by patterning with a first mask after the deposition of the metal film.

The metal used for the gate electrode 30, which is important for the operation of the active matrix liquid crystal display, is mainly composed of aluminum having low resistance to reduce the RC delay, but pure aluminum has low chemical resistance and subsequent high temperature. In the case of aluminum wiring, it is used in the form of an alloy or a laminated structure is applied because it causes a wiring defect problem due to the formation of a hillock in the process.

After the gate electrode 30 and the storage electrode 32 are formed, a gate insulating film 34 is deposited over the top and the entire exposed substrate. In addition, amorphous silicon (a-Si: H), which is a semiconductor material, and amorphous silicon (n ⁺ a-Si: H), which contains impurities, are sequentially deposited on the gate insulating layer 34.

After deposition of the semiconductor material, a pattern is formed with a second mask to form an active layer 36 and an ohmic contact layer 38 having the same size as the active layer (FIG. 3B).

The ohmic contact layer 38 is intended to reduce contact resistance between a metal layer to be formed later and the active layer 36.

The process illustrated in FIG. 3C is a process of depositing a transparent conducting oxide (TCO) and patterning it with a third mask to form the pixel electrode 40. As the transparent conductive material, indium tin oxide (ITO) having excellent light transmittance is mainly used.

The pixel electrode 40 is configured to overlap with the storage electrode 32 to form a storage capacitor together with the storage electrode 32.

Thereafter, as shown in FIG. 3D, a metal layer is deposited and patterned with a fourth mask to form a source electrode 42 and a drain electrode 44. The drain electrode 44 is configured to contact the pixel electrode 40 at a predetermined position. The source and drain electrodes 42 and 44 use a single metal such as chromium (Cr) or molybdenum (Mo).

The ohmic contact layer existing between the source electrode 42 and the drain electrode 44 is removed using the source and drain electrodes 42 and 44 as a mask. If the ohmic contact layer existing between the source electrode 42 and the drain electrode 44 is not removed, serious problems may occur in the electrical characteristics of the thin film transistor S, and a great problem may occur in performance.

Careful attention is required to remove the ohmic contact layer 38. When the ohmic contact layer 38 is actually etched, there is no etching selectivity with the active layer 36 formed thereunder, so that the active layer 36 is overetched by about 50 nm. The etching uniformity is a thin film transistor ( Directly affect the characteristics of S).

Finally, as shown in FIG. 3E, an insulating film is deposited and patterned with a fifth mask to form a protective film 46 to protect the active layer 36.

The passivation layer 46 may adversely affect the characteristics of the thin film transistor due to the unstable energy state of the active layer 36 and the residual material generated during etching, so that the inorganic silicon nitride layer (SiN _x ) or silicon oxide layer (SiO ₂ ) or the like may be adversely affected. It is formed of organic BCB (Benzocyclobutene).

In addition, the passivation layer 46 may have high light transmittance, moisture resistance, and durability in order to protect the channel region and the main portions of the pixel region P of the thin film transistor S from moisture or scratch resistance defects that may occur during subsequent processes. This material is deposited.

By the above-described process, the thin film transistor substrate of the liquid crystal display device is completed.

As described above, in the case of the conventional liquid crystal display device, an insulating film and an active layer process performed at a high temperature (about 300 ° C. or more) are required in order to manufacture a lower plate, which is a thin film transistor substrate. Deformation may occur. Therefore, when forming the thin film transistor, there is a disadvantage that the deterioration and characteristics of the device due to miss-alignment may occur.

The above phenomenon (problem of thermal contraction / expansion of the substrate) is intensified as the size of the substrate 1 increases.

In other words, the thin film transistor is formed as a result of repeating the processes of deposition, photolithography, and etching for each component (gate electrode, gate insulating film, active layer, etc.) several times. Many of these repetitive processes are subject to various conditions that can cause short circuits and short circuits in the wiring, and take into account a number of risks such as distortion of the substrate and defects of the device during such complex processes. do.

In addition, amorphous silicon, which is currently used as an active layer of a thin film transistor, has a problem in that it is applied to a liquid crystal display having a large area due to its electrical characteristics (mobility of about 1 cm ² / Vs). That is, since the mobility is remarkably small, when the amorphous silicon is used as a switching element of a large-area liquid crystal display (area of about 20 "or larger), there is a disadvantage in that image quality such as residual image may be degraded.

In addition, when manufacturing a large-area liquid crystal display by the conventional technology, there is a problem that the cost of the product increases because expensive CVD equipment for the deposition of the semiconductor thin film must be introduced separately.

SUMMARY OF THE INVENTION In order to solve the above problems, an object of the present invention is to provide a large-area liquid crystal display device which prevents deterioration of image quality and is easy to manufacture.

1 is a cross-sectional view showing a cross section of a general liquid crystal display.

2 is a plan view illustrating a plane of a general liquid crystal display;

FIG. 3 is a view illustrating a manufacturing process of a cross section taken along cut line III-III of FIG. 2.

4 is a schematic cross-sectional view of a nanoblock integrated with a switching device according to the present invention.

5 is a cross-sectional view of a switching device embedded in a nanoblock according to the present invention.

6 illustrates an equivalent circuit of a switching element integrated in a nanoblock.

Figure 7 is a view showing a cross section of the interior grooves are to be built nanoblocks according to the present invention.

8 is a plan view of a liquid crystal display according to the present invention;

FIG. 9 is a cross-sectional view taken along the line VII-VII of FIG. 8. FIG.

FIG. 10 is a cross-sectional view taken along the line VII-VII of FIG. 8. FIG.

<Explanation of symbols for the main parts of the drawings>

150: gate wiring 160a, 160b, 160c: data wiring

200: nanoblock 100: thin film transistor

300: internal groove 164: interconnection wiring

In order to achieve the above object, in the present invention, a switching region and a pixel region are defined, the substrate having a plurality of inclined grooves are formed in the switching region symmetrical with each other; A nanoblock mounted in the internal groove and having a side surface corresponding to an inclined surface of the internal groove, and having at least one switching element on the upper surface and a plurality of pads for applying signals to each switching element; A gate wiring crossing the nanoblock in a horizontal direction and in contact with the first pad of the nanoblock; 1, 2 data lines traversing the nanoblocks in a longitudinal direction, discontinuously formed in the vicinity of the nanoblocks around the gate lines, and in contact with the second and third pads of the nanoblocks, respectively; An interconnection wiring formed in a discontinuous portion of the first and second data wires and in common contact with the first and second data wires; An array substrate for a liquid crystal display device formed in the pixel area and in contact with a fourth pad formed in the nanoblock and including a pixel electrode of the same material as the interconnection line is provided.

In addition, the present invention is a substrate with a built-in groove having an inclined side; A nanoblock formed in the internal groove and having at least one switching element formed thereon and a plurality of pads configured to apply a signal to the switching element; A first passivation layer formed on the substrate on which the nanoblocks are formed, and having a contact hole through which each pad of the nanoblocks is exposed; A first and a second pad formed on the first passivation layer and extending discontinuously in a portion where the nanoblock is formed, and contacting the first and second pads exposed through the first and second contact holes formed on the first passivation layer; Data wiring; A second passivation layer formed over the entirety of the first and second data wires and the substrate, and having contact holes exposing portions of the first and second data wires of the portion where the nanoblocks are formed; An interconnection interconnection formed on the second passivation layer of the portion in which the first and second data interconnections are formed discontinuously and simultaneously contacting the first and second data interconnections exposed by contact holes formed on the second passivation layer, respectively. An array substrate for a liquid crystal display device is provided.

And, in the present invention, the substrate is formed with a built-in groove having an inclined side; A nanoblock seated in the internal groove, in which at least one switching element is integrated, and having a plurality of pads connected to each switching element; First wirings discontinuously extending in one direction in the vicinity of the nanoblocks and contacting the first and second pads of the nanoblocks at portions formed on one side and the other side of the nanoblocks; A second wiring crossing the nanoblock in another direction and in contact with a third pad of the nanoblock; A pixel electrode in contact with the fourth pad of the nanoblock; An array for a liquid crystal display device including an interconnection line extending in the same direction as the first line in a discontinuous portion of the first line and simultaneously contacting the first line on one side and the other side with respect to the nanoblock. Provide a substrate.

Hereinafter, with reference to the accompanying drawings will be described in detail the configuration of the present invention.

Compared with the conventional liquid crystal display device, the biggest feature of the liquid crystal display device according to the present invention is that the switching device is manufactured in advance through a separate manufacturing process, and the prefabricated switching device is a device self-dispersing technology (FSA). It will be embedded in the substrate through.

Here, the switching device manufactured separately is called nanoblock because its size is very fine, such as several tens of micrometers. The nanoblocks are formed by forming switching elements on a semiconductor wafer and later cutting them individually.

First, the nanoblocks used as the switching element will be described.

4 is a cross-sectional view showing a cross section of the nanoblock 200 according to the present invention. The nanoblock 200 includes a plurality of switching elements (thin film transistors) 100 and has a trapezoidal shape.

The thin film transistor 100 is formed on the wafer 50, and a detailed cross-sectional structure thereof will be described with reference to FIG. 5.

FIG. 5 is a cross-sectional view illustrating a cross-sectional structure of a thin film transistor formed in the nanoblock 200, and fabrication is performed on a semiconductor wafer 50.

The thin film transistor 100 illustrated in FIG. 5 is generally referred to as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and the configuration thereof is as follows.

First, an impurity semiconductor region 60 is positioned on the wafer 50, and an insulating film 52 through which a portion of the impurity region 60 is exposed is formed on the wafer 50.

In addition, source and drain electrodes 56 and 58 in contact with the impurity region 60 are disposed on the insulating layer 52, and a gate electrode 54 is disposed between the source and drain electrodes 56 and 58. Is formed.

The semiconductor wafer 50 may be formed of single crystal silicon (C-Si), gallium-aside (GaAs), or the like, and the impurity region 60 may include impurities (group 3 on the element periodic table) of the semiconductor wafer 50. It is formed by injecting boron (B) or phosphorus (P), which is an element of Groups 5 to 5.

FIG. 6 is a circuit diagram illustrating a circuit of a portion in which the thin film transistor 100 of the nanoblock 200 is formed, and four thin film transistors 100 are formed in symmetry of up / down / left / right.

Each thin film transistor 100 includes a gate electrode 54 and source and drain electrodes 56 and 58, and the gate electrode 54 is in contact with two gate pads 54a and 54b. The pads 54a and 54b take a symmetrical structure with each other.

In addition, the source electrode 56 is in contact with the data pad 56a, and the drain electrode 58 is in contact with the drain pad 58a.

A storage capacitor 70 having the drain pad 58a as one electrode is formed, and the other electrode of the storage capacitor 70 is a common electrode pad 72.

Here, the data pad 56a is commonly connected to the remaining three source electrodes 56, and may be formed separately. That is, although four source electrodes 56 are connected to one data pad 56a in the circuit diagram of the nanoblock 200 shown in FIG. 6, the source electrodes may be formed to be connected to the four data pads, respectively. Could be.

In addition, the common electrode pad 70 is in common contact with a plurality of formed storage capacitors.

The nanoblock 200 described above includes four thin film transistors 100 and a storage capacitor connected to the data pad 56a and the drain pad 58a for applying a signal to the source electrode 56 of each thin film transistor 100. 70 and a common electrode pad 72 commonly connected to the storage capacitor 70.

As described above, according to the circuit diagram of the nanoblock shown in FIG. 6, each of the four thin film transistors 100 is connected to one data pad 56a and each source electrode 56 is connected to the data pad 56a. When a signal is applied, each of the thin film transistors 100 operates individually according to the application of the signal of each gate electrode 54.

Meanwhile, an FSA technology for disposing a nanoblock on which a plurality of thin film transistors and storage capacitors are formed on a substrate will be described.

7 is a cross-sectional view illustrating a cross section of the substrate 1 on which the nanoblocks 200 are to be seated.

The substrate 1 is prepared in order to arrange the nanoblock 200 as a switching element, and the portion in which the nanoblock 200 is to be disposed is etched by a predetermined method, so that the nanoblock 200 is seated therein. 300). At this time, the built-in groove 300 is made in accordance with the bottom shape of the nanoblock 200 (that is, the length thereof is smaller in the trapezoidal nanoblock).

The substrate thus prepared is immersed in a fluid solution containing a surfactant, and the nanoblock 200 is dispersed on the substrate immersed in the fluid by a predetermined method.

At this time, the nanoblock 200 flows along the fluid to be seated in the internal groove 300, which is an etch groove of the substrate 1, thereby forming a switching device (ie, a nanoblock) on the substrate 1. do.

A technology for seating the nanoblock 200, which is a switching device manufactured separately as described above, in the internal groove 300 formed in the substrate 1 is called a device self-dispersion technology (FSA). The device dispersing technique is disclosed in US Pat. No. 5,904,545.

In the manufacturing process of the conventional liquid crystal display device, the manufacturing process of the thin film transistor, which is a switching element, and the formation process of the pixel electrode are performed on the same substrate in the lower plate where the pixel electrode is formed. do.

Fabrication of the nanoblock as the switching device according to the present invention is a three-terminal device, such as a typical amorphous silicon thin film transistor, the role of which is the same as the switching of the amorphous silicon thin film transistor, the electrical characteristics of a wafer of single crystal silicon or gallium-asnade Excellent because it is prepared in a phase.

The above-described FSA technology does not control the direction of the nanoblock 200.

Therefore, as shown in FIG. 6, which is a circuit diagram of the nanoblock 200, the four thin film transistors 100 are designed to have a symmetrical structure, and a data pad and a gate pad that apply signals to the thin film transistors, respectively. The terminals of the back also have a symmetrical structure.

In addition, the circuit configuration of the nanoblock 200 can be changed to suit the characteristics of the liquid crystal display device, it is not limited to the circuit diagram shown in FIG.

The following description will be directed to a method of manufacturing a liquid crystal display device through the nanoblock 200 and the device diffusion technology (FSA) using the same.

8 is a plan view illustrating a plane corresponding to one pixel part of the liquid crystal display according to the exemplary embodiment of the present invention.

Referring to FIG. 8, a plurality of gate lines 150 are formed in the horizontal direction, and a plurality of data lines 160a, 160b, and 160c are formed in the vertical direction.

In addition, the nano block 200 is positioned at an intersection where the gate line 150 and the data lines 160a, 160b, and 160c cross each other.

In addition, a gate wiring contact hole 152 is formed in the gate wiring 150 adjacent to the nanoblock 200 to be connected to the gate pad 156 of a thin film transistor (not shown) formed in the nanoblock 200.

In addition, a data wiring contact hole 162 is formed at the end of the direction in which the data wires 160a, 160b, and 160c adjacent to the nanoblocks 200 extend to form a drain pad 163 of the nanoblocks 200. Connected with

The first data line 160a is connected to each other by an adjacent second data line 160b and an internally formed line in the nanoblock 200.

Meanwhile, as shown in FIG. 8, in the liquid crystal display according to the present invention, each data line 160a, 160b, 160c is discontinuously formed in the vicinity of the nanoblock 200. This is because the gate wiring 150 and the data wirings 160a, 160b, and 160c are formed in the same process, so that any one of the gate wiring 150 or the data wirings 160a, 160b, and 160c is discontinuously formed. In this embodiment, the data wires 160a, 160b, and 160c are formed discontinuously.

In addition, a drain pad 166 connected to a drain electrode (not shown) of the thin film transistor is formed in the nanoblock 200, and a pixel electrode 170 in contact with the drain pad 166 is formed.

In addition, interconnection lines 164 are formed on top of the data lines 160a, 160b, 160c that are discontinuously extended in the vicinity of the nanoblocks 200. It is in contact with the wirings 160a, 160b, and 160c.

That is, the first data line 160a and the second data line 160b are connected to each other by an interconnection line 164 formed on the nanoblock 200.

The function of the interconnection wiring 164 is discontinuously in the internal groove (P part of FIG. 8) of the unseated portion when the nanoblock 200 is seated in the internal groove by the device scattering technology (FSA). The formed data wires 160a, 160b, and 160c are formed to compensate for the disadvantage that they do not conduct with each other. That is, the interconnection wiring 164 serves to repair the defects of the data lines 160a, 160b, and 160c formed discontinuously.

Meanwhile, in the exemplary embodiment of the present invention, the data lines are formed discontinuously. However, when the gate lines are discontinuously formed, the interconnection lines may be commonly connected to each of the gate lines formed discontinuously.

As described above, the liquid crystal display according to the present invention has the advantage that it can be applied to a large area liquid crystal display by adopting the nano block 200 manufactured by forming a thin film transistor used as a switching element in the form of a block.

9 is a cross-sectional view taken along the cutting line 선 -Ⅸ of FIG. 8, wherein an internal groove (not shown) is formed in the substrate 1, and a plurality of switching elements are integrated in the internal groove. ) Is formed, and the first planarization layer 172 for planarizing the substrate 1 is prevented from being detached from the substrate 1 and the nanoblock 200 is mounted on the substrate ( 1) is formed on.

The first planarization layer 172 may include a source pad 163 and a gate contact hole 162 to which a source pad 163 and a gate pad 156 are exposed, for applying a signal to a switching element formed in the nanoblock 200. Has 152.

The data line 160a and the gate line 150 are formed in contact with the source and gate pads 163 and 156 exposed through the source and gate contact holes 162 and 152 on the first planarization layer 172. .

In addition, a second planarization layer 174 is formed on the data and gate lines 160a and 150, and a pixel electrode 170 is formed on the second planarization layer 174.

The pixel electrode 170 is made of a transparent conductive metal such as ITO or IZO.

Although not illustrated in FIG. 9, the pixel electrode 170 is in contact with the drain pad formed in the nanoblock 200.

As the first and second planarization films, an organic insulating film having excellent planarization rate is used, and BCB (benzocyclobutene), acryl (acryl), and the like are used.

Meanwhile, an interconnection line 164 of the same material as that of the pixel electrode 170 is formed on the second planarization layer 174 on the nanoblock 200, and the structure and function of the interconnection line 164 may be reduced. This will be described in detail with reference to FIG. 10.

As described above, in the manufacturing process of the liquid crystal display according to the present invention, since the deposition of the semiconductor material (mainly amorphous silicon) and the deposition of the insulating film (mainly silicon nitride film) for forming the switching element on the substrate are excluded, It is possible to manufacture the liquid crystal display at the process temperature.

In addition, since the process temperature of the array substrate to which the device spreading technique is applied is performed at a process temperature of up to 250 ^° , it is possible to prevent shrinkage deformation of the substrate due to heat, and misalignment in the exposure machine due to deformation of the substrate during the photolithography process. There is no change in the characteristics of the device.

In addition, unlike the conventional manufacturing process of the liquid crystal display device, the manufacturing process and the wiring process of the switching element can be produced by disadvantageous, it is possible to obtain the effect of simplifying the production equipment and cost reduction.

In addition, by manufacturing a large amount of switching elements on a small area semiconductor wafer, it is possible to ensure uniform electrical characteristics of the switching elements.

In particular, when manufacturing a liquid crystal display device by the device scattering technology according to the present invention it is possible to ensure uniformity in a large area liquid crystal display device.

As described above, in the device dispersing technology (FSA) for seating the nanoblock integrated with the switching element in the internal groove, the nanoblock may not be formed in the internal groove 100% accurately.

That is, as can be seen in the cross-sectional view of the liquid crystal display using the FSA technology corresponding to the plurality of pixel parts shown in FIG. 10, a nanoblock may not be formed in the internal grooves.

FIG. 10 is a cross-sectional view taken along the cutting line Ⅹ-Ⅹ of FIG. 8, and illustrates a cross section of a portion P in which mounting failure occurs when the nanoblock is seated on a substrate on which an internal groove is formed through FSA technology. Drawing.

As shown in the drawing, when the nanoblock is not seated on the substrate 1 having the internal groove 300 formed through the FSA technology, the data wiring formed thereon is disconnected and proceeds to the predecessor. . This is because the data wiring is discontinuous at the portion where the nanoblock is formed, and adopts a method of applying a signal to the adjacent data wiring through the wiring formed in the nanoblock.

Therefore, when the nanoblock is not formed, the result is that the data signal applied through the second data line 160b is not transmitted to the third data line 160c.

Due to the above-described problems, in the present invention, a part of the second and third data wires of the internal groove 300 is exposed to the second planarization film 174 formed on the data wires 160b and 160c, respectively. When the holes are formed and the pixel electrodes are formed, the mutual lead wires 164 are simultaneously formed in contact with the second and third data wires 160b and 160c.

As described above, the mutual lead wires 164 contacting the second and third data wires 160b and 160c at the same time can prevent the nanoblocks from proceeding to the predecessor even when a mounting failure of the nanoblocks occurs.

On the other hand, the gate wiring 150 is formed in the middle portion of the second and third data wirings 160b and 160c.

When manufacturing a liquid crystal display according to the embodiment of the present invention described above has the following features.

First, since a process of depositing a semiconductor material (mostly amorphous silicon) and an insulating film (mostly silicon nitride film) for forming a switching element on a substrate is excluded, there is an advantage that a liquid crystal display device can be manufactured at a low process temperature. .

Second, the process temperature of the array substrate to which the device scattering technology is applied is performed at a process temperature of up to 250 ^o to prevent shrinkage deformation of the substrate due to heat. Since there is no characteristic change of the device, there is an advantage that the production yield of the liquid crystal display device is improved.

Third, unlike the existing manufacturing process of the liquid crystal display device, the manufacturing process of the switching element and the wiring process can be manufactured separately, which has the advantage of simplifying the production equipment and reducing the cost.

Fourth, by manufacturing a large number of switching elements in a small area semiconductor wafer, there is an advantage that can ensure a uniform electrical characteristics of the switching element.

Fifth, when the nanoblock is mounted in the internal groove through the device scattering technology, there is an advantage that can prevent the pre-defect due to the mounting failure through the interconnection wiring.

Claims (8)

A substrate having a built-in groove in which a switching region and a pixel region are defined and in which a plurality of inclined surfaces are symmetrical to each other; A nanoblock mounted in the internal groove and having a side surface corresponding to an inclined surface of the internal groove, and having at least one switching element on the upper surface and a plurality of pads for applying signals to each switching element; A gate wiring crossing the nanoblock in a horizontal direction and in contact with the first pad of the nanoblock; 1, 2 data lines traversing the nanoblocks in a longitudinal direction, discontinuously formed in the vicinity of the nanoblocks around the gate lines, and in contact with the second and third pads of the nanoblocks, respectively; An interconnection wiring formed in a discontinuous portion of the first and second data wires and in common contact with the first and second data wires; A pixel electrode formed in the pixel region and in contact with a fourth pad formed in the nanoblock, the same material as the interconnection wiring Array substrate for a liquid crystal display device comprising a. The method according to claim 1, And the nanoblocks are polygonal in symmetry with respect to each other in plan view. The method according to claim 1, And wherein the interconnection wiring is a material selected from the group consisting of ITO and IZO. A substrate having a built-in groove having an inclined side surface; A nanoblock formed in the internal groove and having at least one switching element formed thereon and a plurality of pads configured to apply a signal to the switching element; A first passivation layer formed on the substrate on which the nanoblocks are formed, and having a contact hole through which each pad of the nanoblocks is exposed; A first and a second pad formed on the first passivation layer and extending discontinuously in a portion where the nanoblock is formed, and contacting the first and second pads exposed through the first and second contact holes formed on the first passivation layer; Data wiring; A second passivation layer formed over the entirety of the first and second data wires and the substrate, and having contact holes exposing portions of the first and second data wires of the portion where the nanoblocks are formed; An interconnection interconnection formed on the second passivation layer of the portion where the first and second data interconnections are formed discontinuously and simultaneously contacting the first and second data interconnections exposed by contact holes formed on the second passivation layer, respectively. Array substrate for a liquid crystal display device comprising a. The method according to claim 4, And the first and second passivation layers are materials selected from a group consisting of BCB and acryl. The method according to claim 4, And wherein the interconnection wiring is a material selected from the group consisting of ITO and IZO. The method according to claim 4, And the nanoblocks have a polygonal shape symmetric to each other in plan view. A substrate having a built-in groove having an inclined side surface; A nanoblock seated in the internal groove, in which at least one switching element is integrated, and having a plurality of pads connected to each switching element; First wirings discontinuously extending in one direction in the vicinity of the nanoblocks and contacting the first and second pads of the nanoblocks at portions formed on one side and the other side of the nanoblocks; A second wiring crossing the nanoblock in another direction and in contact with a third pad of the nanoblock; A pixel electrode in contact with the fourth pad of the nanoblock; An interconnection line extending in the same direction as the first line in a discontinuous portion of the first line and simultaneously contacting the first line on one side and the other side about the nanoblock; Array substrate for a liquid crystal display device comprising a.