KR20010082844A - Liquid crystal display - Google Patents

Abstract

PURPOSE: A liquid crystal display is to enable to manufacture the display at a low temperature by eliminating a deposition process of a semiconductor material and an insulating layer used to form a switching element on a substrate. CONSTITUTION: A substrate includes a pixel area and a switching area. The pixel area is arranged in an nxm matrix form, and the switching area is disposed at a region in which four pixel areas are adjacent. A nano block is formed on respective switching areas in a rectangular shape. Four thin film transistors having a gate electrode and a source/drain electrode are integrated in the nano block. Each thin film transistor has a gate and a source/drain pad and is formed symmetrically on four faces. The m numbers of data interconnections(160) for applying a signal to each nano block are formed on boundaries of a column direction of each pixel area. The n numbers of gate interconnections(150) for commonly applying a signal to N-th and (N+1)th nano blocks are formed on boundaries of a row direction of each pixel area. A pixel electrode(170) formed on each pixel area commonly receives a signal from the N-th and (N+1)th nano blocks.

Description

Liquid crystal display

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device, and more particularly, to a large area liquid crystal display device manufactured by using a fluid self assembly (FSA) technique in manufacturing a large area liquid crystal display device.

In general, the driving principle of the liquid crystal display device uses the optical anisotropy and polarization of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Accordingly, when the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal due to optical anisotropy to express image information.

Currently, thin film transistors fabricated using semiconductor processes and active matrix LCDs (AM-LCDs) in which pixel electrodes connected to the thin film transistors are arranged in a matrix manner have the highest resolution and moving picture performance. I am getting it.

In general, the structure of a liquid crystal panel, which is a basic component of a liquid crystal display, will be described.

1 is a cross-sectional view showing a cross section of a general liquid crystal panel.

In the liquid crystal panel 20, two substrates 2 and 4 having various kinds of elements are formed to correspond to each other, and the liquid crystal layer 10 is interposed between the two substrates 2 and 4. have.

The liquid crystal panel 20 includes an upper substrate 4 having a color filter representing a color and a lower substrate 2 having a switching circuit capable of converting a molecular arrangement direction of the liquid crystal layer 10.

The upper substrate 4 includes a color filter layer 8 for implementing colors and a common electrode 12 covering the color filter layer 8. The common electrode 12 serves as one electrode for applying a voltage to the liquid crystal 10. The lower substrate 2 has a thin film transistor S serving as a switching function and a pixel electrode 14 serving as an electrode for receiving a signal from the thin film transistor S and applying a voltage to the liquid crystal 10. It is composed of

The portion where the pixel electrode 14 is formed is called the pixel portion P. FIG.

In order to prevent leakage of the liquid crystal 10 injected between the upper substrate 4 and the lower substrate 2, sealants (sealant) is formed at the edges of the upper substrate 4 and the lower substrate 2. It is sealed with).

The operation and configuration of the lower substrate 2 will be described in detail with reference to FIG. 2, which shows a plan view of the lower substrate 2 shown in FIG. 1.

The pixel electrode 14 is formed on the lower substrate 2, and the data line 24 and the gate line 22 are formed in the vertical and horizontal alignment directions of the pixel electrode 14, respectively.

In the active matrix liquid crystal display device, a thin film transistor S, which is a switching element for applying a voltage to the pixel electrode 14, is formed at one portion of the pixel electrode 14. The thin film transistor S includes a gate electrode 26, source and drain electrodes 28 and 30, and the gate electrode 26 is connected to the gate wiring 22, and the source electrode 28 Is connected to the data line 24.

In addition, the drain electrode 30 is electrically connected to the pixel electrode 14 through a contact hole (not shown).

The operation of the active matrix liquid crystal display device described above is as follows.

When a voltage is applied to the gate electrode 26 of the switching thin film transistor, the data signal is applied to the pixel electrode 14, and when the signal is not applied to the gate electrode 26, the data signal is applied to the pixel electrode 14. It doesn't work.

In general, the manufacturing process of the lower substrate is often determined by what material is used for each device to be made or designed according to the specification.

For example, in the past, the small liquid crystal display was not a problem, but in the case of a large area of 18 inches or more and a high resolution (eg SXGA, UXGA, etc.) liquid crystal display, the material used for the gate wiring and the data wiring is inherent The resistance value is an important factor in determining the superiority of the image quality. Therefore, in the case of a large area / high resolution liquid crystal display device, it is preferable to use a metal having low resistance such as aluminum or an aluminum alloy as the material of the gate wiring and the data wiring.

Hereinafter, a manufacturing process of a conventional active matrix liquid crystal display will be described in detail with reference to FIGS. 3A to 3E.

In general, the structure of a thin film transistor used in a liquid crystal display is an inverted staggered structure. This is because the structure is the simplest and the performance is excellent.

In addition, the reverse staggered thin film transistor is divided into a back channel etch (EB) and an etch stopper (ES) according to a method of forming a channel portion, and a back channel etch type structure having a simple manufacturing process. The manufacturing process of the liquid crystal display element to which is applied is demonstrated.

First, cleaning is performed to remove foreign matters or organic substances on the substrate 1 and to improve the adhesion between the metal thin film of the gate material to be deposited and the glass substrate, and then the metal film is deposited by sputtering.

3A is a step of forming a gate electrode 30 and a storage electrode 32 by patterning with a first mask after the metal film deposition.

The metal used for the gate electrode 30, which is important for the operation of the active matrix liquid crystal display, is mainly composed of aluminum having low resistance to reduce the RC delay, but pure aluminum has low chemical resistance and subsequent high temperature. In the case of aluminum wiring, it is used in the form of an alloy or a laminated structure is applied because it causes a wiring defect problem due to the formation of a hillock in the process.

After the gate electrode 30 and the storage electrode 32 are formed, a gate insulating film 34 is deposited over the top and the entire exposed substrate. In addition, amorphous silicon (a-Si: H), which is a semiconductor material, and amorphous silicon (n ⁺ a-Si: H), which contains impurities, are sequentially deposited on the gate insulating layer 34.

After deposition of the semiconductor material, a pattern is formed with a second mask to form an active layer 36 and an ohmic contact layer 38 having the same size as the active layer (FIG. 3B).

The ohmic contact layer 38 is intended to reduce contact resistance between a metal layer to be formed later and the active layer 36.

The process illustrated in FIG. 3C is a process of depositing a transparent conducting oxide (TCO) and patterning it with a third mask to form the pixel electrode 40. As the transparent conductive material, indium tin oxide (ITO) having excellent light transmittance is mainly used.

The pixel electrode 40 is configured to overlap with the storage electrode 32 to form a storage capacitor together with the storage electrode 32.

Thereafter, as shown in FIG. 3D, a metal layer is deposited and patterned with a fourth mask to form a source electrode 42 and a drain electrode 44. The drain electrode 44 is configured to contact the pixel electrode 40 at a predetermined position. The source and drain electrodes 42 and 44 use a single metal such as chromium (Cr) or molybdenum (Mo).

The ohmic contact layer existing between the source electrode 42 and the drain electrode 44 is removed using the source and drain electrodes 42 and 44 as a mask. If the ohmic contact layer between the source electrode 42 and the drain electrode 44 is not removed, serious problems may occur in the electrical characteristics of the thin film transistor S, and a great problem may occur in performance.

Careful attention is required to remove the ohmic contact layer 38. When the ohmic contact layer 38 is actually etched, there is no etching selectivity with the active layer 36 formed thereunder, so that the active layer 36 is overetched by about 50 nm. The etching uniformity is a thin film transistor ( Directly affect the characteristics of S).

Finally, as shown in FIG. 3E, an insulating film is deposited and patterned with a fifth mask to form a protective film 46 to protect the active layer 36.

The passivation layer 46 may adversely affect the characteristics of the thin film transistor due to the unstable energy state of the active layer 36 and the residual material generated during etching, so that the inorganic silicon nitride layer (SiN _x ) or silicon oxide layer (SiO ₂ ) or the like may be adversely affected. It is formed of organic BCB (Benzocyclobutene).

In addition, the passivation layer 46 may have high light transmittance, moisture resistance, and durability in order to protect the channel region and the main portions of the pixel region P of the thin film transistor S from moisture or scratch resistance defects that may occur during subsequent processes. This material is deposited.

By the above-described process, the thin film transistor substrate of the liquid crystal display device is completed.

As described above, in the case of the conventional liquid crystal display device, an insulating film and an active layer process performed at a high temperature (about 300 ° C. or more) are required in order to manufacture a lower plate, which is a thin film transistor substrate. Deformation may occur. Therefore, when forming the thin film transistor, there is a disadvantage that the deterioration and characteristics of the device due to miss-alignment may occur.

The above phenomenon (problem of thermal contraction / expansion of the substrate) is intensified as the size of the substrate 1 increases.

In other words, the thin film transistor is formed as a result of repeating the processes of deposition, photolithography, and etching for each component (gate electrode, gate insulating film, active layer, etc.) several times. Many of these repetitive processes are subject to various conditions that can cause short circuits and short circuits in the wiring, and take into account a number of risks such as distortion of the substrate and defects of the device during such complex processes. do.

In addition, amorphous silicon, which is currently used as an active layer of a thin film transistor, has a problem in that it is applied to a liquid crystal display having a large area due to its electrical characteristics (mobility of about 1 cm ² / Vs). That is, since the mobility is remarkably small, when the amorphous silicon is used as a switching element of a large-area liquid crystal display (area of about 20 "or larger), there is a disadvantage in that image quality such as residual image may be degraded.

In addition, when manufacturing a large-area liquid crystal display by the conventional technology, there is a problem that the cost of the product increases because expensive CVD equipment for the deposition of the semiconductor thin film must be introduced separately.

SUMMARY OF THE INVENTION In order to solve the above problems, an object of the present invention is to provide a large-area liquid crystal display device which prevents deterioration of image quality and is easy to manufacture.

1 is a cross-sectional view showing a cross section of a general liquid crystal display.

2 is a plan view illustrating a plane of a general liquid crystal display;

FIG. 3 is a view illustrating a manufacturing process of a cross section taken along cut line III-III of FIG. 2.

4 is a schematic cross-sectional view of a nanoblock integrated with a switching device according to the present invention.

5 is a cross-sectional view of a switching device embedded in a nanoblock according to the present invention.

Figure 6 is a view showing a cross section of the interior grooves are to be built nanoblocks according to the present invention.

7 illustrates an equivalent circuit of a switching element integrated in a nanoblock.

8 is a plan view of a liquid crystal display according to the present invention;

<Explanation of symbols for the main parts of the drawings>

150: gate wiring 160: data wiring

200a, 200b: nanoblock 100: thin film transistor

170: pixel electrode

In order to achieve the above object, in the present invention, four transistors including a gate electrode, a source, and a drain electrode are integrated in a quadrangular shape having a substantially four plane in plan view, and each transistor includes a gate contacting each electrode. A switching element for a liquid crystal display device having a source and a drain pad and symmetrically formed on four surfaces thereof is provided.

In addition, in the present invention, a substrate in which a switching region is defined in an area in which n pieces in a horizontal direction and m pieces in a vertical direction are arranged in a matrix shape of n × m and an area adjacent to four pixel areas (n, m is positive essence); Four thin film transistors formed in each of the switching regions and having a quadrangular shape having substantially four planes in a planar manner include four thin film transistors including a gate electrode, a source and a drain electrode, each thin film transistor having a gate in contact with each electrode, Nanoblocks each having a source and a drain pad symmetrically formed on four surfaces; M data wires formed at a vertical boundary of each pixel area and applying a signal to each of the nanoblocks; N gate wirings formed at horizontal boundaries of each pixel region and commonly applying signals to N and N + 1th nanoblocks formed in the horizontal direction (where N is a positive integer); The present invention provides an array substrate for a liquid crystal display device including pixel electrodes formed in each pixel area and receiving a signal commonly applied to N and N + 1th nanoblocks.

Hereinafter, with reference to the accompanying drawings will be described in detail the configuration of the present invention.

Compared with the conventional liquid crystal display device, the biggest feature of the liquid crystal display device according to the present invention is that the switching device is manufactured in advance through a separate manufacturing process, and the prefabricated switching device is a device self-dispersing technology (FSA). It will be embedded in the substrate through.

Here, the switching device manufactured separately is called nanoblock because its size is very fine, such as several tens of micrometers. The nanoblocks are formed by forming switching elements on a semiconductor wafer and later cutting them individually.

First, the nanoblocks used as the switching element will be described.

4 is a cross-sectional view showing a cross section of the nanoblock 200 according to the present invention. The nanoblock 200 includes a plurality of switching elements (thin film transistors) 100 and has a trapezoidal shape.

The thin film transistor 100 is formed on the wafer 50, and a detailed cross-sectional structure thereof will be described with reference to FIG. 5.

FIG. 5 is a cross-sectional view illustrating a cross-sectional structure of a thin film transistor formed in the nanoblock 200, and fabrication is performed on a semiconductor wafer 50.

The thin film transistor 100 illustrated in FIG. 5 is generally referred to as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and the configuration thereof is as follows.

First, an impurity semiconductor region 60 is positioned on the wafer 50, and an insulating film 52 through which a portion of the impurity region 60 is exposed is formed on the wafer 50.

In addition, source and drain electrodes 56 and 58 in contact with the impurity region 60 are disposed on the insulating layer 52, and a gate electrode 54 is disposed between the source and drain electrodes 56 and 58. Is formed.

The semiconductor wafer 50 may be formed of single crystal silicon (C-Si), gallium-aside (GaAs), or the like, and the impurity region 60 may include impurities (group 3 on the element periodic table) of the semiconductor wafer 50. It is formed by injecting boron (B) or phosphorus (P), which is an element of Groups 5 to 5.

Meanwhile, an FSA technology for disposing a nanoblock on which a plurality of thin film transistors and storage capacitors are formed on a substrate will be described.

6 is a cross-sectional view illustrating a cross section of the substrate 1 on which the nanoblocks 200 are to be seated.

The substrate 1 is prepared in order to arrange the nanoblock 200 as a switching element, and the portion in which the nanoblock 200 is to be disposed is etched by a predetermined method, so that the nanoblock 200 is seated therein. 300). At this time, the built-in groove 300 is made to match the lower shape of the nanoblock 200 (that is, the length thereof is smaller in the trapezoidal nanoblock).

The substrate thus prepared is immersed in a fluid solution containing a surfactant, and the nanoblock 200 is dispersed on the substrate immersed in the fluid by a predetermined method.

At this time, the nanoblock 200 flows along the fluid to be seated in the internal groove 300, which is an etch groove of the substrate 1, thereby forming a switching device (ie, a nanoblock) on the substrate 1. do.

A technology for seating the nanoblock 200, which is a switching device manufactured separately as described above, in the internal groove 300 formed in the substrate 1 is called a device self-dispersion technology (FSA). The device dispersing technique is disclosed in US Pat. No. 5,904,545.

In the manufacturing process of the conventional liquid crystal display device, the manufacturing process of the thin film transistor, which is a switching element, and the formation process of the pixel electrode are performed on the same substrate in the lower plate where the pixel electrode is formed. do.

Fabrication of the nanoblock as the switching device according to the present invention is a three-terminal device, such as a typical amorphous silicon thin film transistor, the role of which is the same as the switching of the amorphous silicon thin film transistor, the electrical characteristics of a wafer of single crystal silicon or gallium-asnade Excellent because it is prepared in a phase.

The above-described FSA technology does not control the direction of the nanoblock 200.

Therefore, as shown in FIG. 7, which is a circuit diagram of the nanoblock 200, the four thin film transistors 100 are designed to have a symmetrical structure, and a data pad and a gate pad that apply signals to the thin film transistors, respectively. The terminals of the back also have a symmetrical structure.

FIG. 7 is a circuit diagram illustrating a circuit of a portion in which the thin film transistor 100 of the nanoblock 200 is formed, and four thin film transistors 100 are symmetrically formed up, down, left, and right. .

Each thin film transistor 100 includes a gate electrode 54 and source and drain electrodes 56 and 58, and the gate electrode 54 is in contact with two gate pads 54a and 54b. The pads 54a and 54b take a symmetrical structure with each other.

In addition, the source electrode 56 is in contact with the data pad 56a, and the drain electrode 45b is in contact with the drain pad 58a.

A storage capacitor 70 having the drain pad 58a as one electrode is formed, and the other electrode of the storage capacitor 70 is a common electrode pad 72.

Here, the data pad 56a is commonly connected to the remaining three source electrodes 56, and may be formed separately. That is, although four source electrodes 56 are connected to one data pad 56a in the circuit diagram of the nanoblock 200 shown in FIG. 7, the source electrodes may be formed to be connected to the four data pads, respectively. Could be.

In addition, the common electrode pad 70 is in common contact with a plurality of formed storage capacitors.

The nanoblock 200 described above includes four thin film transistors 100 and a storage capacitor connected to the data pad 56a and the drain pad 58a for applying a signal to the source electrode 56 of each thin film transistor 100. 70 and a common electrode pad 72 commonly connected to the storage capacitor 70.

As described above, according to the circuit diagram of the nanoblock shown in FIG. 7, each of the four thin film transistors 100 has one source pad 56 connected to one data pad 56a, and the data pad 56a. When a signal is applied to each of the thin film transistors 100, the thin film transistors 100 operate according to the application of the signals of the respective gate electrodes 54.

In addition, the circuit configuration of the nanoblock 200 can be changed to suit the characteristics of the liquid crystal display device, it is not limited to the circuit diagram shown in FIG.

The following description will be directed to the layout of a liquid crystal display using the nanoblock 200 described above.

8 is a plan view illustrating a plane corresponding to one pixel part of the liquid crystal display according to the exemplary embodiment of the present invention.

Referring to FIG. 8, nanoblocks 200a and 200b are formed as switching elements on a substrate (not shown).

The nanoblocks 200 have polygonal shapes symmetrical to each other, and in the present invention, the nanoblocks 200 will be described as having a rectangular shape. Here, the nanoblock 200 is seated in an internal groove (not shown) formed in a substrate (not shown), at least one thin film transistor is integrated, and a plurality of pads for applying a signal to the thin film transistor are formed. . For example, the pad may be a gate pad 202, a source pad 204, and a drain pad 206 connected to the gate electrode, the source electrode, and the drain electrode of the thin film transistor, respectively.

A plurality of data lines 160 are formed in the vertical direction, and the gate lines 150 are formed in the horizontal direction.

The gate wiring 150 is simultaneously connected to each of the nanoblocks 200a and 200b in the horizontal row. As described above, when the gate wiring is connected to two columns adjacent to the horizontal column in the same manner, the nanoblocks of the two columns receive the same gate signal to drive the same.

Here, the pixel electrode 170 is simultaneously connected to two nanoblocks 200a and 200b that take two columns, and even if the mounting failure occurs in any one of the nanoblocks by device scattering technology (FSA), the two nanoblocks The pixel electrode 170 which contacts the blocks 200a and 200b at the same time can be driven.

In other words, since the pixel electrode 170 receives signals simultaneously from the nanoblocks 200a and 200b formed at the upper and lower portions thereof, the nanoblocks 200a and 200b simultaneously contact the pixel electrodes 170. Even if any one of the nanoblocks 200a or 200b does not play a role as a switching element due to a mounting failure or a defect of an element, the pixel electrode 170 can be driven. In other words, each of the nanoblocks 200a or 200b drives two pixel electrodes formed at upper and lower portions thereof.

Here, each of the nanoblocks 200a and 200b is provided with a storage capacitor (see FIG. 7), so that a common electrode 180 for supplying power to the storage capacitor is connected to each of the nanoblocks 200a and 200b. It is.

The pixel electrode 170 is made of ITO, IZO, or the like, which is a substantially transparent conductive metal.

As described above, in the circuit structure of the nanoblock and the liquid crystal display device using the nanoblock, the pixel electrode is adjacent to the horizontal column even when the mounting failure occurs in the device scattering technology (FSA) for mounting the nanoblock on the substrate. Since the signals are simultaneously applied from the two nanoblocks, the incidence of defects is reduced.

When manufacturing a liquid crystal display according to the embodiment of the present invention described above has the following features.

First, since a process of depositing a semiconductor material (mostly amorphous silicon) and an insulating film (mostly silicon nitride film) for forming a switching element on a substrate is excluded, there is an advantage that a liquid crystal display device can be manufactured at a low process temperature. .

Second, the process temperature of the array substrate to which the device scattering technology is applied is performed at a process temperature of up to 250 ^o to prevent shrinkage deformation of the substrate due to heat, and to the misalignment in the exposure machine due to the deformation of the substrate during the photolithography process. Since there is no characteristic change of the device, there is an advantage that the production yield of the liquid crystal display device is improved.

Third, unlike the existing manufacturing process of the liquid crystal display device, the manufacturing process of the switching element and the wiring process can be manufactured separately, which has the advantage of simplifying the production equipment and reducing the cost.

Fourth, by manufacturing a large number of switching elements in a small area semiconductor wafer, there is an advantage that can ensure a uniform electrical characteristics of the switching element.

Fifth, since the storage capacitor is embedded inside the switching element, it is unnecessary to form a separate storage capacitor on the array substrate, thereby improving the aperture ratio, and one nanoblock is seated because two nanoblocks drive one pixel electrode. Even if a defect occurs, there is an advantage that the pixel electrode can be driven.

Claims (4)

In a quadrangular shape having substantially four sides in plan, four transistors including a gate electrode, a source and a drain electrode are integrated, each transistor having four gates, a source and a drain pad in contact with each electrode, respectively on four sides. A switching element for a liquid crystal display device formed symmetrically. The method according to claim 1, And a capacitor in contact with the drain pad. A substrate in which a switching region is defined in an area in which n pieces in a horizontal direction and m pieces in a vertical direction are arranged in a matrix of n × m and an area adjacent to four pixel areas (n and m are positive integers); Four thin film transistors formed in each of the switching regions and having a quadrangular shape having substantially four planes in a planar manner include four thin film transistors including a gate electrode, a source and a drain electrode, each thin film transistor having a gate in contact with each electrode, Nanoblocks each having a source and a drain pad symmetrically formed on four surfaces; M data wires formed at a vertical boundary of each pixel area and applying a signal to each of the nanoblocks; N gate wirings formed at horizontal boundaries of each pixel region and commonly applying signals to N and N + 1th nanoblocks formed in the horizontal direction (where N is a positive integer); A pixel electrode formed in each pixel area and receiving a signal in common at the N and N + 1th nanoblocks; Array substrate for a liquid crystal display device comprising a. The method according to claim 3, And the pixel electrode is a material selected from a group consisting of ITO and IZO.