KR20010078289A - Process for producing a semiconductor wafer with polished edge - Google Patents

Abstract

PURPOSE: A manufacturing method of a semiconductor wafer is provided to polish both surfaces of the semiconductor wafer and to have front and back surfaces and a polished edge. CONSTITUTION: The edge of the semiconductor wafer is polished with polishing cloth. The both surfaces of the semiconductor wafer are simultaneously polished. The both surfaces and the edge of the semiconductor wafer are entirely wetted with a liquid film immediately after the both surfaces of the semiconductor wafer are simultaneously polished. Then the semiconductor wafer is cleaned and dried.

Description

Process for producing a semiconductor wafer with polished edges

The present invention relates to a method for producing bilaterally polished semiconductor wafers having abrasive edges in high yield, and a semiconductor wafer of this type.

Both side polished semiconductor wafers with polished edges are suitable for use in the semiconductor industry, in particular for the production of electronic components having line widths of 0.13 μm or less.

Semiconductor wafers that are particularly suitable for the manufacture of electronic components having a line width of 0.13 μm or less have a high value in all partial regions represented by SFQR _max of 0.13 μm or less, taking into account, for example, how the stepper is operated. It is necessary to have high local flatness.

The high level of flatness of this property can be obtained by known bilateral polishing methods such as abrasion polishing processes.

Apparatuses suitable for polishing both sides of a semiconductor wafer are described by way of example in patent documents DE 19 14 082 B2 and EP 8 360 B1.

The semiconductor wafer according to one embodiment of bilateral polishing described in the patent document EP 208 315 B1 is a process of carriers consisting of metal and having cutouts made of plastic embedded in a suitable size. Depending on the process parameters and the path predetermined by the machine, they move between two rotating abrasive plates, each covered and polished with an abrasive cloth in the presence of an abrasive wear agent.

Fabrication of semiconductor wafers with local flatness values suitable for 0.13 µm component technology has been improved by maintaining a strictly defined thickness relationship between the thickness of the carrier and the thickness of the semiconductor wafer after polishing. In the German Patent Application No. 199 05 737.0, which describes the polishing method, it has the main technical details.

Various polishing cloths are known and can be obtained commercially, which cooperate by mechanical action of the chemical polishing of semiconductor wafers (“chemical-mechanical polishing”: CMP).

In such polishing cloths, the porous side opposite the polished semiconductor wafer is generally firmly attached to the supporting support structure.

The layer that can act in the polishing process may consist of a homogeneous polymer foam, for example polyurethane foam.

Fabrics of this type are described, for example, in patent document US 4,841,680, which is referred to as "foam type" in this particular field.

Another variation is a polishing cloth ("velour type") consisting of polymer fibers, for example polymer foam reinforced with polyester fibers, for example polyurethane foam.

An abrasive cloth of this type is described, for example, in patent documents US 4,728,552 and US Pat. No. 4,927,432, and is produced by impregnating crosslinks by impregnating felts made of the fibers with a polymer liquid.

It is made of felt filled and covered by a porous, soft elastomeric layer.

An example of this type of abrasive cloth is a polyester felt filled and coated with polyurethane.

Patent document EP 8 360 B1 describes a technical configuration in which two types of polishing cloths can be used for polishing on both sides.

The use of a homogeneous polyurethane cloth for polishing both sides of a semiconductor wafer without sawing and edge polishing is known from patent document EP754 785 A1.

Geometry values obtained by such known techniques cannot be used for semiconductor components of this type of wafers belonging to technology generations of 0.13 μm and smaller.

The most widely used polyester-fibre-reinforced polyurethane cloth for double sided polishing is, for example, patent application DE 39 26 673 A1. EP 208 315 B1, EP 711 854 B1, US 5,821,167 and US 5,827,395, German patent applications DE 199 05 737.0, DE 199 38 340.05, DE 199 56 250.4 and DE 199 58 077.4.

In order to adjust the friction and / or adhesion when polishing both sides, holes or channels are formed by the prior art, for example as in patent documents EP 8 360 B1 and German patent applications DE 199 58 077.4 and DE 199 62 564.6. Woven one or two abrasive cloths are described.

A significant drawback of the polyester-fibre-reinforced polyurethane fabrics used for bilateral polishing is the rapid attack of the top polyurethane layer due to mechanical attack on its carriers, exposing the underlying fabric layer.

As a result, the wafer surface and the edges are scratched.

Therefore, the service life of the cloth is shortened and the processing cost is high.

As an example, as described in patent document US Pat. No. 5,900,164, a technically improved polishing cloth by the combination of polymeric microelements also equally withstands attack from carriers up to the limit and is complex and expensive to manufacture. It can manufacture by an expensive method.

In particular, when assembling integrated circuits, semiconductor wafers intended for use in components of the technology generation of 0.13 μm or less, in order to avoid the adhesion of particles that cause defects in all components or component assemblies, must be Need to have

The production of both side polished semiconductor wafers with abrasive edges is equally known.

Both side polishing methods for simultaneously polishing the wafer edges are described in patent documents EP 776 030 A2 and EP 940 219 A2.

However, it is known to those skilled in the art that this type of process includes a technique for balancing in throughput and yield.

Patent documents US 5,882,539 and US 5,899,743 describe a technical configuration in which the edge polishing is carried out after polishing on both sides.

Even in this case, mechanical and chemical deterioration of the bilaterally polished wafer surface results in enormous loss of yield when edge polishing, and wafers of this type are poor in quality and therefore discarded or costly. It needs to be reworked.

As an example, the patent document is described in patent application DE 199 56 250.4.

Accordingly, it is an object of the present invention to provide a method for producing bilateral polishing semiconductor wafers with polished edges in high yield.

1 shows a manufacturing process diagram of a semiconductor wafer polished on both sides according to the present invention.

2 shows a manufacturing process diagram of a semiconductor wafer polished on both sides according to the prior art.

Fig. 3 shows a schematic plan view showing the arrangement of semiconductor wafers polished on both sides and polished on edges when irradiated by an optical microscope.

4 shows a photograph of some sections of a semiconductor wafer made of silicon prepared in Example 1, polished on both sides and polished on edges.

FIG. 5 shows a photograph of some sections of a silicon semiconductor wafer polished to both sides and edges according to Comparative Example 2 (prior art).

<Description of the symbols for the main parts of the drawings>

1: One section of the surface of the semiconductor wafer

2: one section of flank protrusion of semiconductor wafer

The manufacturing method of the present invention is a method of manufacturing a semiconductor wafer for polishing both sides by configuring the semiconductor wafer having the front and rear surfaces and the polishing edge in the following process sequence.

(a) a step of polishing an edge of a semiconductor wafer using an abrasive cloth while continuously supplying an alkaline abrasive wear agent;

(b) two polishing cloths comprising porous homogeneous fiberless polymer foam, the polishing cloth of the lower polishing plate having a smooth surface, and the polishing cloth of the upper polishing plate coated with an polishing cloth having a surface blocked by the channel. A process of simultaneously polishing the front and rear surfaces of the semiconductor wafer while continuously supplying an alkaline abrasive wear agent between the rotating upper and lower polishing plates,

(c) a process of complete wetting the front, back and edges of the semiconductor wafer immediately with a liquid film, following process (b) above;

(d) washing and drying the semiconductor wafer.

The invention also polishes both sides, with a maximum local area of 0.13 μm or less, based on the front and back and the polishing edges and partial regions of the surface grid on the front surface of the semiconductor wafers fabricated as in this method. A semiconductor wafer having a maximum local flatness value SFQR _max .

An important feature of the present invention is that the edge polishing step (a) is performed before both side polishing steps (b) in order to manufacture the semiconductor wafer according to the present invention.

Another feature of the present invention is to use a polishing cloth composed of porous homogeneous fiberless polymer foam during both sides polishing by the process (b), and the polishing cloth spread on the lower polishing plate has a smooth surface, and the upper polishing plate shape The polishing cloth is in a configuration with a surface blocked by channels.

The third feature of the present invention is that the semiconductor wafer is completely wetted with the liquid film by the step (c).

As such, by constructing a two-side polished semiconductor wafer with abrasive edges, the yield can be significantly increased, and thus manufacturing costs can be reduced only when equipped with all three of the specific features described above. .

The starting material of the process of the invention is a semiconductor wafer, the semiconductor wafer being cut into crystals obtained in known methods, eg longitudinally, to a cylindrical shape, rounding its edges, the front and / or The backside is a semiconductor wafer separated from the silicon single crystal that is planarized in the polishing, lapping and / or etching process, if appropriate.

The final product of the process of the present invention is a bilateral polished semiconductor wafer having a polishing edge that meets the requirements for use as a starting material for semiconductor component processes with line widths of 0.13 μm or less and because of its high yield, In terms of technology, both side polished semiconductor wafers having polishing edges prepared in the prior art are technically improved.

In particular, it is possible to produce disk-like bodies using the method according to the invention, the disk-shaped body being a material which can be machined using chemical-mechanical edge polishing processes and bilateral polishing processes. A disk shaped body is used.

Materials of this type include, for example, III-V semiconductors such as silicon, silicon / germanium and gallium arsenide.

The process of the present invention is particularly suitable for the production of single crystal silicon wafers with diameters of 200 mm, 300 mm, 400 mm and 450 mm and thicknesses of two hundred and thirty to two or three centimeters, preferably 400 to 1200 micrometers.

The semiconductor wafer can be used directly as a starting material for the manufacture of semiconductor components, and after the final polishing process according to the prior art, or for example epitaxial coating or backside seal on the front surface of a wafer with silicon. After treatment of layers such as back surface seals, or after heat treatment, for example, under hydrogen or argon atmosphere, they may be supplied according to the desired purpose.

In addition to the production of a wafer from a homogeneous material, the present invention can also be used for the production of a semiconductor substrate having a multilayer structure such as an SOI (silicon-on-insulator) wafer.

The method of the present invention will be further described according to the production examples of silicon wafers.

Initially starp, silicon wafers sawed using a sawing method with an annular saw, for example, rounding wafer edges that are too sensitive to mechanical processing, are suitably made of metal or resin bonded diamonds. It is processed by the formed grinding wheel.

In this case, the edge can be rounded in one step.

In the case of the preferred two-step edge rounding due to the throughput, a polishing wheel with diamond particles ranging from 40 mesh (particle size range 30-50 μm) to 600 mesh (particle size range 20-30 μm) is used first. A grinding wheel having a diamond particle size of 1000 mesh (particle size range 8-15 μm) to 2000 mesh (particle size range 4-6 μm) is used.

A planarization step is preferred at this point in order to improve its geometric shape and partially wear down the broken crystal layer.

As such, the semiconductor wafer may be subjected to mechanical wear processes such as lapping or grinding, and then to wet-chemical or plasma etching processes to reduce material wear in both side wear processes (b).

The front and rear surfaces of the wafer using a grinding wheel made of metal or resin-bonded diamond particles with particles ranging from 400 mesh (particle size range 30-50 μm) to 1000 mesh (particle size range 8-15 μm). Sequential surface grinding is preferably performed in combination with an acid etching process in a mixed solution of concentrated nitric acid solution and concentrated hydrofluoric acid solution.

In particular, a preferred starting material is a semiconductor wafer consisting of silicon having a diameter of 200 mm or more, wherein the semiconductor wafer is subjected to wire sawing of silicon single crystals, followed by edge rounding, to remove silicon having a thickness of 10 µm to 100 µm on each surface. Produced by wet chemical etching treatment in the acid etching mixture which removes 5-50 micrometers of silicon from each surface by carrying out surface polishing of both sides of the semiconductor wafer.

Next, the starting material is converted into a double-sided polishing silicon wafer with a high yield polishing edge that meets the requirements imposed on the semiconductor wafer as a starting material for semiconductor component processes with line widths of 0.13 μm or less. Steps (a) to (d) of the method of the present invention to be described in more detail below.

Edge-polishing Process (a)

A commercially available edge grinder depends on the diameter of the wafer to be polished, and can be used to perform the edge polishing step (a).

Polishing is preferably carried out using a commercially available polyurethane abrasive cloth having a hardness of 30-70 (Shore A), which polyurethane abrasive cloth may comprise reinforced polyester fibers.

Suitable abrasive cloths are equally used on the market.

The process involves first polishing one flank, e.g., lower flank, of the wafer edge by rotating the silicon wafer, using an inclinedly positioned polishing plate covered with an abrasive cloth. And then to the other side, for example to polish the upper side of the wafer edge.

Processes of this type are described by way of example in patent document US 5,866,477.

However, as described in patent document EP 687 524 B1 as an example, the whole rounding edge can also be polished in one step.

The edge polishing process is performed by continuously supplying an abrasive abrasive of PH 9-12.

Suitable abrasive wear agents comprise a number of inorganic materials having abrading action, such as suspending solutions or claudes of silicon dioxide in the presence of an alkali and, if appropriate, further additives.

In particular, the preferred alkaline abrasive wear agent in the process (a) of the present invention has PH 10 to 11.5 and is composed of 1 to 5 wt% SiO ₂ in water.

The polishing time required to obtain a polishing edge free of defects throughout the process depends on the wafer diameter, for example, for a 300-mm silicon wafer, the polishing time is 0.5 to 5 minutes.

In the process 0.5 to 15 μm of silicon, particularly preferably 2 to 10 μm, wear based on the surface of the edge.

Both Side Polishing Process (b)

A commercially available bilateral polishing machine of suitable size can be used for carrying out the bilateral polishing step (b).

Due to the cost, it can be seen that a plurality of silicon wafers are simultaneously polished.

The polishing machine is actually composed of a lower abrasive plate that can rotate freely in the horizontal plane and an upper abrasive plate that can rotate freely in the horizontal plane, so that the upper and lower plates are covered with an abrasive cloth and used in step (a). The abrasive wear agent having the same composition as the abrasive wear agent is continuously supplied.

The polishing machine, in the case of this silicon wafer, causes the polishing of the semiconductor wafer on both sides.

In this case, during polishing, the silicon wafer is subjected to a geometry path determined by the polishing machine and a process parameter by a driven carrier with appropriately sized cutouts to support the silicon wafer. Supported

Carriers composed of steel or fiber reinforced plastic are preferred.

Carriers made of stainless chromium steel are particularly preferred because of their high dimensional stability and chemical resistance.

During polishing, in order to prevent damage to the polishing wafer edge by the inner edge of the cutout of the carrier, for example, a plastic coating of the same thickness as the carrier by an extrusion process as described in patent document EP 208 315 B1. Lining is preferred for the inner side of the cutout.

Examples of suitable plastics are polyamide, polyethylene, polypropylene, polyvinylchloride, polytetrafluoroethylene, or polyvinylidenedifluoride, all of which are equally preferred.

In view of the quality maintenance of the edges, it is preferable that the plastic coatings on all the cutouts check their damage before each side polishing operation and replace them after a predetermined period of use, for example after 100 to 200 polishing operations.

In the present invention, both side polishing processes (b) are carried out using an abrasive cloth made of porous homogeneous polymer foam having a hardness of 60-90 (Shore A).

The side opposite the semiconductor wafer side to be polished does not act in the polishing process, if appropriate, and is bonded to a mechanically more stable support layer that does not form part of the present invention.

Mixtures of polymer foams of this type or polymer foams belonging to the elastomer group are preferred for the abrasion of the silicone in process (b).

Examples of such foams are polyurethanes, polyamides, polyethers, polyvinyl alcohols, polyvinyl chlorides and polycarbonates (different in chain length and degree of crosslinking).

In particular polymer foam consisting of polyurethane is particularly preferred.

In practice to achieve the object of the present invention, it has been found that only homogeneous polymer foams of this type are suitable for providing flawless wiper surfaces and edges.

For example, when polyester-reinforced abrasive cloth is used under the conditions currently practiced for both side polishing, the top polymer foam layer will wear after only two or three polishing operations, resulting in a roughened wafer edge. It is necessary to replace the fabric of this type after the polishing operation is lost, and after 10 to 20 polishing operations, for example, after only two or three polishing operations.

In addition, an abrasive cloth made of polymer foam has 100 to 200 double-sided polishing operations, and in exceptional cases, has a service life with a greater number of operations.

An abrasive cloth made of polymer foam within the preferred hardness range can also be used in commercial products.

Both side grinding machines with large diameters, for example 2 m, constitute the covering of a plurality of pieces, for example two or four pieces of upper and lower polishing plates, as described in the patent document DE 199 62 564.6. It is necessary.

In order to achieve the object of the present invention, a network of channels is added to the polishing cloth fixed to the upper polishing plate, and the polishing cloth fixed to the lower polishing plate having the smooth surface is separated without forming such a structure. It is necessary.

Once the polishing on both sides is completed, the rotating means initially introduced can be removed so that the upper polishing plate is lifted and the silicon wafer is not fixed to the upper polishing plate.

However, as a result of such texturing, it is necessary to improve the dispersion of the abrasive wear agent used to maintain the quality of the abrasive wafer edge.

The channel can be formed in an abrasive cloth by, for example, a material-removing milling operation.

The upper abrasive cloth preferably has a constant channel arrangement, which is similar to a chess board, having a square size of 5 mm x 5 mm to 50 mm x 50 mm and a channel width and a depth of 0.5 to 2 mm.

In this arrangement, polishing is carried out at a polishing pressure of 0.1 to 0.3 bar.

The silicon wear amount is preferably 0.1 to 1.5 µm / min, particularly preferably 0.4 to 0.9 µm / min.

The total amount of silicon worn in step (b) is preferably 2 to 100 µm, particularly 20 to 50 µm.

The thickness of the carrier in the both side polishing step (b) is preferably 400-1200 µm.

After the step (b), in order to have a silicon wafer having a high local flatness, in particular when using an abrasive cloth made of a porous homogeneous polymer foam according to the present invention, the German patent application 199 05 Particular preference is given to bilateral polishing methods, as described in the 737.0 specification.

In this bilateral polishing method, the thickness selected for the carrier depends on the desired final thickness of the silicon wafer following the step (b), and is configured to be 2 to 20 µm or less than the final thickness of the silicon wafer.

Stopping step to form film

After the bilateral polishing step (b) is completed, it is necessary to passivate the chemically highly reactive hydrophobic wafer surface.

In order to achieve the object of the present invention, by supplying one or more liquids so that the polishing front, the polishing back and the polishing edge of the silicon wafer is completely wetted with the liquid film so that the liquid acts as a stopping agent. To achieve.

In the absence of film formation during the stopping step, the polishing edge inevitably becomes considerably rougher even with all the measurements described above.

A liquid having ultrapure water as a main component is practically preferred in the stopping step (c) in which film formation is performed.

The film former is included in the supplied liquid.

In addition, various film-forming agents are contained in one or more liquids having different compositions, and the concentration to be used depends on the characteristics of the film-forming agent and ranges from 10 ^-4 to 50 vol.

A concentration range of 0.1 to 10 vol.% Is generally preferred.

The liquid film mainly has two requirements:

(1) The film needs to protect the surface and the edge of the silicon wafer after the step (b) subjected to the continuous etching attack of the abrasive wear agent is finished.

(2) It is necessary to remove the film completely by washing | cleaning in a process (d).

The liquid or various kinds of liquid supply can be exchanged with the supply of abrasive wear described above.

The polisher seals and simultaneously treats the front, back and edges of the silicon wafer with the stopper between the rotating polishing plates and there is no temporary contact with atmospheric oxygen to the reactive wafer surface.

In order to reduce the frictional force, it is desirable to reduce the polishing pressure to a range of 0.02 to 0.10 bar and to supply a stopper.

The chemical composition of the film former can be selected mainly as needed.

However, the two requirements mentioned above can be met, and the regulations and standards that can be handled reliably at the time of implementation can be met, especially at no cost.

If appropriate, it is preferred to use a compound which facilitates mixing with the liquid, preferably ultrapure water, while adding a phase compatibilizer without significantly increasing the viscosity of the liquid.

Particularly preferred in the present invention is the use of at least one substance which can be used for the production of semiconductor wafers with satisfactory purity and selected from the group of compounds consisting of polyhydric alcohols, polyalcohols and surfactants.

Here, the term surfactant can be defined as inorganic and organic surfactants, which are described in the technical literature as "wetting agents".

Examples of suitable polyhydric alcohols include ethylene glycol (1,2-ethanediol), propylene glycol (1,2 and 1,3-propanediol), butylene glycol (1,3- and 1,4-butanediol) and Glycerol (1,2,3-propanetriol).

The use of these materials as stoppers for bilateral polishing is described in the German patent application DE 199 38 340.5 specification.

One example of polyalcohols is polyvinylalcohol, which is commercially available under the trade name vinnapas by way of example from Wacker Chemie GmbH.

Another example of a polyalcohol is one material selected from the group consisting of polyetherpolyols, whose polyetherpolyols are commercially available under the trade name polyox by, for example, Union Carbide.

The use of polyetherpolyols as a bilateral polishing terminator is described in patent document EP 684 634 A2.

One example of a surfactant is a preparation compound based on alkylbenzenesulfonic acid and amine ethoxylate, which was supplied by the manufacturer ICB under the trade name Silapur.

Furthermore, the terminators include short-chain monohydric alcohols having a concentration of 0.01 to 2 vol.%, Such as i-propanol and n-butanol.

The addition of a strongly acidic component or a strong base component results in SiO ₂ particles being generated due to unchanged PH change in the former, which scratches the wafer surface and edges, while etching in the latter surface on the wafer surface and edges. spots are obtained, which is undesirable.

Moreover, another example of the stop process of forming especially preferable film is as follows.

First, the feed of abrasive wear used in process (b) has a PH 9-11, at least one substance in the compound group consisting of 0.5-4 wt% SiO ₂ , polyhydric alcohol, polyalcohol and surfactant 10 It consists of a water-soluble mixture of -4 to 50 vol.%, In particular 0.1 to 10 vol.%, And another small amount of additive is replaced by a feed of abrasive wear which can be present in the mixture.

Mixtures of this type are known and generally used as abrasive wear agents for the polishing of surfaces of silicon wafers and component wafers in the manufacture of components where very low wear is desirable.

The use of polyvinyl alcohol-containing abrasive wear agents is described in patent document DE 2247 067 B2.

Abrasive wear agents comprising polymer additives and surfactants as film forming agents are known from patent document US 5,861,055 as an example.

Abrasive wear agents (trade name Glanzox 3900, manufacturer Fujimi), which are commercially available in the method of the embodiment of the present invention, are abrasive wear agents which contain, in the manufacturer's instructions, SiO ₂ , ammonia and surfactants not specifically described. As an example it has been used in the preferred embodiment of patent document EP 684 634 A2 and is suitable as abrasive wear agent in this invention.

This mixture was supplied, but the rotation was maintained while reducing the polishing pressure to 0.05-0.15 bar, and the process was maintained for 1 to 10 minutes.

As a result, a liquid film made of polyvalent alcohol and / or polyalcohol and / or surfactant is formed on the surface and edge of the silicon wafer.

Then, in order to clean and remove the abrasive wear agent from the silicon wafer and to maintain the film on the surface and the edge, the rotation is continuously performed by supplying ultrapure water, and the pressure ranges from 0.02 to 0.10 bar over 1 minute to 10 minutes. To further reduce.

After completion of the film forming stop step (c), the upper polishing plates of both side polishers are lifted off while rotating and then rotated.

Desorption of the silicon wafer and transfer to an aqueous bath is carried out in a vacuum sucker or automatic unloading device which is guided manually or manually using gloved fingers. It can be carried out by.

Removal and removal of the wafer by a vacuum sucker described in the patent application DE 199 58 077.4 in the patent literature is preferred in the present invention.

This is because in this process, for example, both side grinders with 30 to 200 mm wafers or 15 to 300 mm wafers must be unloaded within 2 minutes, while at the same time obtaining an acceptable manufacturing cost and wafer yield. to be.

In this way, a wet tray filler formed into a receiving device in which the silicon wafer picked up by suction is placed in the infusion tank or to a diameter of the wafers to be received. Go inside

The used fluid bath or wet tray filler may be filled with ultrapure water or ultrapure water consisting of a small amount of addition of acid and / or oxides and / or surfactants in order to optimize the preservation of the wafer surface.

Cleaning / Drying Process (d)

After step (c), the silicon wafer was cleaned and dried according to the prior art.

The cleaning process can be carried out in a batch process or a single wafer process which simultaneously cleans multiple wafers using a spray method in a bath.

In the present invention, for example, in the present invention, the tub washing is performed simultaneously using the hydrofluoric acid (HF) solution-ultrapure water-TMAH / H ₂ O ₂ -ultrapure water, and TMAH / In a H ₂ O ₂ bath, the help of megasound is effective in improving the removal of particles.

By way of example, devices operating using centrifugal drying, hot water, Marangoni or HF / ozone treatment may be used in commercial products and are equally preferred for drying without spots.

Both side polished and edge polished wafers obtained in this way are dried, hydrophilic and no longer have any residue of the liquid film treated in step (c).

The processing method in the order of steps (a), (b), (c), and (d) according to the present invention does not form part of the present invention, but the silicon wafer can be understood and Evaluation was made according to required quality standards.

As an example, the geometry can be measured.

For example, measurements made on a commercially available shape measurement device operating according to the capacitive optical principle for a component surface 25 mm x 25 mm show a local shape value SFQR _max of 0.13 μm or less, which is 0.13. Prerequisites for these wafers for use in the manufacture of semiconductor components with line widths of [mu] m or less.

In this respect, visual evaluation of the front, back and edges of all silicon wafers treated in a darkened assessment chamber under haze light is commonly understood as eliminating defective wafers.

In this evaluation, defects that occur in the processing of the wafer in the component manufacturing have been found, such as scratches and spots.

In particular, in the manufacture of the edge-polishing semiconductor wafer according to the present invention, in order to confirm and verify deviations existing on the surface of the polishing wafer as a result of roughening, for example, it is necessary to inspect the edges under a microscope. desirable.

Using a commercially available optical microscope with 10 to 100 times resolution, the wafer can be evaluated vertically and placed at the set position, and the microscope is suitable for this purpose in its edge region. .

When using the present invention, the yield of bilateral abrasive silicon wafers with abrasive edges suitable for 0.13 μm components is greater than 96%, while the yield is less than 85% in the treatment process according to the prior art.

According to a further use of the invention, in each case the front surface of the silicon wafer produced using the method according to the invention can be prepared using a conventional abrasive cloth with alkaline abrasive wear based on SiO ₂ as an example. It is necessary to process by the final polishing process.

In order to maintain the lowest local shape value, the amount of silicon worn on each wafer in this process is relatively small, for example in the range of 0.1 to 1 mu m.

If necessary, another machining process on the silicon wafer can be added at a suitable point by the method of the present invention and, for example, eliminating thermal donors in view of the specific configuration required for the manufacture of the component. Heat treatment process, laser marking for wafer identification, backside coating or epitaxial layer treatment, and cleaning and drying process.

Semiconductor wafers, in particular silicon wafers, produced by the present invention meet the requirements for the manufacture of semiconductor components having a line width of 0.13 μm or less.

The method according to the present invention was found to be an optimal solution to increase the yield of the wafer by reducing the manufacturing cost of the two-side polishing silicon wafer with abrasive edge.

The present invention will be described with reference to the following examples and comparative examples by the accompanying drawings, but is not limited thereto.

In the following, all the embodiments described and the contrast examples relate to the manufacture of a single crystal silicon wafer of coordination 100 having a diameter of 300 mm.

Bilateral polishing and edge polishing wafers with defect-free faces and edges are preferred.

The single crystal required for this purpose is drawn by a conventional technique into a wire saw that can be used for commercial purposes to be a wafer with a constant thickness made from the final product, cut to a certain length, polished into a cylindrical shape, and then cut. do.

After rounding the edges, the surface polishing process was carried out in a rotary polishing machine using diamond particles 600 mesh (particle size range 20-30 μm), in which case 30 μm silicon was treated in this way on the front and back of the wafer. An acid etching process using a fluid etching process is performed to rotate the wafer in a mixture of 90 wt% concentrated nitric acid (70 wt% in aqueous solution), 10 wt% concentrated hydrofluoric acid (50 wt% in aqueous stone) and 0.1 wt% ammonium lauryl sulfate. As a result of impregnation, in each case 10 μm of silicon was simultaneously worn on each wafer surface.

The temperature of the etching mixture was adjusted to 20 ° C., and gaseous nitrogen was introduced through the mixture.

At this time, the thickness of the wafer was 815 mu m.

The process of continuing processing is described below.

In certain and contrasting examples, the edge polishing process is represented by step (a), the two-side polishing process is represented by step (b), the stopping process for forming a film is represented by step (c), and the cleaning / drying step. Is represented by step (d).

In both side polishing processes (b), the material of the upper and lower polishing cloths is the same in each case in the predetermined embodiment and in the contrast embodiment.

In all cases it is specifically specified whether the upper abrasive cloth is constituted by the channel.

All silicon wafers manufactured by Examples and Contrast Examples had a local flatness value SFQR for a component surface of size 25 mm x 25 mm._max 0.13 μm

Or less.

Example 1

Edge polishing process (a)

An edge rounding and polishing, and then the edge of the etched wafer and the edge polishing machine (for a 300mm wafer, a type EP300-IV, speedFam manufacture) that can be purchased on the market, SiO ₂ solids content of 3wt%, PH 10.5 (potassium carbonate Polishing was carried out using a water-soluble abrasive (trade name Levasil 200, manufactured by Bayer) with the addition of carbonate (fixed PH to 10.5) and a polyethylene-fiber-reinforced polyurethane polishing cloth of hardness 50 (Shore A).

The lower flank of the wafer edge was initially polished and then the top side of the wafer edge was continuously polished while rotating the silicon wafer with the polishing cloth with the polishing cloth disposed obliquely.

Both Side Polishing Process (b)

Four carriers made of stainless chromium steel with a lapping surface and a thickness of 770 μm were used.

The carriers are each arranged at regular intervals on the circular passage, lined with polyamide, and have three circular cutouts with an internal diameter of 301 mm.

Both side polishers (type AC 2000, manufactured by Peter wolters) were used to polish 15 300 mm silicon wafers simultaneously.

The two-side polishing process uses a commercially available abrasive cloth made of porous polyurethane foam with a hardness of 80 (Shore A), without fiber reinforcement, in which case, the SiO ₂ solids content is 3wt% and the pH 10.8 (potassium carbonate and potassium hydroxide). The polishing cloth was attached to the upper and lower abrasive plates by a pressure adhesive of 0.15 bar using a water-soluble abrasive (Levasil 200, manufactured by Bayer) having a pH of 10.8 by the addition of the side. .

The surface of the polishing cloth spread on the lower polishing plate had a smooth surface, and the surface of the polishing cloth spread on the upper polishing plate had milling channels of a chessboard pattern having a width of 1.5 mm and a length of 0.5 mm. The channels were arranged at even intervals of 30 mm in one circle segment configuration.

In each case, the polishing was performed by the upper and lower abrasive plates at a temperature of 40 ° C., resulting in a low wear amount of 0.68 μm / min.

20 μm of silicon was polished on each wafer surface.

Stopping process with film formation (c)

After the polishing wafer had a thickness of 775 占 퐉, the polishing wear agent was supplied in 3 minutes for 1 vol.% Of glycerol, 1 vol.% Of n-butanol, and a surfactant (alkylbenzenesulfonic acid and amine epoxylate. It was replaced by supplying a stopper composed of an aqueous solution of 0.07 vol.% (Trade name silapur, manufactured by ICB).

After the upper polishing plate was lifted and rotated, the entire surface of the fully polished silicon wafer placed on the carrier cutout was sufficiently wetted with a stopping liquid.

The silicon wafer was removed from both side polishers using a vacuum sucker with a handle, made of polypropylene, and with three suction cups of soft PVC.

Ultrapure water was added using a commercially available 300 mm wet tray filler containing the polished silicon wafer.

In the processing step, the carrier remained at the position where the wafer was removed and removed, and then the wafer was removed and moved to the wet tray filler by the vacuum circuit.

Cleaning / Drying Process (d)

The silicon wafers thus treated are cleaned in a batch-cleaning apparatus using the following procedure, water-soluble hydrofluoric acid-ultra pure water-TMAH / H ₂ O ₂ / megasound-ultra pure water, and the i-Pro by Marangoni principle. It was dried in a commercial dryer operating with panol.

Next, a visual evaluation of the front, back and edges of all the wafers treated in this way in the darkening chamber under hazelight and an optical stereomicroscope magnified by 20 times and the warp edge of the wafer edge. The wafer edges were evaluated by oblique illumination.

In the quality evaluation of wafers treated in this way, 97% met the quality criteria without scratches, spots and light point defects requiring further processing.

Irradiation with a light microscope showed no unacceptable defects on the wafer edge.

Example 2

The treatment step was carried out as in Example 1 except that the stop step (c) of forming the film was carried out as follows.

Supply of the abrasive wear agent supplied in the step (b), after the polishing wafer reached a thickness of 775 占 퐉, was terminated again and mixed for three minutes, a mixture of the abrasive wear agent (Glanzox 3900, manufactured by Fujimi) and ultrapure water, SiO _It was replaced by supplying a stopper with ₂ solids content of 2 wt% and having a PH10.0, and the lower polishing plate, upper polishing plate and carrier were continuously moved to reduce the pressure to 0.10 bar.

Then, while rinsing with ultrapure water for 2 minutes, the rotation was maintained, and the pressure was further reduced to 0.05 bar.

After the upper polishing plate was lifted up and rotated, sufficient wetting of the silicon wafer was also observed in this case.

The yield of the satisfied wafer was 98%.

Irradiation with a light microscope showed no unacceptable defects on the wafer edge.

Contrast Example 1

In the patent literature, the experiment used in Comparative Example 1, which corresponds to the experiment described in Example 7 of the German patent application DE 199 56 250.4, is characterized by an edge polishing process (a) which is carried out only after both side polishing processes (b). Include.

The two-side polishing process (b) was carried out as in Example 1, but a commercially available polyethylene-fiber-reinforced polyurethane polishing cloth having a hardness of 74 (Shore A) was used, and the polishing cloth was applied to the upper and lower polishing plates in each case by a pressure-sensitive adhesive. Once again attached to.

The upper abrasive cloth similarly constituted a channel of the chessboard shape pattern according to Example 1.

At 0.64 m / min, the amount of wear did not differ significantly from the amount of wear prescribed in Example 1.

Supply of the abrasive wear agent was terminated after the thickness of the abrasive wafer reached 775 占 퐉, and then supplied with a stopper consisting of a mixture of 3 wt% Levasil 200 and 1 vol.% N-butanol in water for 3 minutes. The lower abrasive plate, the upper abrasive plate and the carrier were moved continuously to reduce the pressure to 0.5 bar.

After the upper polishing plate was raised and rotated, there were some areas wetted with the stop mixture and some dry areas on the front of the fully polished silicon wafer located on the carrier cutout.

This is a sign that the used stopper does not meet the sufficient wetting requirements of the semiconductor wafer.

The four carriers were stripped off and removed, and then the silicon wafer was stripped off using the fingers protected by a Radex glove at the polisher.

Then, the edge polishing step (a) was carried out as in Example 1, followed by washing and drying by the step (d) of Example 1.

Of the relevant quantities of wafers treated in this way, 5% did not meet quality criteria without light point defects requiring scratches, spots and further processing.

In addition, an unacceptable initial local etching due to the edge polishing process (a) was also formed on the wafer of 11%.

Irradiation with a light microscope showed no unacceptable roughening of the wafer edge.

Contrast Example 2

As in Example 1, the treatment steps (a) to (d) were performed in the same order.

However, unlike Example 1, as described in Comparative Example 1, both side polishing steps (b) were carried out using a polyethylene-fiber-reinforced polyurethane polishing cloth having a hardness of 74 (Shore A).

The upper abrasive cloth was composed of a channel of the chessboard shape pattern according to Example 1.

After the two-side polishing process (b) was completed, a mixture of the above-described product name Levasil 200 and n-butanol dissolved in water was added as in Comparative Example 1, and the silicon wafer was removed by removing the carrier and then removed from the polishing machine. Manually removed and removed.

Next, the semiconductor wafer according to Example 1 was washed and dried.

Wafers irradiated by light microscopy exhibited significant roughening of the wafer edges which would not allow further processing.

Comparative Example 3

Instead of the polyurethane cloth, the process was treated as in Example 1 using the polyethylene-fiber-reinforced polyurethane polishing cloth described in Comparative Example 1, in which the top fabric was constructed.

5% of the wafers showed scratches, spots and / or light point defects.

Another 47% of wafers did not adequately meet the specification because of the roughened edges detectable by light microscopy.

Dash Example 4

Instead of the urethane cloth, the treatment process was carried out as in Example 2 using the polyethylene-fiber-reinforced polyurethane polishing cloth of Comparative Example 1 which constituted the upper fabric.

3% of the wafers exhibited scratch, spot and / or light point defects. In addition, 36% of the wafers were not adequately met by the specification because of the roughened edges that could be detected by light microscopy.

Comparative Example 5

Instead of the polyethylene-fiber-reinforced polyurethane cloth, the process was carried out as in Comparative Example 2, except that the polyurethane abrasive cloth described in Example 1, which constituted the top fabric, was used.

All wafers examined by light microscopy exhibited significant roughening of the wafer edge which was unacceptable for further processing.

Comparative Example 6

The treatment was carried out as in Example 1, except that the upper polyurethane cloth was not constituted.

4% of the wafers were unacceptable because of scratch, spot and / or lightpoint defects, and 17% of the wafers were unacceptable because of the roughened edges that could be detected by the light microscope.

As a result, the configuration of Examples (E1 and E2) and Comparative Examples (C1 to C6) differed significantly by the features listed in the table shown below.

In this table, PU stands for porous polyurethane foam, PE / PU stands for polyester-fiber-reinforced polyurethane, (a) refers to the edge-polishing process, and (b) refers to the film forming stop process. , (d) refers to the washing / drying process.

Re (a): edge polishing Re (b): type of abrasive cloth Re (b): upper fabric channel Re (c): film formation Re (c): remove the circus Re (d): Yield of Statement E1E2 Yes Yes PUDU Yes Yes Yes Yes Yes Yes 97% 98% C1C2C3C4C5C6 (b) Yes Yes Yes Yes PE / PUPE / PUPE / PUPE / PUPUPU Yes Yes Yes Yes Yes No None None Yes Yes Yes Yes None None Yes Yes Yes Yes 84% 0% 48% 61% 0% 79%

It is evident from the table above that the performance of the method of the present invention is high in the yield of bilateral polished semiconductor wafers of silicon with abrasive edges capable of meeting the specification "bonded faces and edges".

According to the present invention, both side polishing semiconductors having polishing edges can be produced with high yield.

In the yield of silicon semiconductor wafers polished on both sides with defect-free surfaces and polishing edges capable of satisfying edges, high yields can be obtained by the method of the present invention.

Claims (16)

A manufacturing method of a semiconductor wafer having a front and rear surfaces and a polishing edge for polishing both sides of the semiconductor wafer, the manufacturing method comprising the following process sequence. (a) polishing the edge of the semiconductor wafer with an abrasive cloth while continuously supplying an alkaline abrasive wear agent; (b) Abrasive cloth Two rotating cloths coated with an abrasive cloth having a smooth surface and having a surface blocked by the abrasive transition channel of the upper abrasive plate, with the polishing cloth of the lower abrasive plate made of polymer foam without the porous homogeneous fiber. Simultaneously polishing the front and rear surfaces of the semiconductor wafer while continuously supplying an alkaline abrasive wear agent between the upper and lower polishing plates; (c) immediately following step (b), fully wetting the front, back and edges of the semiconductor wafer with liquid film; And (d) A step of washing and drying the semiconductor wafer. 2. The manufacturing method according to claim 1, wherein the semiconductor wafer is set at a cutout of a career when the steps (b) and (c) are processed. 3. The manufacturing method according to claim 2, wherein the thickness of the carrier is 2 to 20 [mu] m or less than the thickness of the completely polished semiconductor wafer. The method according to claim 1, wherein in step (b), the thickness of the semiconductor wafer is reduced to 2 to 100 mu m. The method according to claim 1, wherein the alkaline abrasive wear agent used in steps (a) and (b) is composed of a suspension of pH 9-12 in which silicon dioxide particles and inorganic and / or organic bases are dissolved in ultrapure water. The method of claim 1, wherein the polishing cloth of the upper and lower abrasive plates is made of polyurethane, and has a Shore A hardness of 60 to 90. 3. The polishing pad of claim 1, wherein the polishing cloth of the upper abrasive plate has a constant channel arrangement equal to a chess board having a square size of 5 mm x 5 mm to 50 mm x 50 mm and a channel width and depth of 0.5 mm x 2 mm. Method for producing having a. 2. A process according to claim 1, wherein the liquid film generated in step (c) is then completely removed in a cleaning step (d). The method according to claim 1, wherein the liquid film generated in step (c) comprises at least one compound in the group consisting of polyhydric alcohol, polyalcohol and surfactant. 10. The method of claim 9, wherein the liquid film contains glycerol. 10. The process according to claim 9, wherein the liquid film constitutes at least one compound selected from the group consisting of polyethers, polyols and polyvinyl alcohols. 10. A process according to claim 9, wherein the liquid film comprises a surfactant, initially producing a mixture of the water-soluble abrasive wear agent and the surfactant, followed by supplying ultrapure water for a short time. 2. A method according to claim 1, wherein the semiconductor wafer is removed from the polishing machine by a vacuum sucker after step (c). The method according to claim 1, wherein after carrying out steps (a) to (d), semiconductive epitaxial coating is applied to the entire surface of the semiconductor wafer. The process according to claim 1, wherein steps (a) to (d) are carried out, followed by final polishing on the front surface of the semiconductor wafer to clean and dry the semiconductor wafer, and if necessary, semiconductive epitaxial coating on the front surface of the semiconductor wafer. Manufacturing method characterized in that the treatment. The maximum local flatness value SFOR _max of 0.13 μm or less, based on the partial area of the surface grid on the front surface of the semiconductor wafer manufactured by the method of claim 1, and on the front, back and polishing surfaces. Semiconductor wafers polished on both sides with paper.