KR20010077405A - Method for Forming Metal Line of Semiconductor Device - Google Patents

Method for Forming Metal Line of Semiconductor Device Download PDF

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Publication number
KR20010077405A
KR20010077405A KR1020000005195A KR20000005195A KR20010077405A KR 20010077405 A KR20010077405 A KR 20010077405A KR 1020000005195 A KR1020000005195 A KR 1020000005195A KR 20000005195 A KR20000005195 A KR 20000005195A KR 20010077405 A KR20010077405 A KR 20010077405A
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South Korea
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semiconductor substrate
metal
film
contact hole
forming
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KR1020000005195A
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Korean (ko)
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한상엽
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박종섭
주식회사 하이닉스반도체
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Priority to KR1020000005195A priority Critical patent/KR20010077405A/en
Publication of KR20010077405A publication Critical patent/KR20010077405A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric

Abstract

PURPOSE: A method for manufacturing a metal interconnection of a semiconductor device is provided to reduce manufacturing cost and to improve step coverage, by depositing a TiN layer of a minimum thickness satisfying an electrical characteristic or a diffusion barrier by a chemical vapor deposition(CVD) method, and by depositing the rest of a TiN layer of a required thickness by a conventional physical vapor deposition(PVD) method. CONSTITUTION: An insulation layer is formed on a semiconductor substrate(21). The insulation layer is selectively eliminated to expose the surface of the semiconductor substrate and to form a contact hole. The first metal layer is formed on the entire surface of the semiconductor substrate including the contact hole. The first and second barrier metal layers are sequentially formed on the first metal layer by a chemical vapor deposition(CVD) method and a physical vapor deposition(PVD) method. A metal plug(28a) is formed inside the contact hole. A metal interconnection(29) electrically connected to the semiconductor substrate through the metal plug is formed.

Description

반도체 소자의 금속 배선 형성 방법{Method for Forming Metal Line of Semiconductor Device}Method for forming metal wiring of semiconductor device {Method for Forming Metal Line of Semiconductor Device}

본 발명은 반도체 소자의 제조 공정에 관한 것으로, 특히 베리어층의 스텝 커버리지(step coverage) 문제를 개선하기 위한 반도체 소자의 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing process of a semiconductor device, and more particularly, to a method of forming metal wirings in a semiconductor device for improving a step coverage problem of a barrier layer.

반도체 소자의 제조 공정의 중요한 요소중의 하나인 소자에 전기적 신호를 인가해 줄 수 있는 금속 배선을 형성하는 공정에서 현재는 텅스텐 플러그 공정과 알루미늄 배선 공정을 많이 사용하고 있다.The tungsten plug process and the aluminum wiring process are currently used in the process of forming a metal wiring for applying an electrical signal to the device, which is one of the important elements of the semiconductor device manufacturing process.

소자를 구동시키는 트랜지스터 또는 메모리 캐패시터와 금속 배선간의 절연, 또는 다층 금속 배선 형성시 하부 금속 배선과의 절연을 위한 절연막상에 텅스텐 플러그 공정을 바로 실시하면 절연막과 텅스텐의 접착이 좋지 않다.If the tungsten plug process is immediately performed on the insulating film for insulation between the transistor or memory capacitor driving the device and the metal wiring, or the lower metal wiring when forming the multilayer metal wiring, the adhesion between the insulating film and tungsten is not good.

그래서 상기 텅스텐 플러그 공정에 앞서 확산 베리어 역할을 할 수 있는 베리어층을 형성한다. 상기 베리어층은 텅스텐막과 접촉하는 박막의 접촉을 향상시키는데 Ti, TiN를 사용하여 Ti막상에 TiN막을 형성하는 Ti/TiN 구조로 베리어층을 형성한다.Thus, a barrier layer capable of acting as a diffusion barrier prior to the tungsten plug process is formed. The barrier layer forms a barrier layer with a Ti / TiN structure in which a TiN film is formed on the Ti film using Ti and TiN to improve contact between the thin film in contact with the tungsten film.

상기 Ti/TiN 구조에서 Ti막은 TiN막과 절연막 및 텅스텐 플러그와의 접촉을 향상시키고, 반도체 기판과 반응하여 실리사이드를 형성하여 접촉저항을 낮춘다. 또 반도체 기판과 텅스텐 플러그 계면 사이에 존재할 수 있는 불순물을 Ti막이 개더링(gathering)하여 접촉저항을 낮춘다.In the Ti / TiN structure, the Ti film improves contact between the TiN film, the insulating film, and the tungsten plug, and reacts with the semiconductor substrate to form silicide to lower the contact resistance. In addition, the Ti film gathers impurities that may exist between the semiconductor substrate and the tungsten plug interface to lower the contact resistance.

하지만 Ti막만을 베리어층으로 사용하게 되면 텅스텐 플러그 형성시 CVD내의 리덕션반응에 의해 플로린(F) 가스가 티타늄과 반응하여 TiF3과 같은 원하지 않는 반응 부산물을 생성하고, 반도체 기판과 텅스텐 플러그가 반응하여 전기적 특성을 악화시킬 수도 있어 Ti막상에 TiN막을 형성한다.However, when only the Ti film is used as the barrier layer, when the tungsten plug is formed, the Florin (F) gas reacts with titanium to produce an unwanted reaction byproduct such as TiF 3 due to the reduction reaction in the CVD, and the semiconductor substrate and the tungsten plug react. The electrical properties may be deteriorated to form a TiN film on the Ti film.

그래서 Ti/TiN 구조를 사용하고 이 구조는 금속배선 공정에서 사용되는 알루미늄의 우선 배향성을 향상시켜 금속배선의 EM(eletro-migration)에 대한 저항성을 증가시킨다.Thus, the Ti / TiN structure is used, which improves the preferential orientation of aluminum used in the metallization process, thereby increasing the resistance of the metallization to EM (eletro-migration).

이하, 첨부된 도면을 참고하여 종래의 반도체 소자의 금속 배선 형성 방법을 설명하면 다음과 같다.Hereinafter, a metal wire forming method of a conventional semiconductor device will be described with reference to the accompanying drawings.

도 1a 내지 1e는 종래의 반도체 소자의 금속 배선 형성 방법을 나타낸 공정 단면도이다.1A to 1E are cross-sectional views illustrating a method of forming metal wirings of a conventional semiconductor device.

도 1a에 도시한 바와 같이 반도체 기판(11)상에 층간 절연막(12)을 형성하고 상기 층간 절연막(12)상에 포토레지스트(13)를 도포한 후, 노광 및 현상 공정으로 포토레지스트(13)를 패터닝하여 콘택영역을 정의한다.As shown in FIG. 1A, an interlayer insulating film 12 is formed on a semiconductor substrate 11 and a photoresist 13 is applied on the interlayer insulating film 12, and then the photoresist 13 is exposed and developed. Pattern to define the contact area.

이어, 상기 패터닝된 포토레지스트(13)를 마스크로 이용해 반도체 기판(11)의 표면이 소정부분 노출되도록 상기 층간 절연막(12)을 선택적으로 제거하여 콘택홀(14)을 형성한다.Subsequently, the interlayer insulating layer 12 is selectively removed so that the surface of the semiconductor substrate 11 is exposed by using the patterned photoresist 13 as a mask to form a contact hole 14.

도 1b에 도시한 바와 같이, 상기 포토레지스트(13)을 제거하고, 상기 콘택홀(14)과 층간 절연막(12)의 전면에 Ti막(15)을 형성한 후, 도 1c에 도시한 바와 같이 상기 Ti막(15)상에 TiN막(16)을 형성한다.As shown in FIG. 1B, the photoresist 13 is removed, and a Ti film 15 is formed on the entire surface of the contact hole 14 and the interlayer insulating film 12, and as shown in FIG. 1C. A TiN film 16 is formed on the Ti film 15.

이 때 상기 Ti막(15)과 TiN막(16)은 일반적인 PVD (Physical Vapor Deposition)법을 실시하여 형성하였으나 소자가 집적화 되면서 스텝 커버리지를 향상시키기 위해 새로운 PVD법인 IMP(Ion Metal Plasma), HCM(Halo Cathode Magnetic), LTS(Long Through Sputtering)법이나 CVD(Chemical Vapor Deposition)법을 이용하여 형성한다.At this time, the Ti film 15 and the TiN film 16 were formed by performing a general physical vapor deposition (PVD) method, but new PVD methods such as ion metal plasma (IMP) and HCM It is formed using Halo Cathode Magnetic (Llo), Long Through Sputtering (LTS), or Chemical Vapor Deposition (CVD).

도 1d에 도시한 바와 같이, 상기 반도체 기판(11)에 CVD법으로 상기 콘택홀(14)을 포함한 반도체 기판(11)의 전면에 텅스텐막(17)을 형성한다.As shown in FIG. 1D, a tungsten film 17 is formed on the entire surface of the semiconductor substrate 11 including the contact hole 14 in the semiconductor substrate 11 by CVD.

도 1e에 도시한 바와 같이 상기 텅스텐막(17)을 콘택홀(14)의 내부에만 남도록 상기 TiN막(16)을 식각중단층으로 하여 전면에 에치백 또는 CMP(Chemical Mechanical Polishing)공정을 실시하여 텅스텐 플러그(17a)를 형성한 후, 상기 텅스텐 플러그(17a)를 포함한 반도체 기판(11)의 전면에 알루미늄막을 증착하고 포토 및 식각 공정을 통해 알루미늄막을 선택적으로 제거하여 알루미늄 배선(18)을 형성한다.As shown in FIG. 1E, an etch back or chemical mechanical polishing (CMP) process is performed on the entire surface by using the TiN film 16 as an etch stop layer so that the tungsten film 17 remains only inside the contact hole 14. After forming the tungsten plug 17a, an aluminum film is deposited on the entire surface of the semiconductor substrate 11 including the tungsten plug 17a, and the aluminum film 18 is selectively removed through photo and etching processes to form the aluminum wiring 18. .

그러나 상기와 같은 종래의 반도체 소자의 금속 배선 형성 방법에 있어서 다음과 같은 문제점이 있다.However, there is the following problem in the metal wiring forming method of the conventional semiconductor device as described above.

첫째, 소자의 집적도가 증가함에 따라 콘택홀의 종횡비가 10:1 이상으로 커져 새로운 PVD법인 IMP, HCM, LTS법으로도 10%이하의 취약한 스텝 커버리지를 나타내 PVD법이 한계에 이르렀다.First, as the integration of devices increases, the aspect ratio of the contact hole increases to 10: 1 or more, resulting in a weak step coverage of less than 10% even with the new PVD methods IMP, HCM, and LTS.

둘째, 스텝 커버리지를 향상시키기 위해 도입된 CVD법은 공정 비용과 능률(capability) 측면에서 취약하다.Second, the CVD method introduced to improve step coverage is vulnerable in terms of process cost and capacity.

본 발명은 상기와 같은 문제점을 해결하기 위해 안출한 것으로 반도체 소자의 고집적화에 따른 콘택홀의 종횡비가 커져 베리어층 구조가 직면하고 있는 스텝 커버리지 문제나 공정 비용 측면에서 우수한 반도체 소자의 금속 배선 형성 방법을제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems and provides a method for forming a metal wiring of a semiconductor device excellent in terms of step coverage problems and process costs faced by a barrier layer structure due to an increase in aspect ratio of contact holes due to high integration of semiconductor devices. Its purpose is to.

도 1a 내지 1e는 종래의 반도체 소자의 금속 배선 형성 방법을 나타낸 공정 단면도1A to 1E are cross-sectional views illustrating a method of forming metal wirings in a conventional semiconductor device.

도 2a 내지 2e는 본 발명의 반도체 소자의 금속 배선 형성 방법을 나타낸 공정 단면도2A to 2E are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device of the present invention.

도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings

21 : 반도체 기판 22 : 층간 절연막21 semiconductor substrate 22 interlayer insulating film

23 : 포토레지스트 24 : 콘택홀23: photoresist 24: contact hole

25 : Ti막 26 : 제 1 TiN막25 Ti film 26 First TiN film

27 : 제 2 TiN막 28 : 텅스텐막27: second TiN film 28: tungsten film

28a : 텅스텐 플러그 29 : 알루미늄 배선28a: tungsten plug 29: aluminum wiring

상기와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 소자의 금속 배선 형성 방법은 반도체 기판상에 절연막을 형성하는 단계와, 상기 반도체 기판의 표면이 소정 부분 노출되도록 상기 절연막을 선택적으로 제거하여 콘택홀을 형성하는 단계와, 상기 콘택홀을 포함한 반도체 기판의 전면에 제 1 금속막을 형성하는 단계와, 상기 제 1 금속막상에 CVD 및 PVD 법으로 제 1, 제 2 베리어 금속막을 차례로 형성하는 단계와, 상기 콘택홀 내부에 금속 플러그를 형성하는 단계와, 그리고 상기 금속 플러그를 통해 반도체 기판과 전기적으로 연결되는 금속 배선을 형성하는 단계를 포함하여 형성함을 특징으로 한다.In accordance with an aspect of the present invention, there is provided a method of forming a metal wire in a semiconductor device, the method including forming an insulating film on a semiconductor substrate, and selectively removing the insulating film to expose a predetermined portion of the surface of the semiconductor substrate. Forming a first metal film on the entire surface of the semiconductor substrate including the contact hole, sequentially forming first and second barrier metal films on the first metal film by CVD and PVD; And forming a metal plug in the contact hole, and forming a metal wire electrically connected to the semiconductor substrate through the metal plug.

이하, 첨부된 도면을 참고하여 본 발명에 의한 반도체 소자의 금속 배선 형성 방법을 상세히 설명하면 다음과 같다.Hereinafter, a metal wire forming method of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 2e는 본 발명에 의한 반도체 소자의 금속 배선 형성 방법을 나타낸 공정 단면도이다.2A to 2E are cross-sectional views illustrating a method for forming metal wirings of a semiconductor device according to the present invention.

도 2a에 도시한 바와 같이 반도체 기판(21)상에 층간 절연막(22)을 형성하고 상기 층간 절연막(22)상에 포토레지스트(23)를 도포한 후, 노광 및 현상 공정으로 포토레지스트(23)를 패터닝하여 콘택영역을 정의한다.As shown in FIG. 2A, the interlayer insulating film 22 is formed on the semiconductor substrate 21, and the photoresist 23 is applied on the interlayer insulating film 22, and then the photoresist 23 is exposed and developed. Pattern to define the contact area.

이어, 상기 패터닝된 포토레지스트(23)를 마스크로 이용해 반도체 기판(21)의 표면이 소정부분 노출되도록 상기 층간 절연막(22)을 선택적으로 제거하여 콘택홀(24)을 형성한다.Subsequently, the interlayer insulating layer 22 is selectively removed so that the surface of the semiconductor substrate 21 is exposed by using the patterned photoresist 23 as a mask to form a contact hole 24.

도 2b에 도시한 바와 같이, 상기 포토레지스트(23)를 제거하고, 상기 콘택홀(24)을 포함한 반도체 기판(21)의 전면에 Ti막(25)을 새로운 PVD법 또는 CVD법을 이용하여 형성하고, 상기 Ti막(25)상에 CVD법을 이용하여 제 1 TiN막(26)을 형성한다. 이 때 상기 Ti막(25)과 제 1 TiN막(26)은 확산 베리어나 전기적 특성을 만족하는 최소한의 두께로 형성한다.As shown in FIG. 2B, the photoresist 23 is removed, and a Ti film 25 is formed on the entire surface of the semiconductor substrate 21 including the contact hole 24 using a new PVD method or a CVD method. Then, the first TiN film 26 is formed on the Ti film 25 by the CVD method. At this time, the Ti film 25 and the first TiN film 26 are formed to a minimum thickness satisfying the diffusion barrier or electrical characteristics.

여기서 최소한의 두께란 콘택리스의 10%이하의 두께를 말하며 예를 들어 콘택리스가 1㎛인 경우는 0.1㎛이하를 최소한의 두께라고 한다.Here, the minimum thickness refers to a thickness of 10% or less of the contactless. For example, when the contactless is 1 µm, the thickness is 0.1 µm or less.

도 2c에 도시한 바와 같이, 상기 제 1 TiN막(26)상에 PVD법을 이용하여 제 2 TiN막(27)을 형성한다.As shown in Fig. 2C, a second TiN film 27 is formed on the first TiN film 26 by the PVD method.

여기서, 상기 제 1, 제 2 TiN막(26,27)은 10nm이상의 두께로 형성한다. 그 이유는 이후에 형성되는 텅스텐막 증착시 콘택홀(24)이외의 영역에서 텅스텐막의 필링(peeling) 유발을 방지하고, 텅스텐막 증착 후 평탄화 공정이 진행되는데 상기 제 1, 제 2 TiN막(26,27)은 식각중단층으로 사용되기 때문이다.Here, the first and second TiN films 26 and 27 are formed to a thickness of 10 nm or more. The reason for this is to prevent the peeling of the tungsten film in a region other than the contact hole 24 when the tungsten film is formed later, and to planarize after deposition of the tungsten film, the first and second TiN films 26 (27) is used as an etch stop layer.

한편, 상기 제 2 TiN막(27)은 콘택홀(24)의 내부에는 형성되지 않고 콘택홀(24) 이외의 제 1 TiN막(26)상에만 형성된다.On the other hand, the second TiN film 27 is not formed inside the contact hole 24 but is formed only on the first TiN film 26 other than the contact hole 24.

그 이유는 콘택홀의 종횡비가 10:1이상 CD가 0.30㎛이하인 콘택홀(24)내부의 제 1 TiN막(26)상에 PVD법으로 제 2 TiN막(27)을 증착하면 도포성이 열악하여 콘택홀(24)내부에는 제 2 TiN막(27)이 증착되지 않는다. 그래서 이 점을 이용하여 PVD법으로 제 2 TiN막(27)을 원하는 두께만큼 상기 콘택홀(24)내부의 제 1 TiN막(26)을 제외한 제 1 TiN막(26)상에 형성한다.The reason is that when the second TiN film 27 is deposited by the PVD method on the first TiN film 26 inside the contact hole 24 in which the aspect ratio of the contact hole is 10: 1 or more and CD is 0.30 μm or less, the coating property is poor. The second TiN film 27 is not deposited inside the contact hole 24. Thus, using this point, the second TiN film 27 is formed on the first TiN film 26 except for the first TiN film 26 inside the contact hole 24 by the desired thickness.

도 2d에 도시한 바와 같이, 상기 반도체 기판(21)에 CVD법으로 상기 콘택홀(24)을 포함한 반도체 기판(21)의 전면에 텅스텐막(28)을 형성한다.As shown in FIG. 2D, a tungsten film 28 is formed on the entire surface of the semiconductor substrate 21 including the contact hole 24 in the semiconductor substrate 21 by CVD.

도 2e에 도시한 바와 같이, 상기 텅스텐막(28)을 콘택홀(24) 내부에만 남도록 상기 제 1, 제 2 TiN막(26,27)을 식각중단층으로 하여 전면에 에치백 또는 CMP 공정을 실시하여 텅스텐 플러그(28a)를 형성한 후, 상기 텅스텐 플러그(28a)를 포함한 반도체 기판(21)의 전면에 알루미늄막을 증착하고 포토 및 식각 공정을 통해 알루미늄막을 선택적으로 제거하여 알루미늄 배선(29)을 형성한다.As shown in FIG. 2E, an etch back or CMP process is performed on the entire surface of the first and second TiN layers 26 and 27 as an etch stop layer so that the tungsten layer 28 remains only in the contact hole 24. After forming the tungsten plug 28a, an aluminum film is deposited on the entire surface of the semiconductor substrate 21 including the tungsten plug 28a, and the aluminum wire 29 is selectively removed by performing a photo and etching process. Form.

이상에서 설명한 바와 같이 본 발명에 의한 반도체 소자의 금속 배선 형성 방법에 있어서 다음과 같은 효과가 있다.As described above, the metal wiring formation method of the semiconductor device according to the present invention has the following effects.

즉, 소자의 고집적화로 콘택홀의 종횡비가 10:1이상으로 커져 Ti/TiN막을 형성할 때 PVD법으로 스텝 커버리지를 개선하는데 한계가 있어, CVD법으로 확산 베리어나 전기적 특성을 만족하는 최소한의 두께만큼의 TiN막을 먼저 증착하고 나머지 요구되는 TiN막의 두께는 일반적인 PVD법으로 형성함으로서 공정 비용과 능률(capability) 측면에서 효과를 가져올 수 있고, 스텝 커버리지도 향상시킬 수 있다.In other words, due to the high integration of the device, the aspect ratio of the contact hole is increased to 10: 1 or more, so that there is a limit to improving the step coverage by the PVD method when forming the Ti / TiN film. The TiN film is deposited first, and the remaining required thickness of the TiN film is formed by a general PVD method, which can bring about an effect in terms of process cost and capacity, and improve step coverage.

Claims (3)

반도체 기판상에 절연막을 형성하는 단계;Forming an insulating film on the semiconductor substrate; 상기 반도체 기판의 표면이 소정 부분 노출되도록 상기 절연막을 선택적으로 제거하여 콘택홀을 형성하는 단계;Forming a contact hole by selectively removing the insulating layer to expose a portion of the surface of the semiconductor substrate; 상기 콘택홀을 포함한 반도체 기판의 전면에 제 1 금속막을 형성하는 단계;Forming a first metal film on an entire surface of the semiconductor substrate including the contact hole; 상기 제 1 금속막상에 CVD 및 PVD 법으로 제 1, 제 2 베리어 금속막을 차례로 형성하는 단계;Sequentially forming first and second barrier metal films on the first metal film by CVD and PVD methods; 상기 콘택홀 내부에 금속 플러그를 형성하는 단계; 그리고Forming a metal plug in the contact hole; And 상기 금속 플러그를 통해 반도체 기판과 전기적으로 연결되는 금속 배선을 형성하는 단계를 포함하여 형성함을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.And forming metal wires electrically connected to the semiconductor substrate through the metal plugs. 제 1항에 있어서,The method of claim 1, 제 1 금속막은 PVD 또는 CVD 법을 이용하여 형성하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The first metal film is formed by PVD or CVD method. 제 1항에 있어서,The method of claim 1, 상기 제 1, 제 2 베리어 금속막은 10nm이상의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.And the first and second barrier metal films are formed to a thickness of 10 nm or more.
KR1020000005195A 2000-02-02 2000-02-02 Method for Forming Metal Line of Semiconductor Device KR20010077405A (en)

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