KR20010065329A - Method For Forming The Fuse Of Semiconductor Device - Google Patents

Method For Forming The Fuse Of Semiconductor Device Download PDF

Info

Publication number
KR20010065329A
KR20010065329A KR1019990065202A KR19990065202A KR20010065329A KR 20010065329 A KR20010065329 A KR 20010065329A KR 1019990065202 A KR1019990065202 A KR 1019990065202A KR 19990065202 A KR19990065202 A KR 19990065202A KR 20010065329 A KR20010065329 A KR 20010065329A
Authority
KR
South Korea
Prior art keywords
fuse
metal layer
via hole
wiring
semiconductor device
Prior art date
Application number
KR1019990065202A
Other languages
Korean (ko)
Other versions
KR100334970B1 (en
Inventor
장윤영
Original Assignee
박종섭
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 박종섭, 주식회사 하이닉스반도체 filed Critical 박종섭
Priority to KR1019990065202A priority Critical patent/KR100334970B1/en
Publication of KR20010065329A publication Critical patent/KR20010065329A/en
Application granted granted Critical
Publication of KR100334970B1 publication Critical patent/KR100334970B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H01L23/5258—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE: A method for manufacturing a fuse is to control the thickness of a metal fuse, thereby securing a laser cutting process margin of a repair device, and to perform a pad/repair etch concurrently, thereby shortening a process time. CONSTITUTION: A fuse is provided in a semiconductor device having a plurality of memory devices. When any memory device is wrongly operated, the fuse is physically cut. An interlayer dielectric layer is formed between a (n+1)th interconnection metal layer and an n-th interconnection metal layer(51) both of which are formed in a region other than the interconnection region. The interlayer dielectric layer is etched to an interconnection via hole for connecting the (n+1)th interconnection metal layer and the n-th interconnection metal layer and a fuse via hole at the same time. A metal layer having a high melting point is formed on the resultant structure having the via holes. The metal layer is etched back to form a plug(56) and a fuse spacer(57) on an inner wall of the fuse via hole at the same time.

Description

반도체소자의 퓨즈 제조방법 { Method For Forming The Fuse Of Semiconductor Device }Method for Forming the Fuse Of Semiconductor Device

본 발명은 반도체 소자의 제조방법에 관한 것으로서, 특히 MML 소자와 같은 다층 금속배선을 구비하는 반도체 소자에서 배선용 금속층간을 연결하기 위한 플러그와 퓨즈를 동시에 형성할 수 있는 반도체 소자의 퓨즈 박스 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a fuse box of a semiconductor device capable of simultaneously forming a plug and a fuse for connecting between metal layers for wiring in a semiconductor device having a multi-layered metal wiring such as an MML device. It is about.

일반적으로, 가장 널리 사용되는 메모리 소자인 디램(DRAM)은 제조된 칩 내부에 부분적으로 동작을 하지 않는 메모리 셀들이 존재하게 되며, 이러한 메모리 셀들은 리페어(repair) 과정을 통해 칩 제조시에 미리 만들어둔 여분의 셀들로 교체함으로써 실제 칩은 동작상에 아무런 영향이 없도록 하고 있으며, 이러한 방법을 이용함으로써 제조된 칩의 수율을 높이고 있다.In general, DRAM, the most widely used memory device, includes memory cells that do not operate partially inside a manufactured chip, and these memory cells are pre-made at the time of chip manufacturing through a repair process. By replacing the spare cells, the actual chip has no effect on operation, and by using this method, the yield of the manufactured chip is increased.

이때, 리페어가 이루어지는 부분을 칩상에서 퓨즈박스라 부르며, 대개의 경우 제1폴리실리콘층이나 제2폴리실리콘층으로 사용하여 왔으며, 이 폴리실리콘층을 레이저를 이용하여 기계적으로 끊음으로써 퓨즈박스 내에서 리페어가 이루어지도록 하고 있다.At this time, the repair part is called a fuse box on the chip, and in most cases, it has been used as a first polysilicon layer or a second polysilicon layer, and the polysilicon layer is mechanically cut by using a laser to cut the fuse box. Repairs are being made.

그리고 디램은 일반적으로 2층의 배선용 금속층을 사용하고, 평탄화를 위해 CTR(Cell Topology Reduction)이 SOG(Spin On Glass)를 사용하기 때문에 상기 퓨즈박스 내에 존재하는 절연층을 제거하는 리페어 식각공정에 큰 문제가 없었다.In general, DRAM uses two layers of wiring metal layers, and CTR (Cell Topology Reduction) uses SOG (Spin On Glass) for planarization, which is a great value for the repair etching process to remove the insulating layer existing in the fuse box. there was no problem.

그러나, 로직(logic)과 디램을 단일 웨이퍼에서 구현하여 속도를 향상시키고 제조단가를 절감할 수 있는 MML 소자에 경우에는, 도 1a 에 도시한 바와 같이 배선을 위한 금속층이 3개층(15, 16, 17, 18) 이상이 되므로 패드/리페어 식각 마스크(20)를 이용하여 도 1b 와 같은 패드/리페어 식각을 실시하면 상기보호막(19)과 층간절연막(14)의 두께가 5000Å 이상으로 제거량이 급격히 증가되며, 그 결과 도 1c 의 A에 도시한 바와 같이 최상부의 금속층(18)에서 식각되어 나온 금속 폴리머가 식각된 부분에 식각저지막(31)을 형성하면서 식각 타겟(target)에 이르지 못하게 된다.However, in the case of MML devices that can implement logic and DRAM on a single wafer to improve speed and reduce manufacturing costs, as shown in FIG. 1A, three metal layers 15 and 16 for wiring are provided. 17, 18) or more, so when the pad / repair etching is performed using the pad / repair etching mask 20 as shown in FIG. 1B, the removal amount of the protective layer 19 and the interlayer insulating layer 14 is 5000 kÅ or more, and the removal amount is rapidly increased. As a result, as illustrated in A of FIG. 1C, the metal polymer etched from the uppermost metal layer 18 may not reach the etch target while forming the etch stop layer 31 on the etched portion.

또한 상기 퓨즈박스영역의 절연막을 원하는 두께만큼 얻기 위해 상기 식각저지막(31)을 제거하고 계속하여 패드/리페어 식각을 실시하게 되면 도 1d 의 B에 도시한 바와 같이 패드 영역의 최상부 금속층(18)이 남지 않고 그 하부의 층간절연막이 노출되는등, 충분한 공정마진(margin) 확보가 어렵고, 이러한 원하지 않는 금속 폴리머의 형성이나 금속층에 생기는 물리적인 공격(attack)과 이때 받는 플라즈마 손상에 의한 안테나 효과는 트랜지스터의 특성을 저하시키고 수율을 감소시킬 뿐만 아니라 소자 자체에 문제를 발생시키게 되며, 이를 방지하기 위해 패드 식각과 리페어 식각을 각기 별도로 시행하면 공정시간이 매우 길어지게 되어 생산성을 저하시키는 문제점을 지닌다.In addition, when the etch stop layer 31 is removed and the pad / repair etch is continued to obtain the insulating film of the fuse box region to a desired thickness, the uppermost metal layer 18 of the pad region is shown in FIG. It is difficult to secure sufficient process margin, such as exposing the lower interlayer insulating film, and the antenna effect due to the formation of undesired metal polymer or physical attack on the metal layer and the plasma damage received at this time In addition to degrading the characteristics of the transistor and reducing the yield, it also causes a problem in the device itself. To prevent this, if the pad etching and the repair etching are performed separately, the process time becomes very long, which causes a problem of lowering productivity.

본 발명적은 이러한 점을 감안하여 안출한 것으로서, 상기와 같은 종래 기술의 문제점을 해결하기 위하여 금속퓨즈의 두께를 조절가능하도록 하여 리페어장치의 레이저 컷팅 공정마진을 확보하고 다층의 배선용금속층을 사용하는 소자에서도 패드/리페어 식각을 동시에 실시하여 공정시간을 단축시킬 수 있는 반도체 소자의 퓨즈박스 제조방법을 제공하는 것이 목적이다.The present invention has been made in view of this point, in order to solve the problems of the prior art as described above, by adjusting the thickness of the metal fuse to ensure the laser cutting process margin of the repair apparatus and using a multi-layer metal layer for wiring An object of the present invention is to provide a method of manufacturing a fuse box of a semiconductor device capable of simultaneously performing pad / repair etching, thereby shortening process time.

도 1a 내지 도 1d 는 종래의 반도체 소자의 퓨즈제조방법을 도시한 단면도들이고,1A to 1D are cross-sectional views illustrating a fuse manufacturing method of a conventional semiconductor device.

도 2a 내지 도 2f 는 본 발명의 일시예에 따른 반도체 소자의 퓨즈제조방법을 도시한 단면도 이다.2A through 2F are cross-sectional views illustrating a method of manufacturing a fuse of a semiconductor device in accordance with an embodiment of the present invention.

*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

51 : n번째 배선용 금속층 52 : 퓨즈박스영역내 도전층51: metal layer for nth wiring 52: conductive layer in fuse box area

53 : 층간절연막 54 : 포토레지스트 패턴53 interlayer insulating film 54 photoresist pattern

55 : 고융점 금속층 56 : 플러그55: high melting point metal layer 56: plug

57 : 스페이서57: spacer

상기 목적을 달성하기 위하여 본 발명은, 다수개의 메모리 소자들과, 상호 적층되는 다수개의 배선용 금속층들과, 상기 메모리 소자들 및 배선용 금속층들과 일정간격 이격되어 있으며 상기 다수개의 메모리 소자중 임의의 메모리 소자의 오동작시 물리적으로 컷팅하기 위한 퓨즈를 구비하는 반도체 소자에 있어서, 상기 배선부분을 제외한 영역에서 n+1(n = 1 이상의 정수)번째 배선용 금속층과 하부의 n번째 배선용 금속층간을 절연시키기 위한 층간절연막을 형성하는 단계와, 상기 층간절연막을 식각하여 n번째 배선용 금속층과 n+1번째 배선용 금속층을 연결하기 위한 배선용 비아홀을 형성함과 동시에 퓨즈용 비아홀을 형성하는 단계와, 상기 비아홀들이 형성된 결과물의 전면에 고융점 금속층을 형성하는 단계와, 상기 고융점 금속층을 에치백하여 플러그를 형성함과 동시에 상기 퓨즈용 비아홀 내측벽에 스페이서를 형성하는 단계를 포함하여 이루어지는 반도체 소자의 퓨즈제조방법을 제공함으로써 달성된다.In order to achieve the above object, the present invention provides a plurality of memory devices, a plurality of wiring metal layers stacked on each other, and a predetermined distance from the memory devices and the wiring metal layers, and any one of the plurality of memory devices. A semiconductor device having a fuse for physically cutting a device in malfunction, wherein the semiconductor device is to insulate between an n + 1 (n = 1 integer) wiring metal layer and a lower n-th wiring metal layer in a region excluding the wiring portion. Forming an interlayer insulating film, forming a via via hole for connecting the n-th wiring metal layer and the n + 1 th wiring metal layer by etching the interlayer insulating film, and forming a fuse via hole at the same time; Forming a high melting point metal layer on the front surface of the metal layer; And simultaneously forming him by forming a spacer on the inner walls of the via hole for the fuse is achieved by providing a method of manufacturing a semiconductor fuse element made.

이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세하게 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2f 는 본 발명의 일실시예에 따른 반도체 소자의 퓨즈제조방법을 도시한 것으로, 다수개의 메모리 소자를 포함한 능동/수동 소자를 제조하는 과정과 상기 능동/수동 소자를 배선하기 위한 최하부의 배선용 금속층(51)을 제조하는 과정은 일반적이므로 설명의 편의상 생략하고 이후의 공정을 설명하면 다음과 같다.2A to 2F illustrate a method of manufacturing a fuse of a semiconductor device according to an embodiment of the present invention, and a process of manufacturing an active / passive device including a plurality of memory devices and a lowermost part for wiring the active / passive device The process of manufacturing the wiring metal layer 51 is generally omitted for convenience of explanation and the following process will be described below.

먼저 도 2a에 도시된 바와 같이, 상기 능동/수동 소자와 배선용 금속층(51)이 형성되어 있는 구조물의 전면에 층간절연막(53)을 형성하고, 이어서 상기 층간절연막(53) 위에 포토레지스트 패턴(54)를 형성한다. 이때 상기 포토레지스트 패턴(54)는 상기 배선용 금속층(51)과 퓨즈박스영역에서 오픈되도록 하며, 특히 상기 퓨즈박스 영역의 포토레지스트는 넓게 오픈되도록 한다. 미설명부호 52는 퓨즈박스영역내 도전층이다.First, as shown in FIG. 2A, an interlayer insulating film 53 is formed on the entire surface of the structure in which the active / passive element and the metal layer 51 for wiring are formed. Then, a photoresist pattern 54 is formed on the interlayer insulating film 53. ). In this case, the photoresist pattern 54 may be opened in the wiring metal layer 51 and the fuse box region, and in particular, the photoresist in the fuse box region may be widely opened. Reference numeral 52 is a conductive layer in the fuse box region.

도 2b 및 도 2c에 도시된 바와 같이, 상기 포토레지스트 패턴(54)을 마스크로 하여 상기 층간절연막(53)을 식각함으로써 배선용 비아홀과 퓨즈용 비아홀을 형성한 후 상기 포토레지스트 패턴(54)을 제거한다. 이때 상기 퓨즈용 비아홀의 폭은 퓨즈의 피치(pitch)가 된다.As shown in FIGS. 2B and 2C, the interlayer insulating layer 53 is etched using the photoresist pattern 54 as a mask to form a via via and a fuse via hole, and then the photoresist pattern 54 is removed. do. In this case, the width of the via via hole for the fuse is a pitch of the fuse.

그리고, 도 2d에 도시된 바와 같이, 상기 포토레지스트 패턴 제거 후 상기 배선용 비아홀과 퓨즈용 비아홀이 형성되어 있는 구조물의 전면에 예를들면 텅스텐(W)을 증착시켜 고융점 금속층(55)을 형성한다. 이때 상기 고융점 금속층(55)의 두께를 조절하여 퓨즈의 두께를 조절할 수 있다.As shown in FIG. 2D, after removing the photoresist pattern, for example, tungsten (W) is deposited on the entire surface of the structure in which the wiring via hole and the fuse via hole are formed to form a high melting point metal layer 55. . At this time, the thickness of the fuse may be adjusted by adjusting the thickness of the high melting point metal layer 55.

도 2f에 도시된 바와 같이, 상기 고융점 금속층(55)을 전면 에치백하여 n번째 배선용 금속층(51)과 그 상부에 형성될 n+1 번째 금속층을 연결하기 위한 플러그(56)를 형성하고, 동시에 제거되지 않고 남게 되는 고융점 금속층 물질로 상기 퓨즈용 비아홀의 내측벽에 퓨즈로 사용하기 위한 스페이서(57)를 형성한다. 이때 상기 에치백 공정은 상기 배선용 금속층간의 연결이 이루어지는 부분에는 비아홀을 제외한 윗부분의 고융점 금속층이 모두 날아갈 정도로 과도식각(over etch)이 이루어져야 한다. 한편 이러한 에치백의 식각정도에 따라 상기 스페이서(57)로 이루어지는 퓨즈의 두께를 조절할 수 있다.As shown in FIG. 2F, the high melting point metal layer 55 is etched back to form a plug 56 for connecting the n-th wiring metal layer 51 and the n + 1 th metal layer to be formed thereon. At the same time, a spacer 57 for use as a fuse is formed on the inner wall of the via hole for the fuse using a high melting point metal layer material which is left without being removed. At this time, the etch back process should be overetched to the extent that the high melting point metal layers of the upper portions except the via holes are blown to the portions where the wiring metal layers are connected. Meanwhile, the thickness of the fuse made of the spacer 57 may be adjusted according to the etching degree of the etch back.

상기한 바와 같이, 본 발명에 따른 반도체 소자의 퓨즈제조방법을 이용하면, 배선용 금속층간을 연결하기 위한 플러그 형성시 배선용 비아홀과 퓨즈용 비아홀을 동시에 형성하고, 상기 비아홀들을 덮도록 고융점 금속층을 형성한 후 에치백시켜 플로그를 형성함과 동시에 상기 퓨즈용 비아홀의 내측벽에 남은 고융점 금속층으로 퓨즈를 형성하기 때문에 상기 퓨즈용 비아홀의 폭과 고융점 금속층의 두께 및 에치백 정도로 퓨즈의 피치와 두께를 조절가능하도록 하여 리페어장치의 레이저 컷팅 공정마진을 확보하고, 이에 따라 다층의 배선용금속층을 사용하는 소자에서도 패드/리페어 식각을 동시에 실시하여 공정시간을 단축시킬 수 있는 매우 유용하고 효과적인 발명이다.As described above, when the fuse manufacturing method of the semiconductor device according to the present invention is used, a wiring via hole and a fuse via hole are simultaneously formed when a plug for connecting the wiring metal layers is formed, and a high melting point metal layer is formed to cover the via holes. After forming the plug by etching back, the fuse is formed of the high melting point metal layer remaining on the inner wall of the via hole for the fuse. Therefore, the width of the via hole for the fuse, the thickness of the high melting point metal layer, and the pitch of the fuse are about the same. It is possible to control the laser cutting process margin of the repair apparatus, and accordingly according to the device using a multi-layered metal layer for the pad / repair etching is a very useful and effective invention that can shorten the process time.

Claims (3)

다수개의 메모리 소자들과, 상호 적층되는 다수개의 배선용 금속층들과, 상기 메모리 소자들 및 배선용 금속층들과 일정간격 이격되어 있으며 상기 다수개의 메모리 소자중 임의의 메모리 소자의 오동작시 물리적으로 컷팅하기 위한 퓨즈를 구비하는 반도체 소자에 있어서,A plurality of memory elements, a plurality of wiring metal layers stacked on each other, and a fuse spaced apart from the memory elements and the wiring metal layers at a predetermined interval and for physically cutting a malfunction of any one of the plurality of memory elements In the semiconductor device comprising: 배선부분을 제외한 영역에서 n+1(n = 1 이상의 정수)번째 배선용 금속층과 하부의 n번째 배선용 금속층간을 절연시키기 위한 층간절연막을 형성하는 단계와;Forming an interlayer insulating film for insulating between the n + 1 (n = 1 integer) wiring metal layer and the lower n-th wiring metal layer in the region excluding the wiring portion; 상기 층간절연막을 식각하여 n번째 배선용 금속층과 n+1번째 배선용 금속층을 연결하기 위한 배선용 비아홀을 형성함과 동시에 퓨즈용 비아홀을 형성하는 단계와;Etching the interlayer insulating film to form a wiring via hole for connecting an n-th wiring metal layer and an n + 1th wiring metal layer, and simultaneously forming a via via hole for the fuse; 상기 비아홀들이 형성된 결과물의 전면에 고융점 금속층을 형성하는 단계와;Forming a high melting point metal layer on an entire surface of the resultant product in which the via holes are formed; 상기 고융점 금속층을 에치백하여 플러그를 형성함과 동시에 상기 퓨즈용 비아홀 내측벽에 퓨즈용 스페이서를 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 퓨즈제조방법.And forming a fuse spacer on an inner side wall of the fuse via hole by etching the high melting point metal layer to form a plug. 제 1 항에 있어서, 상기 퓨즈용 비아홀의 폭에 따라 상기 퓨즈용 스페이서의 피치를 조절하는 것을 특징으로 하는 반도체소자의 퓨즈제조방법.The method of manufacturing a fuse of a semiconductor device according to claim 1, wherein a pitch of the spacer for the fuse is adjusted according to a width of the fuse via hole. 제 1 항에 있어서, 상기 고융점 금속층의 두께와 에치백 정도에 따라 상기퓨즈용 스페이서의 두께를 조절하는 것을 특징으로 하는 반도체소자의 퓨즈제조방법.The method of manufacturing a fuse of a semiconductor device according to claim 1, wherein the thickness of the spacer for the fuse is adjusted according to the thickness of the high melting point metal layer and the degree of etch back.
KR1019990065202A 1999-12-29 1999-12-29 Method For Forming The Fuse Of Semiconductor Device KR100334970B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019990065202A KR100334970B1 (en) 1999-12-29 1999-12-29 Method For Forming The Fuse Of Semiconductor Device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019990065202A KR100334970B1 (en) 1999-12-29 1999-12-29 Method For Forming The Fuse Of Semiconductor Device

Publications (2)

Publication Number Publication Date
KR20010065329A true KR20010065329A (en) 2001-07-11
KR100334970B1 KR100334970B1 (en) 2002-05-04

Family

ID=19632406

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019990065202A KR100334970B1 (en) 1999-12-29 1999-12-29 Method For Forming The Fuse Of Semiconductor Device

Country Status (1)

Country Link
KR (1) KR100334970B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100873810B1 (en) * 2002-07-06 2008-12-11 매그나칩 반도체 유한회사 Method for fabricating image sensor having fuse box
US7763887B2 (en) 2006-09-04 2010-07-27 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100873810B1 (en) * 2002-07-06 2008-12-11 매그나칩 반도체 유한회사 Method for fabricating image sensor having fuse box
US7763887B2 (en) 2006-09-04 2010-07-27 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
US8071469B2 (en) 2006-09-04 2011-12-06 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same

Also Published As

Publication number Publication date
KR100334970B1 (en) 2002-05-04

Similar Documents

Publication Publication Date Title
KR100335498B1 (en) Fuse area structure in semiconductor device and forming method thereof
KR100351050B1 (en) Forming method of fuse area in semiconductor device
KR100442868B1 (en) Forming method of fuse in semiconductor device
KR100334970B1 (en) Method For Forming The Fuse Of Semiconductor Device
KR20000035223A (en) Fuse layout for improved fuse blow process window
KR100379508B1 (en) Method for manufacturing of fuse
KR20010065692A (en) Method for manufacturing fuse box of a semiconductor device
KR100357302B1 (en) Manufacturing method for semiconductor device
KR20090070826A (en) Semiconductor device with fuse and method for manufacturing the same
KR101073125B1 (en) Semiconductor memory device and method for fabricating the same
KR100734251B1 (en) Method for forming fuse line opening portion of semiconductor device
JPH1131748A (en) Semiconductor device and manufacture of the same
KR20040008707A (en) Semiconductor device and Method for fabricating the same
KR20020024919A (en) Method of manufacturing fuse box in semiconductor device
KR100998950B1 (en) Semiconductor device with fuse and method for manufacturing the same
KR20020024460A (en) Method for forming fuse in Semiconductor device
KR20010038436A (en) Method for opening bit line fuse
KR20050051503A (en) Fuse boxes having fuse retard layer and fuse plug pattern, and fabrication methods thereof
KR20050102009A (en) Mtehod for fabricating semiconductor memory device
KR20020075002A (en) Semiconductor Device with Fuse Region and Method of Forming the Same
KR20030035632A (en) Method of fabricating semiconductor device having fuse regions
KR20010061081A (en) Manufacturing method for fuse of semiconductor device
KR20020027051A (en) Method for forming semiconductor device having fuse line parallel to direction of wafer rotation
KR20010005082A (en) A method for fabricating semiconductor memory device for increasing throughput
KR20060011479A (en) Semiconductor memory device and method for fabricating the same

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20050322

Year of fee payment: 4

LAPS Lapse due to unpaid annual fee