KR20010065305A - Method of manufacturing a flash memory device - Google Patents

Abstract

PURPOSE: A method for manufacturing a flash memory device is to prevent a bridge between patterns and a short failure and prevent a charge loss of a gate oxide layer, thereby improving a reliability of the device. CONSTITUTION: A cell region and a peripheral region are defined in a semiconductor substrate(30). A buffer oxide layer(31) and a gate mask are sequentially formed on the semiconductor substrate. The cell region and the peripheral region of the semiconductor substrate are exposed using an etching process to thereby form a trench. A gate oxide layer(34), the first polysilicon layer(35) and an ONO layer(36) are sequentially formed on an entire structure. An etch stop mask (37) is formed, and the ONO layer disposed in the peripheral region is removed. The etch stop mask is removed. The second polysilicon layer(37) is deposited on an entire structure, and the buffer oxide layer is etched to thereby form a gate electrode(38) within the trench. A source/drain junction region is formed.

Description

Method of manufacturing a flash memory device

The present invention relates to a method of manufacturing a flash memory device, and more particularly, to a method of manufacturing a flash memory device capable of eliminating a step between a cell region and a peri region.

In a typical flash memory device manufacturing process, a difference occurs after a subsequent process due to a difference in structure between a cell region and a peripheral region.

Referring to the accompanying drawings, a method of manufacturing a conventional flash memory device is as follows.

1A to 1C are cross-sectional views of devices for explaining a method of manufacturing a conventional flash memory device.

Referring to FIG. 1A, after the cell region and the peripheral region are defined in the semiconductor substrate 10, the gate oxide layer 11 and the first polysilicon layer 12 are formed, and an etching process using a floating gate mask is performed. The ONO film 13 and the second polysilicon film 14 are sequentially deposited on the entire upper surface, the photoresist pattern 15 is formed in the cell region, and then the peripheral region is etched using the photoresist pattern 15 as a mask. The second polysilicon film 14 and the ONO film 13 are removed.

Referring to FIG. 1B, the gate mask 16 is formed after removing the photoresist pattern 15.

Referring to FIG. 1C, after the gate electrode 17 is formed by an etching process using the gate mask 16, the gate mask 16 is removed.

In the above, in the gate electrode 17 of the cell region, the first polysilicon film 12 becomes a floating gate of the flash memory device, and the second polysilicon film 14 becomes a control gate of the flash memory device.

A junction is then formed by a subsequent source / drain ion implantation process to form a flash memory device in the cell region and a transistor in the peripheral region.

2 is a cross-sectional photograph of a state in which an interlayer insulating film such as a PSG film or a BPSG film, which is a subsequent process, is formed after the conventional flash memory device is formed.

As described above, the height of the step difference between the conventional cell region and the peripheral region is about 1000 to 1500 차이, and the β of FIG. 2 shows the degree of planarization as the spacer, PSG, BPSG film, etc. of the subsequent process are deposited. The value is about 70 °, and the d value in the picture in FIG. 2 showing the final step between the cell area and the peripheral area is about 4000 mW. As such, the step difference between the cell region and the peripheral region may cause an unstable process during subsequent metal contact masks and etching processes, and bridges and shorts between patterns may occur, causing a device to fail.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of performing a stable subsequent process by minimizing a step between a cell region and a peripheral region in a flash memory device manufacturing process.

According to an aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method including: sequentially forming a cell region and a peripheral region on a semiconductor substrate, and sequentially forming a buffer oxide film and a gate mask on the semiconductor substrate; Forming a trench to expose a semiconductor substrate in the cell region and the peripheral region by an etching process using a gate mask; Sequentially depositing a gate oxide film, a first polysilicon film, and an ONO film on the entire upper surface; Forming an etch mask to open only a peripheral area, and then removing the ONO film in the peripheral area and removing the etch mask; Forming a gate electrode in the trench by depositing a second polysilicon layer on the entire upper surface and performing a front side etching process to expose the buffer oxide layer; And forming a source / drain junction.

1A to 1C are cross-sectional views of a device for explaining a method of manufacturing a conventional flash memory device.

Figure 2 is a cross-sectional photograph of a state following a subsequent process after forming a conventional flash memory device.

3A to 3F are schematic views of a device for explaining a method of manufacturing a flash memory device according to the present invention.

<Description of Signs of Major Parts of Drawings>

10 and 30: semiconductor substrate 11 and 34: gate oxide film

12 and 35: first polysilicon film 13 and 36: ONO film

14 and 37: second polysilicon films 16 and 32: gate mask

17 and 38: gate electrode 31: buffer oxide film

37: anti-etch mask

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3A to 3F are cross-sectional views of devices for describing a method of manufacturing a flash memory device according to the present invention.

Referring to FIG. 3A, after the cell region and the peripheral region are defined in the semiconductor substrate 30, the buffer oxide film 31 is formed on the semiconductor substrate 30, and the gate mask 32 is formed on the upper surface of the buffer oxide film 31. Form.

In the above, the buffer oxide film 31 is formed of a PSG film or a BPSG film to a thickness of 3000 to 5000 Å.

Referring to FIG. 3B, a trench 33 is formed to expose the semiconductor substrate 30 in the cell region and the peripheral region by an etching process using the gate mask 32.

Referring to FIG. 3C, the gate oxide film 34, the first polysilicon film 35, and the ONO film 36 are sequentially stacked on the entire upper surface.

Referring to FIG. 3D, after forming the etch stop mask 37 to open only the peripheral region, the ONO layer 36 of the peripheral region is removed.

Referring to FIG. 3E, the second polysilicon layer 37 is deposited on the entire upper surface after removing the etch stop mask 37.

Referring to FIG. 3F, the gate electrode 38 is formed in the trench 33 in the cell region and the peripheral region by performing an entire surface etching process to expose the buffer oxide film 31.

In the above, in the gate electrode 38 of the cell region, the first polysilicon film 35 becomes a floating gate of the flash memory device, and the second polysilicon film 37 becomes a control gate of the flash memory device. In addition, the first polysilicon film 35 serving as the floating gate may have a structure surrounding the second polysilicon film 37 serving as the control gate, thereby increasing the ONO coupling ratio.

After that, a junction portion is formed by a source / drain ion implantation process to form a flash memory device.

As described above, the present invention eliminates the step difference caused by the different structure of the cell region and the peripheral region to planarize, thereby improving the problem of bridges and shorts between patterns in subsequent processes, thereby reducing the device failure. In addition, since the floating gate surrounds the control gate, the ONO coupling ratio is increased, which is advantageous for low voltage driving devices. Since the buffer oxide film surrounds the gate electrode, the substrate and the gate oxide film are formed by a self-aligned etching process to define the gate electrode. By preventing the damage of the gate oxide to prevent the charge loss of the gate oxide film has the effect of improving the reliability of the device.

Claims (3)

Defining a cell region and a peripheral region in the semiconductor substrate and sequentially forming a buffer oxide film and a gate mask on the semiconductor substrate; Forming a trench to expose a semiconductor substrate in the cell region and the peripheral region by an etching process using a gate mask; Sequentially depositing a gate oxide film, a first polysilicon film, and an ONO film on the entire upper surface; Forming an etch mask to open only a peripheral area, and then removing the ONO film in the peripheral area and removing the etch mask; Forming a gate electrode in the trench by depositing a second polysilicon layer on the entire upper surface and performing a front side etching process to expose the buffer oxide layer; And A method of manufacturing a flash memory device comprising the step of forming a source / drain junction. The method of claim 1, The buffer oxide film is a PSG film or a BPSG film manufacturing method of a flash memory device, characterized in that formed to a thickness of 3000 to 5000Å. The method of claim 1, Wherein the first polysilicon film of the cell region is a floating gate, and the second polysilicon film is a control gate, and the first polysilicon film, which is a floating gate, is formed to surround the second polysilicon film, which is a control gate. A method of manufacturing a flash memory device.