KR20010064542A - Method for forming contact of semiconductor device - Google Patents
Method for forming contact of semiconductor device Download PDFInfo
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- KR20010064542A KR20010064542A KR1019990064757A KR19990064757A KR20010064542A KR 20010064542 A KR20010064542 A KR 20010064542A KR 1019990064757 A KR1019990064757 A KR 1019990064757A KR 19990064757 A KR19990064757 A KR 19990064757A KR 20010064542 A KR20010064542 A KR 20010064542A
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- 238000000034 method Methods 0.000 title claims abstract description 20
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 239000010410 layer Substances 0.000 claims abstract description 31
- 150000004767 nitrides Chemical class 0.000 claims abstract description 31
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 25
- 229920005591 polysilicon Polymers 0.000 claims abstract description 25
- 239000011229 interlayer Substances 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 11
- 239000003990 capacitor Substances 0.000 claims abstract description 8
- 238000000206 photolithography Methods 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000007740 vapor deposition Methods 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 2
- 238000000151 deposition Methods 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 238000009413 insulation Methods 0.000 abstract 6
- 230000008021 deposition Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Plasma & Fusion (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체소자의 콘택 형성방법에 관한 것으로, 특히 디자인 룰(design rule) 0.18㎛ 미만의 고집적 반도체소자에서 간단한 공정을 통해 바닥의 임계치수(critical demension : CD)가 0.10∼0.12㎛ 정도로 형성할 수 있도록 한 반도체소자의 콘택 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact of a semiconductor device. In particular, in a highly integrated semiconductor device having a design rule of less than 0.18 μm, a critical dimension (CD) of the bottom may be formed in a range of about 0.10 to 0.12 μm through a simple process. A contact forming method of a semiconductor device is made.
일반적으로, 디자인 룰 0.18㎛ 미만의 고집적 반도체소자를 구현하기 위해서 사용되는 DUV 노광원을 이용한 패터닝방법은 균일한 임계치수를 갖는 0.20㎛ 이하의 미세 패턴을 구현하는데 어려움이 있으며, 이를 보완하기 위하여 폴리실리콘을 DUV 노광원을 이용하여 사진식각한 다음 다시 폴리실리콘 측벽을 형성하여 개구부 크기를 최소화하고 있다. 이와같은 종래 반도체소자의 콘택 형성방법을 첨부한 도1a 내지 도1f의 수순단면도를 참조하여 상세히 설명하면 다음과 같다.In general, the patterning method using a DUV exposure source used to implement a highly integrated semiconductor device of less than 0.18㎛ design rule has a difficulty in implementing a fine pattern of 0.20㎛ or less with a uniform critical dimension, to compensate for this Silicon is photo-etched using a DUV exposure source and then polysilicon sidewalls are formed to minimize opening size. This will be described in detail below with reference to the procedure cross-sectional view of FIGS.
먼저, 도1a에 도시한 바와같이 절연막(2)을 통해 엔모스 트랜지스터와 같은 소자가 형성된 하부의 반도체기판(미도시)과 선택적으로 접속되는 플러그(1)를 형성한 다음 상부전면에 층간절연막(3)을 형성하여 평탄화하고, 층간절연막(3) 상부에 도전물질을 증착 및 패터닝하여 비트라인(4)을 형성한 다음 상부전면에 순차적으로 질화막(5)과 산화막(6)을 형성한다.First, as shown in FIG. 1A, a plug 1 that is selectively connected to a lower semiconductor substrate (not shown) on which an element such as an NMOS transistor is formed is formed through the insulating film 2, and then an interlayer insulating film ( 3) is formed and planarized, a conductive material is deposited and patterned on the interlayer insulating film 3 to form a bit line 4, and then the nitride film 5 and the oxide film 6 are sequentially formed on the upper surface.
그리고, 도1b에 도시한 바와같이 상기 산화막(6) 상부에 폴리실리콘(7)을 증착하고, 사진식각을 통해 상기 플러그(1) 상의 산화막(6)이 노출되도록 식각한 다음 다시 폴리실리콘을 증착하고, 전면식각하여 폴리실리콘(7)의 식각된 측면에 측벽(8)을 형성한다. 이때, 폴리실리콘(7)의 식각된 측면에 측벽(8)을 형성하는 이유는 반도체소자가 고집적화됨에 따라 노광장비의 한계 해상력보다도 작은 공정마진을 확보함과 아울러 하부 플러그(1)와의 중첩마진을 확보하기 위한 것으로, 이를 적용하면 콘택홀 바닥의 임계치수를 0.10∼0.12㎛ 까지 확보할 수 있게 된다.1B, polysilicon 7 is deposited on the oxide film 6, and the photoresist is etched to expose the oxide film 6 on the plug 1, followed by deposition of polysilicon. And etched to form sidewalls 8 on the etched side of the polysilicon 7. In this case, the reason for forming the sidewall 8 on the etched side of the polysilicon 7 is to secure a process margin smaller than the limit resolution of the exposure equipment as the semiconductor device is highly integrated and to overlap the bottom plug 1 with the margin. If this is applied, it is possible to secure the critical dimension of the contact hole bottom to 0.10 ~ 0.12㎛.
그리고, 도1c에 도시한 바와같이 상기 폴리실리콘(7) 및 측벽(8)을 하드마스크(hard mask)로 적용하여 산화막(6), 질화막(5) 및 층간절연막(3)을 순차적으로 식각함으로써, 상기 플러그(1)가 노출되는 콘택홀(9)을 형성한다.As shown in FIG. 1C, the polysilicon 7 and the sidewall 8 are applied as a hard mask to sequentially etch the oxide film 6, the nitride film 5, and the interlayer insulating film 3. A contact hole 9 is formed through which the plug 1 is exposed.
그리고, 도1d에 도시한 바와같이 상기 콘택홀(9)이 형성된 결과물의 상부전면에 폴리실리콘(10)을 증착하고, 상기 산화막(6)이 노출될때까지 전면 식각하여 콘택홀(9)을 채우는 폴리실리콘(10) 플러그를 형성한다.As shown in FIG. 1D, the polysilicon 10 is deposited on the upper surface of the resultant in which the contact hole 9 is formed, and the entire surface is etched until the oxide layer 6 is exposed to fill the contact hole 9. The polysilicon 10 plug is formed.
그리고, 도1e에 도시한 바와같이 상기 폴리실리콘(10) 플러그가 형성된 결과물의 상부전면에 순차적으로 질화막(11)과 산화막(12)을 형성한다.As shown in FIG. 1E, the nitride film 11 and the oxide film 12 are sequentially formed on the upper front surface of the resultant product in which the polysilicon 10 plug is formed.
그리고, 도1f에 도시한 바와같이 상기 산화막(12)이 형성된 결과물 상에 커패시터의 하부전극 형성을 위한 사진식각을 통해 산화막(12), 질화막(11) 및 산화막(6)을 식각하여 상기 폴리실리콘(10) 플러그를 노출시킨다.As illustrated in FIG. 1F, the oxide film 12, the nitride film 11, and the oxide film 6 are etched through the photolithography for forming the lower electrode of the capacitor on the resultant product on which the oxide film 12 is formed. (10) Expose the plug.
그러나, 상기한 바와같은 종래 반도체소자의 콘택 형성방법은 폴리실리콘의 2회 증착에 따른 제품의 제조시간(turn around time : TAT) 및 제조단가에 있어서 불리한 문제점이 있고, 또한 폴리실리콘의 2회 식각에 따른 파티클(particle) 증가로 인해 수율이 나빠지며, 커패시터의 하부전극 형성을 위한 산화막의 식각시에 하부의 질화막도 완전히 제거해야 하는 공정상의 난점이 있고, 이는 질화막의 식각시 감광막의 선택비 저하로 인해 산화막 표면에 손상을 입히게 되어 후속 반구체 그레인(hemi sphere grain : HSG) 공정에서 단락이 발생하는 문제점이 있었다.However, the contact formation method of the conventional semiconductor device as described above has disadvantages in the turn around time (TAT) and the manufacturing cost of the product due to the double deposition of polysilicon, and also the two times etching of polysilicon. Yields are poor due to the increase of particles, and there is a process difficulty in that the lower nitride film must be completely removed during the etching of the oxide film for forming the lower electrode of the capacitor, which lowers the selectivity of the photoresist film during etching of the nitride film. Due to the damage to the surface of the oxide film there was a problem that a short circuit occurs in the subsequent hemi sphere grain (HSG) process.
본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 디자인 룰 0.18㎛ 미만의 고집적 반도체소자에서 간단한 공정을 통해 바닥의 임계치수가 0.10∼0.12㎛ 정도로 형성할 수 있는 반도체소자의 콘택 형성방법을 제공하는데 있다.The present invention was devised to solve the above-mentioned problems, and an object of the present invention is to form a critical dimension of about 0.10 to 0.12 μm through a simple process in a highly integrated semiconductor device having a design rule of less than 0.18 μm. A method of forming a contact for a semiconductor device is provided.
도1a 내지 도1f는 종래 반도체소자의 콘택 형성방법을 보인 수순단면도.1A to 1F are cross-sectional views showing a conventional method for forming a contact of a semiconductor device.
도2a 내지 도2d는 본 발명의 일 실시예를 보인 수순단면도.2A to 2D are cross-sectional views showing an embodiment of the present invention.
***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
21:플러그 22,28:절연막21: plug 22, 28: insulating film
23:층간절연막 24:비트라인23: interlayer insulating film 24: bit line
25,27:질화막 26,31:산화막25, 27: nitride film 26, 31: oxide film
29:콘택홀 30:폴리실리콘29: contact hole 30: polysilicon
상기한 바와같은 본 발명의 목적을 달성하기 위한 반도체소자의 콘택 형성방법은 반도체기판의 소자들과 제1절연막을 통해 선택적으로 접속되는 플러그를 형성한 다음 상부전면에 층간절연막을 형성하여 평탄화하고, 층간절연막 상부에 비트라인을 패터닝하는 공정과; 상기 결과물의 상부전면에 제1질화막과 제2절연막을 순차적으로 형성하여 평탄화한 다음 제2절연막 상부에 제2질화막과 제3절연막을 형성하는 공정과; 상기 제3절연막, 제2질화막, 제2절연막 및 제1질화막의 일부를 사진식각을 통해 건식 식각장비에서 순차적으로 식각하여 상기 플러그가 노출되도록 콘택홀을 형성한 다음 상부전면에 폴리실리콘을 형성하고, 전면식각하여 상기 콘택홀을 채우는 폴리실리콘 플러그를 형성하는 공정과; 상기 제3절연막을 습식식각으로 제거한 다음 상부전면에 폴리실리콘 플러그와 커패시터 하부전극을 선택적으로 접속시키기 위한 산화막을 형성하는 공정을 구비하여 이루어지는 것을 특징으로 한다.In order to achieve the object of the present invention as described above, the method for forming a contact of a semiconductor device may be planarized by forming a plug that is selectively connected with the devices of the semiconductor substrate through the first insulating film, and then forming an interlayer insulating film on the upper surface thereof. Patterning a bit line on the interlayer insulating film; Forming a first nitride film and a second insulating film sequentially on the upper surface of the resultant to planarize them, and then forming a second nitride film and a third insulating film on the second insulating film; A portion of the third insulating film, the second nitride film, the second insulating film, and the first nitride film are sequentially etched by dry etching equipment through photolithography to form contact holes to expose the plug, and then form polysilicon on the upper surface thereof. Forming a polysilicon plug to etch the entire surface by etching the entire surface; And removing the third insulating film by wet etching, and then forming an oxide film on the upper front surface to selectively connect the polysilicon plug and the lower electrode of the capacitor.
상기한 바와같은 본 발명에 의한 반도체소자의 콘택 형성방법을 첨부한 도2a 내지 도2d의 수순단면도를 일 실시예로 하여 상세히 설명하면 다음과 같다.Referring to the cross-sectional view of Figure 2a to 2d attached to the method for forming a contact of a semiconductor device according to the present invention as described above in detail as follows.
먼저, 도2a에 도시한 바와같이 절연막(22)을 통해 엔모스 트랜지스터와 같은 소자가 형성된 하부의 반도체기판(미도시)과 선택적으로 접속되는 플러그(21)를 형성한 다음 상부전면에 층간절연막(23)을 형성하여 평탄화하고, 층간절연막(23) 상부에 도전물질을 증착 및 패터닝하여 비트라인(24)을 형성한 다음 상부전면에 순차적으로 질화막(25)과 산화막(26)을 형성한다.First, as shown in FIG. 2A, a plug 21 that is selectively connected to a lower semiconductor substrate (not shown) on which an element such as an NMOS transistor is formed is formed through the insulating film 22. Then, an interlayer insulating film ( 23 is formed and planarized, and a bit line 24 is formed by depositing and patterning a conductive material on the interlayer insulating layer 23, and then the nitride layer 25 and the oxide layer 26 are sequentially formed on the upper surface.
그리고, 도2b에 도시한 바와같이 상기 산화막(26)의 상부에 후속 습식식각 차단을 위한 질화막(27)과 콘택홀 하드마스크로 적용하기 위한 절연막(28)을 형성한 다음 사진식각을 통해 건식식각 장비에서 절연막(28), 질화막(27), 산화막(26), 질화막(25) 및 층간절연막(23)을 순차적으로 식각하여 상기 플러그(21)가 노출되도록 콘택홀(29)을 형성한다. 이때, 질화막(27)은 플라즈마 기상증착 또는 저압 기상증착을 통해 50∼2000Å 정도의 두께로 형성하며, 절연막(28)은 PSG, BPSG, USG, HLD 또는 TEOS 중에 선택된 하나의 산화막을 플라즈마 기상증착 또는 저압 기상증착을 통해 50∼3000Å 정도의 두께로 형성하는 것이 바람직하다.As shown in FIG. 2B, an nitride film 27 for subsequent wet etching blocking and an insulating film 28 for applying as a contact hole hard mask are formed on the oxide layer 26, and then dry etching through photolithography. In the device, the insulating layer 28, the nitride layer 27, the oxide layer 26, the nitride layer 25, and the interlayer insulating layer 23 are sequentially etched to form a contact hole 29 to expose the plug 21. At this time, the nitride film 27 is formed to a thickness of about 50 ~ 2000Å by plasma vapor deposition or low pressure vapor deposition, the insulating film 28 is formed by plasma vapor deposition or one oxide film selected from PSG, BPSG, USG, HLD or TEOS It is preferable to form a thickness of about 50 to 3000 kPa through low pressure vapor deposition.
그리고, 도2c에 도시한 바와같이 상기 콘택홀(29)이 형성된 결과물의 상부전면에 폴리실리콘(30)을 증착하고, 상기 절연막(28)이 노출될때까지 전면 식각하여 콘택홀(29)을 채우는 폴리실리콘(30) 플러그를 형성한 다음 노출된 절연막(28)을 습식식각을 통해 제거한다. 이때, 절연막(28) 하부의 질화막(27)은 하부 구조물이 습식식각되지 않도록 차단한다.As shown in FIG. 2C, the polysilicon 30 is deposited on the upper surface of the resultant in which the contact hole 29 is formed, and the entire surface is etched until the insulating layer 28 is exposed to fill the contact hole 29. After forming the polysilicon 30 plug, the exposed insulating layer 28 is removed by wet etching. In this case, the nitride layer 27 below the insulating layer 28 blocks the lower structure from being wet etched.
그리고, 도2d에 도시한 바와같이 상기 질화막(27) 상부에 산화막(31)을 형성한 다음 커패시터의 하부전극 형성을 위한 사진식각을 통해 산화막(31)을 식각하여 상기 폴리실리콘(30) 플러그를 노출시킨다.As shown in FIG. 2D, the oxide film 31 is formed on the nitride film 27, and then the oxide film 31 is etched through the photolithography for forming the lower electrode of the capacitor to remove the plug of the polysilicon 30. Expose
상기한 바와같은 본 발명에 의한 반도체소자의 콘택 형성방법은 하드마스크로 적용하기 위하여 2회의 폴리실리콘 증착 및 식각을 생략하여 제품의 제조시간 및 제조단가에 있어서 유리하고, 파티클 발생을 억제할 수 있게 되어 수율을 향상시킴과 아울러 커패시터의 하부전극 형성을 위한 산화막의 식각시에 하부의 질화막 식각이 생략되어 감광막의 선택비 저하로 인한 산화막 표면 손상을 방지하고, 과도손실에 의한 하부전극의 접촉불량을 개선할 수 있는 효과가 있으며, 종래 기술에서 과도손실이 발생하는 영역에 습식각 방지용 질화막이 형성되어 식각 멈춤(etch-stop)이 발생할 수 있으나, 본원 발병에서는 콘택홀 식각이 이루어짐과 동시에 습식각 방지용 질화막도 식각되어 식각 멈춤 현상을 억제할 수 있는 효과가 있다.The contact forming method of the semiconductor device according to the present invention as described above is advantageous in terms of manufacturing time and manufacturing cost of the product by suppressing two polysilicon deposition and etching in order to apply as a hard mask, it is possible to suppress the generation of particles As a result of improving the yield, the etching of the lower nitride film during the etching of the oxide film to form the lower electrode of the capacitor is omitted, thereby preventing damage to the surface of the oxide film due to the decrease in selectivity of the photosensitive film, and preventing contact failure of the lower electrode due to excessive loss. In the prior art, an etching stop may occur because a wet etching prevention nitride film is formed in a region where excessive loss occurs, but in the present invention, a contact hole etching is performed and at the same time, a wet etching prevention is performed. The nitride film is also etched to have an effect of suppressing the etch stop phenomenon.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100780244B1 (en) * | 2006-08-24 | 2007-11-27 | 동부일렉트로닉스 주식회사 | Cmos image sensor and a method of fabricating the same |
| KR100816720B1 (en) * | 2002-06-07 | 2008-03-27 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
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1999
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100816720B1 (en) * | 2002-06-07 | 2008-03-27 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
| KR100780244B1 (en) * | 2006-08-24 | 2007-11-27 | 동부일렉트로닉스 주식회사 | Cmos image sensor and a method of fabricating the same |
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