TWI785992B - Semiconductor structure and manufacturing method of the same - Google Patents

Abstract

A manufacturing method of the semiconductor structure is provided. First active areas, a second active area, and a third active area are formed. A first dielectric layer is formed on the first active areas, the second active area, and the third active area. A patterning region is formed in the first dielectric layer, wherein the patterning region includes a cavity region and a dielectric region surrounding the cavity region, and the dielectric region corresponds to the second active area. A filling layer is formed in the cavity region. A cap layer is formed on the first dielectric layer. A second dielectric layer is formed on the cap layer. Multiple first contact holes and at least one second contact hole that penetrate the second dielectric layer, the cap layer, and the first dielectric layer are formed. Each first contact hole exposes a portion of the corresponding first active area, and the second contact hole replaces the dielectric region and exposes a portion of the second active area. Metal layers are filled in the first contact hole and the second contact hole.

Description

Semiconductor structure and manufacturing method thereof

The present disclosure relates to a semiconductor structure and a manufacturing method thereof, in particular to a manufacturing method capable of reducing contact hole manufacturing steps and the formed semiconductor structure.

In the process of manufacturing a semiconductor structure, multiple processes are often required to complete the connection of the through hole, which is not only time-consuming but also requires high alignment accuracy. In order to avoid short circuits caused by misalignment, the widths of some contact holes and the metal connection lines filled therein are limited (eg, cannot be reduced). As semiconductor structures become increasingly complex (for example, volumes become smaller and device densities increase), manufacturing methods of semiconductor structures face more challenges.

The disclosed embodiment proposes a method for manufacturing a semiconductor structure, which can effectively reduce the number of processes for forming contact holes, thereby shortening the overall process time and cost. In addition, the manufacturing method of the semiconductor structure according to the disclosed embodiments can provide higher alignment tolerance, thereby effectively shortening the width of the contact hole and the connection line filled therein, so as to reduce the volume of the semiconductor structure and increase the density of the device.

Some embodiments of the present disclosure include a method of manufacturing a semiconductor structure, and the method of manufacturing the semiconductor structure includes the following steps. A plurality of first active areas, at least one second active area and at least one third active area are formed, wherein the first active area defines the unit area, and the second active area and the third active area define the peripheral area. A first dielectric layer is formed on the first active area, the second active area and the third active area. A patterned area is formed in the first dielectric layer, wherein the patterned area includes a cavity area and a dielectric area, the cavity area surrounds the dielectric area, and the dielectric area corresponds to the second active area. A filling layer is formed in the cavity region. A capping layer is formed over the first dielectric layer. A second dielectric layer is formed over the capping layer. forming a plurality of first contact holes and at least one second contact hole, wherein the first contact hole and the second contact hole penetrate through the second dielectric layer, the cover layer and the first dielectric layer, and each first contact hole exposes a corresponding part of the first active region, and the second contact hole further replaces the dielectric region and exposes a part of the second active region. Multiple metal layers are filled in the first contact hole and the second contact hole.

Some embodiments of the present disclosure include a semiconductor structure. The semiconductor structure includes a first active area, at least one second active area and at least one third active area, the first active area defines a unit area, and the second active area and the third active area define a peripheral area. The semiconductor structure also includes a first dielectric layer and a capping layer. The first dielectric layer is disposed on the first active region, the second active region, and the third active region and includes a patterned region, and the patterned region corresponds to the second active region. region, and the capping layer is disposed on the first dielectric layer. The semiconductor structure further includes a second dielectric layer disposed on the capping layer. In addition, the semiconductor structure includes a plurality of first metal layers and at least one second metal layer, the first metal layer penetrates through the second dielectric layer, the cover layer and the first dielectric layer and is electrically connected with the first active region, and the second The metal layer penetrates through the second dielectric layer, the cover layer and the first dielectric layer and is electrically connected with the second active region.

For simplicity, some components of the semiconductor structure 100 have been omitted from FIGS. 1A to 8 .

Referring to FIG. 1A, a plurality of first active area (active area) A1, second active area A2 and third active area A3 are formed. The first active region A1 defines a cell region C of the semiconductor structure 100 , and the second active region A2 and the third active region A3 define a peripheral region P of the semiconductor structure 100 .

The first active region A1 , the second active region A2 and the third active region A3 may include conductive materials such as metals, metal silicides, semiconductor materials, similar materials or combinations thereof, but the disclosure is not limited thereto.

The first active region A1 , the second active region A2 and the third active region A3 may include various p-type doped regions and/or n-type doped regions formed by ion implantation and/or diffusion processes. The first active region A1, the second active region A2, and the third active region A3 can be deposited through physical vapor deposition (physical vapor deposition, PVD), chemical vapor deposition (chemical vapor deposition, CVD), atomic layer deposition (atomic layer deposition) , ALD), evaporation (evaporation), sputtering (sputtering), similar processes or a combination thereof, but the present disclosure is not limited thereto.

In addition, the first active region A1 , the second active region A2 and the third active region A3 may be separated by various isolation components TI. For example, the isolation component TI may include shallow trench isolation (STI), but the disclosure is not limited thereto. The step of forming the isolation feature TI may include etching a trench and filling the trench with an insulating material (eg, silicon oxide, silicon nitride, or silicon oxynitride).

In some embodiments, a gate structure G is formed on the third active region A3. For example, the gate structure G may comprise conductive materials such as metals, metal silicides, similar materials, or combinations thereof. The gate structure G can be formed by, for example, physical vapor deposition, chemical vapor deposition, atomic layer deposition, evaporation, sputtering, similar processes or a combination thereof.

In some embodiments, the first dielectric layer D1 is formed on the first active region A1 , the second active region A2 and the third active region A3 . The first dielectric layer D1 may comprise any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric material, aluminum oxide, aluminum nitride, and the like. Or a combination of the foregoing, but the present disclosure is not limited thereto. In addition, the first dielectric layer D1 can be formed by, for example, a deposition process, such as a chemical vapor deposition process, an atomic layer deposition process, a spin-on coating process, a similar deposition process, or a combination thereof.

Referring to FIG. 1A, a patterned region P1 and a patterned region P2 are formed in the first dielectric layer D1. The patterned area P1 corresponds to the second active area A2, and the patterned area P2 corresponds to the gate structure G (or the third active area A3). Specifically, the first dielectric layer D1 is patterned to form a patterned area P1 and a patterned area P2. Figure 1B may, for example, be a partial top view corresponding to the patterned region P1 in Figure 1A. It should be noted that FIG. 1B may also be, for example, a partial top view corresponding to the patterned region P2 in FIG. 1A . In other words, the patterned region P1 may have the same or similar structure as the patterned region P2.

Referring to FIG. 1A and FIG. 1B , the patterned region P1 includes a cavity region P11 and a dielectric region P13 , the cavity region P11 surrounds the dielectric region P13 , and the dielectric region P13 corresponds to the second active region A2 . In other words, the dielectric region P13 of the patterned region P1 at least partially overlaps with the second active region A2. Similarly, as shown in FIG. 1A, the patterned region P2 includes a cavity region P21 and a dielectric region P23, the cavity region P21 surrounds the dielectric region P23, and the dielectric region P23 corresponds to the gate structure G (or the third Active zone A3). In other words, the dielectric region P23 of the patterned region P2 at least partially overlaps with the third active region A3.

In addition, as shown in FIG. 1A, a patterned region P3 is further formed in the first dielectric layer D1, and the patterned region P3 includes a cavity region P31. Specifically, the first dielectric layer D1 is patterned to form a patterned region P3. For example, the patterned region P1 , the patterned region P2 and the patterned region P3 can be formed simultaneously through the same (patterning) process, but the disclosure is not limited thereto.

In some embodiments, a mask layer (not shown) is disposed on the first dielectric layer D1 through a patterning process, and then an etching process is performed using the aforementioned mask layer as an etching mask to form the patterned region P1. , the patterned region P2 and/or the patterned region P3 (that is, the first dielectric layer D1 is etched into the cavity region P11 , the cavity region P21 and/or the cavity region P31 ). The mask layer may comprise a hard mask, for example comprising silicon oxide (SiO ₂ ), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbide nitride (SiCN), similar materials or the foregoing combination. The mask layer can be a single-layer or multi-layer structure.

The mask layer can be formed, for example, by deposition process, lithography process, other suitable processes or a combination of the foregoing. The example of the deposition process has been described above and will not be repeated here. The lithography process may, for example, include photoresist coating (eg, spin coating), soft baking, mask aligning, exposure, post-exposure baking, PEB), developing, rinsing, drying (such as hard baking), other suitable processes or a combination of the foregoing.

Referring to FIG. 2 , the first barrier layer B1 is formed in the cavity region P11 , the cavity region P21 and the cavity region P31 . Specifically, the first barrier layer B1 can be formed on the sidewall and bottom of the cavity region P11 in the patterned region P1, the sidewall and bottom of the cavity region P21 in the patterned region P2, and the cavity region in the patterned region P3. The side wall and bottom of P31. In this embodiment, the first barrier layer B1 includes titanium (Ti) or titanium nitride (TiN). In addition, the first barrier layer B1 can be formed through a deposition process, but the disclosure is not limited thereto. The example of the deposition process has been described above and will not be repeated here.

Referring to FIG. 2 , FIG. 3A and FIG. 3B , the filling layer M0 is formed in the cavity area P11 , the cavity area P21 and the cavity area P31 . The filling layer M0 is formed on the first barrier layer B1 and fills the cavity region P11 of the patterned region P1 , the cavity region P21 of the patterned region P2 and the cavity region P31 of the patterned region P3 . In this embodiment, the filling layer M0 includes tungsten (W). The filling layer M0 can be formed through a deposition process, but the disclosure is not limited thereto. The example of the deposition process has been described above and will not be repeated here.

After forming the first barrier layer B1 and the filling layer M0, a planarization process may be performed. For example, a chemical mechanical polishing (CMP) process can be performed to make the top surface of the first dielectric layer D1, the top surface of the patterned region P1, the top surface of the patterned region P2 and the patterned region P3 The top surface is coplanar. That is, the topmost surface of the first barrier layer B1 and the topmost surface of the filling layer M0 may be coplanar with the top surface of the first dielectric layer D1 (ie, not exceeding the top surface of the first dielectric layer D1), But this disclosure is not limited thereto.

Referring to FIG. 4, a capping layer CL is formed on the first dielectric layer D1. For example, the cap layer CL can be formed through a deposition process, but the disclosure is not limited thereto. The example of the deposition process has been described above and will not be repeated here. The capping layer CL may comprise any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric material, aluminum oxide, aluminum nitride, similar materials, or the foregoing. combinations, but this disclosure is not limited thereto. It should be noted that the material of the capping layer CL is different from that of the first dielectric layer D1, so that the etching rate of the capping layer CL and the first dielectric layer D1 are different (that is, have etching selectivity) during the subsequent etching process. ).

Referring to FIG. 5, a second dielectric layer D2 is formed on the capping layer CL. The material and manufacturing method of the second dielectric layer D2 may be the same as or similar to those of the first dielectric layer D1 , which will not be repeated here, but the disclosure is not limited thereto.

Referring to FIG. 6, a plurality of first contact holes CH1 and second contact holes CH2 are formed. For example, a patterning process may be performed to form the first contact hole CH1 and the second contact hole CH2, but the disclosure is not limited thereto. An example of the patterning process is described above and will not be repeated here. In some embodiments, both the first contact hole CH1 and the second contact hole CH2 penetrate the second dielectric layer D2, the capping layer CL and the first dielectric layer D1, and each first contact hole CH1 exposes a corresponding first active layer. As part of the region A1, the second contact hole CH2 further replaces the dielectric region P13 of the patterned region P1 and exposes a part of the second active region A2.

Similarly, a third contact hole CH3 and a fourth contact hole CH4 are formed. For example, a patterning process may be performed to simultaneously form the first contact hole CH1 , the second contact hole CH2 , the third contact hole CH3 and the fourth contact hole CH4 , but the present disclosure is not limited thereto. The third contact hole CH3 penetrates through the second dielectric layer D2 , the capping layer CL and a part of the first dielectric layer D1 , replaces the dielectric region P23 of the patterned region P2 and exposes a part of the gate structure G. The fourth contact hole CH4 penetrates through the second dielectric layer D2 and the capping layer CL, and exposes a portion of the filling layer M0 filled in the cavity region P31 of the patterned region P3.

Referring to FIG. 7, a second barrier layer B2 is formed in the first contact hole CH1, the second contact hole CH2, the third contact hole CH3, and the fourth contact hole CH4. Specifically, the second barrier layer B2 may be formed on the sidewalls of the first contact hole CH1 , the second contact hole CH2 , the third contact hole CH3 and the fourth contact hole CH4 . The material and manufacturing method of the second barrier layer B2 may be the same as or similar to those of the first barrier layer B1 and will not be repeated here, but the disclosure is not limited thereto.

Referring to FIG. 8 , a metal layer is filled in the first contact hole CH1 , the second contact hole CH2 , the third contact hole CH3 and the fourth contact hole CH4 to form a semiconductor structure 100 . Specifically, the metal layer includes a first metal layer M1, a second metal layer M2, a third metal layer M3, and a fourth metal layer M4, and are respectively formed in the first contact hole CH1, the second contact hole CH2, the third contact hole CH3 and the fourth contact hole CH4. In other words, the first metal layer M1 is formed on the second barrier layer B2 and fills the first contact hole CH1; the second metal layer M2 is formed on the second barrier layer B2 and fills the second contact hole. CH2; the third metal layer M3 is formed on the second barrier layer B2 and fills the third contact hole CH3; the fourth metal layer M4 is formed on the second barrier layer B2 and fills the fourth contact hole CH4.

As shown in FIG. 8 , a part of the second barrier layer B2 is located between the second metal layer M2 and the filling layer M0 . Alternatively, a part of the second barrier layer B2 is located between the third metal layer M3 and the filling layer M0. In other words, the filling layer M0 is located between the first barrier layer B1 and the second barrier layer B2. In more detail, the first barrier layer B1 and the second barrier layer B2 cover the sidewall and bottom of the filling layer M0, but the disclosure is not limited thereto.

In this embodiment, the first metal layer M1 , the second metal layer M2 , the third metal layer M3 and the fourth metal layer M4 include tungsten (W). In addition, the first metal layer M1 , the second metal layer M2 , the third metal layer M3 and the fourth metal layer M4 can be formed through a deposition process, but the present disclosure is not limited thereto. The example of the deposition process has been described above and will not be repeated here.

As shown in FIG. 8, the first metal layer M1 penetrates the second dielectric layer D2, the capping layer CL and the first dielectric layer D1, and is electrically connected to the first active region A1; the second metal layer M2 penetrates the second The dielectric layer D2, the capping layer CL and the first dielectric layer D1 are electrically connected to the second active region A2; the third metal layer M3 penetrates the second dielectric layer D2, the capping layer CL and part of the first dielectric layer D1 is also connected (electrically) to the gate structure G.

The first barrier layer B1 is disposed on at least a portion of the sidewall and bottom of the patterned region P1 , at least a portion of the sidewall and bottom of the patterned region P2 , and/or the sidewall and bottom of the patterned region P3 . The second barrier layer B2 is disposed on the sidewall of each first metal layer M1 , at least part of the sidewalls of the second metal layer M2 and the third metal layer M3 and/or the sidewall of the fourth metal layer M4 . In other words, in the patterned region P1, the filling layer M0 is disposed between the second metal layer M2 and the first barrier layer B1; in the patterned region P2, the filling layer M0 is disposed between the third metal layer M3 and the first barrier layer B1. Between the barrier layers B1 ; in the patterned region P3 , the first barrier layer B1 covers the sidewall and the bottom of the filling layer M0 , but the disclosure is not limited thereto.

As shown in FIG. 8, each first metal layer M1 has a substantially constant width. It should be noted that the bottom of the first metal layer M1 may be gradually narrowed due to process factors (convergence of the bottom of the first contact hole CH1), but other parts of the first metal layer M1 remain Virtually constant width.

The second metal layer M2 includes a first connection portion M21, a filling portion M23 and a second connection portion M25, the first connection portion M21 is connected to the second active area A2, the filling portion M23 fills the patterned area P1 and is connected to the first connection portion M21 is connected, and the second connection part M25 is disposed on the filling part M23 and connected with the filling part M23. In other words, the second connection portion M25 of the second metal layer M2 can be electrically connected to the first connection portion M21 through the filling portion M23. In some embodiments, the width WM25 of the second connection portion M25 is greater than the width WM21 of the first connection portion M21. As shown in FIG. 8, the second barrier layer B2 is disposed on the sidewalls of the first connecting portion M21 and the second connecting portion M25. In this embodiment, the second barrier layer B2 is further disposed on the sidewall of the filling portion M23, but the disclosure is not limited thereto.

Similarly, in some embodiments, the third metal layer M3 includes a first connection portion M31, a filling portion M33, and a second connection portion M35, the first connection portion M31 is connected to the gate structure G, and the filling portion M33 fills the patterned The region P2 is also connected to the first connection portion M31, and the second connection portion M35 is disposed on the filling portion M33 and connected to the filling portion M33. In other words, the second connection portion M35 of the third metal layer M3 can be electrically connected to the first connection portion M31 through the filling portion M33 . In some embodiments, the width WM35 of the second connection portion M35 is greater than the width WM31 of the first connection portion M31. As shown in FIG. 8, the second barrier layer B2 is disposed on the sidewalls of the first connecting portion M31 and the second connecting portion M35. In this embodiment, the second barrier layer B2 is further disposed on the sidewall of the filling portion M33, but the disclosure is not limited thereto.

Compared with the conventional manufacturing method of semiconductor structure, in the manufacturing method of the semiconductor structure 100 of the disclosed embodiment, the contact holes can be formed through fewer processes, thereby shortening the overall process time and cost. In addition, since the second metal layer M2 can be electrically connected to the first connecting portion M21 through the filling portion M23 , higher alignment tolerance can be provided and the possibility of open circuit (open) can be effectively reduced.

FIG. 9 is a partial top view of a semiconductor structure 100 according to some embodiments of the present disclosure. Traditionally, in the process of manufacturing a semiconductor structure, multiple processes are required to complete the connection of the contact holes. Therefore, generally, the first metal layer M1 of the semiconductor structure is formed in segments and has different widths. In contrast, as shown in FIG. 8 and FIG. 9, in some embodiments of the present disclosure, the first contact hole CH1 located in the cell region C directly penetrates through the second dielectric layer D2 and the capping layer through a patterning process. CL and the first dielectric layer D1, so that each first metal layer M1 has a substantially constant width. Therefore, the width of the first contact hole CH1 and the connection line filled therein (ie, the first metal layer M1 ) can be effectively shortened.

In addition, since the contact holes can be formed at one time, alignment marks added for alignment can be reduced. Furthermore, compared with the conventional technique of forming contact holes and metal layers through at least two patterning processes and filling (eg, deposition) processes, the overall width (eg, top width) of the formed metal layer is larger, as shown in No. As shown in Figure 9, through the method of the disclosed embodiment, the overall width of the first metal layer M1 can be further reduced, thereby shortening the distances S1 and S3 between the first metal layer M1 and the peripheral region P and the distances S1 and S3 between the two adjacent first metal layers. The distance S2 of the layer M1 in the X direction reduces the volume of the semiconductor structure 100 and increases the device density.

10 to 17 are partial cross-sectional views illustrating various stages of the manufacturing method of the semiconductor structure 102 according to other embodiments of the present disclosure. For example, the stage depicted in FIG. 10 may eg follow the stage depicted in FIG. 1A. Similarly, some components of the semiconductor structure 102 have been omitted from FIGS. 10-17 for simplicity.

Referring to FIG. 10, the first barrier layer B1' is formed in the cavity region P11 of the patterned region P1, the cavity region P21 of the patterned region P2, and the cavity region P31 of the patterned region P3. The position and method of forming the first barrier layer B1' are similar to those of the aforementioned first barrier layer B1, so the description will not be repeated. In this embodiment, the first barrier layer B1' includes tantalum (Ta).

Referring to FIG. 10 and FIG. 11, a filling layer M0' is formed on the first barrier layer B1', and the filling layer M0' fills the cavity region P11, the cavity region P21 and the cavity region P31. In this embodiment, the filling layer M0' includes spin-on carbon (SOC) material. Similarly, in some embodiments, after forming the first barrier layer B1' and the filling layer M0', a planarization process may be performed.

Referring to FIGS. 12 to 14, a capping layer CL is formed on the first dielectric layer D1. For example, the cap layer CL can be formed under the condition lower than the glass transition temperature (for example, 300 degrees Celsius) of the filling layer M0', but the disclosure is not limited thereto. Next, a second dielectric layer D2 is formed on the capping layer CL. Next, a plurality of first contact holes CH1 and second contact holes CH2 are formed. As shown in FIG. 14, the first contact hole CH1 and the second contact hole CH2 both penetrate the second dielectric layer D2, the cap layer CL and the first dielectric layer D1, and each first contact hole CH1 exposes a corresponding first contact hole CH1. A part of the active region A1, the second contact hole CH2 further replaces the dielectric region P13 of the patterned region P1 and exposes a part of the second active region A2.

Similarly, a third contact hole CH3 and a fourth contact hole CH4 are formed. For example, a patterning process may be performed to simultaneously form the first contact hole CH1 , the second contact hole CH2 , the third contact hole CH3 and the fourth contact hole CH4 , but the present disclosure is not limited thereto. The third contact hole CH3 penetrates through the second dielectric layer D2 , the cap layer CL and a part of the first dielectric layer D1 , and exposes a part of the gate structure G. The fourth contact hole CH4 penetrates through the second dielectric layer D2 and the capping layer CL, and exposes a portion of the filling layer M0' filled in the cavity region P31 of the patterned region P3.

Referring to FIG. 15, the filling layer M0' is removed. For example, the filling layer M0' can be removed from the cavity region P11 of the patterned region P1, the cavity region P21 of the patterned region P2, and the cavity region P31 of the patterned region P3 through a wet cleaning process. removed, but this disclosure is not limited thereto.

Referring to FIG. 16, a second barrier layer B2' is formed in the first contact hole CH1, the second contact hole CH2, the third contact hole CH3, and the fourth contact hole CH4. Specifically, the second barrier layer B2' may be formed on the sidewalls of the first contact hole CH1, the second contact hole CH2, the third contact hole CH3, and the fourth contact hole CH4. The material of the second barrier layer B2' may be the same as or similar to that of the first barrier layer B1', which will not be repeated here, but the disclosure is not limited thereto.

Referring to FIG. 17 , a metal layer is filled in the first contact hole CH1 , the second contact hole CH2 , the third contact hole CH3 and the fourth contact hole CH4 to form a semiconductor structure 102 . Specifically, as shown in FIG. 17, the metal layer includes a first metal layer M1', a second metal layer M2', a third metal layer M3' and a fourth metal layer M4', the first metal layer M1', the second metal layer The second metal layer M2', the third metal layer M3' and the fourth metal layer M4' are respectively formed in the first contact hole CH1, the second contact hole CH2, the third contact hole CH3 and the fourth contact hole CH4.

In other words, in some embodiments, the first metal layer M1' is formed on the second barrier layer B2' and fills the first contact hole CH1; the second metal layer M2' is formed on the second barrier layer B2' and fill the second contact hole CH2 and the cavity region P11 of the patterned region P1; the third metal layer M3' is formed on the second barrier layer B2' and fill the third contact hole CH3 and the pattern The cavity area P21 of the patterned area P2; the fourth metal layer M4' is formed on the second barrier layer B2', and fills the fourth contact hole CH4 and the cavity area P31 of the patterned area P3.

In this embodiment, the first metal layer M1', the second metal layer M2', the third metal layer M3' and the fourth metal layer M4' include copper (Cu). In addition, the first metal layer M1 ′, the second metal layer M2 ′, the third metal layer M3 ′, and the fourth metal layer M4 ′ can be respectively formed in the first contact hole CH1 and the second contact hole CH2 through an electroplating process. (and the cavity region P11 of the patterned region P1), the third contact hole CH3 (and the cavity region P21 of the patterned region P2) and the fourth contact hole CH4 (and the cavity region P31 of the patterned region P3), But this disclosure is not limited thereto.

Similarly, as shown in FIG. 17, in some embodiments, each first metal layer M1' has a substantially constant width. It should be noted that the bottom of the first metal layer M1' may be gradually narrowed due to process factors (convergence of the bottom of the first contact hole CH1), but other parts of the first metal layer M1' The section still maintains a substantially constant width.

In addition, as shown in FIG. 17, in some embodiments, the second metal layer M2' includes a first connection part M21', a filling part M23' and a second connection part M25', and the first connection part M21' and the second The active area A2 is connected, the filling part M23' is filled in the patterned area P1 and connected to the first connecting part M21, and the second connecting part M25' is disposed on the filling part M23' and connected to the filling part M23'. In other words, the second metal layer M2' can be electrically connected to the first connection part M21' through the filling part M23'.

Moreover, as shown in FIG. 17, in some embodiments, the third metal layer M3' includes a first connection part M31', a filling part M33' and a second connection part M35', and the first connection part M31' is connected to the gate The pole structure G is connected, the filling part M33' is filled in the patterned region P2 and connected to the first connecting part M31', and the second connecting part M35' is disposed on the filling part M33' and connected to the filling part M33'. In other words, the second connection portion M35' of the third metal layer M3' can be electrically connected to the first connection portion M31' through the filling portion M33'.

According to the above description, through the manufacturing method of the semiconductor structure of the disclosed embodiment, the number of processes for forming the contact holes can be effectively reduced, thereby shortening the overall process time and cost. In addition, the manufacturing method of the semiconductor structure according to the disclosed embodiments can provide higher alignment tolerance, thereby effectively shortening the width of the contact hole and the connection line filled therein, so as to reduce the volume of the semiconductor structure and increase the density of the device.

The components of several embodiments are summarized above, so that those skilled in the art of the present disclosure can better understand the viewpoints of the embodiments of the present disclosure. Those with ordinary knowledge in the technical field of the present disclosure should understand that they can design or modify other processes and structures based on the embodiments of the present disclosure to achieve the same purpose and/or advantages as the embodiments described herein. Those with ordinary knowledge in the technical field to which this disclosure belongs should also understand that such equivalent structures do not depart from the spirit and scope of this disclosure, and they can make various changes without departing from the spirit and scope of this disclosure. Various changes, substitutions and substitutions. Therefore, the scope of protection of this disclosure should be defined by the scope of the appended patent application. In addition, although the present disclosure has been disclosed above with several preferred embodiments, it is not intended to limit the present disclosure.

100, 102: Semiconductor Structures A1: The first active area A2: The second active area A3: The third active area B1, B1': the first barrier layer B2, B2': the second barrier layer C: cell area CH1: first contact hole CH2: second contact hole CH3: The third contact hole CH4: fourth contact hole CL: cover layer D1: The first dielectric layer D2: Second dielectric layer G: gate structure M0, M0': filling layer M1, M1': the first metal layer M2, M2': the second metal layer M3, M3': the third metal layer M21, M31, M21’, M31’: the first connecting part M23, M33, M23’, M33’: filling part M25, M35, M25’, M35’: the second connecting part M4, M4': the fourth metal layer P: Surrounding area P1, P2, P3: patterned area P11, P21, P31: cavity area P13, P23: dielectric area TI: Isolation Components WM21, WM25, WM31, WM35: Width X, Y, Z: coordinate axis

FIG. 1A , FIG. 2 , FIG. 3A , and FIG. 4 to FIG. 8 are partial cross-sectional views illustrating various stages of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure. Fig. 1B is a top view corresponding to the partial structure in Fig. 1A. Fig. 3B is a top view corresponding to part of the structure in Fig. 3A. FIG. 9 is a partial top view illustrating a semiconductor structure according to some embodiments of the present disclosure. FIG. 10 to FIG. 17 are partial cross-sectional views illustrating various stages of a manufacturing method of a semiconductor structure according to some other embodiments of the present disclosure.

100: Semiconductor Structures

A1: The first active area

A2: The second active area

A3: The third active area

B1: The first barrier layer

B2: Second barrier layer

C: cell area

CL: cover layer

D1: The first dielectric layer

D2: Second dielectric layer

G: gate structure

M0: filling layer

M1: first metal layer

M2: second metal layer

M3: The third metal layer

M21, M31: the first connecting part

M23, M33: filling part

M25, M35: Second connecting part

M4: fourth metal layer

P: Surrounding area

P1, P2, P3: patterned area

TI: Isolation Components

WM21, WM25, WM31, WM35: Width

X, Z: coordinate axis

Claims (15)

A method for manufacturing a semiconductor structure, comprising: forming a plurality of first active regions, at least one second active region, and at least one third active region, wherein the first active regions define a unit region, and the second active regions and The third active region defines a peripheral area; a first dielectric layer is formed on the first active regions, the second active region and the third active region; a pattern is formed in the first dielectric layer A patterned region, wherein the patterned region includes a cavity region and a dielectric region, the cavity region surrounds the dielectric region, and the dielectric region corresponds to the second active region; a filling layer is formed in the cavity region ; forming a capping layer on the first dielectric layer; forming a second dielectric layer on the capping layer; forming a plurality of first contact holes and at least one second contact hole, wherein the first contacts The hole and the second contact hole penetrate through the second dielectric layer, the capping layer and the first dielectric layer, each of the first contact holes exposes a part of one of the first active regions, and the second contact hole further replacing the dielectric region and exposing a part of the second active region; and filling a plurality of metal layers in the first contact holes and the second contact holes. The method for manufacturing a semiconductor structure according to claim 1, further comprising: forming a gate structure on the third active region; wherein another patterned region is formed in the first dielectric layer, and the another patterned The dielectric region of the region corresponds to the gate structure. The method for manufacturing a semiconductor structure according to claim 1, further comprising: forming a first barrier layer in the cavity region before forming the filling layer in the cavity region. The method for manufacturing a semiconductor structure according to claim 3, wherein before filling the metal layers in the first contact holes and the second contact holes, further comprising: filling the first contact holes and the second contact holes forming a second barrier layer. The method of manufacturing a semiconductor structure according to claim 4, wherein the first barrier layer and the second barrier layer comprise titanium or titanium nitride, and the filling layer and the metal layers comprise tungsten. The method of manufacturing a semiconductor structure as claimed in claim 4, wherein the filling layer comprises a spin-on carbon material. The method for manufacturing a semiconductor structure according to claim 6, further comprising: removing the filling layer after forming the first contact holes and the second contact holes. The method of manufacturing a semiconductor structure according to claim 6, wherein the first barrier layer and the second barrier layer comprise tantalum, and the metal layers comprise copper. A semiconductor structure, comprising: a plurality of first active regions defining a cell region; at least one second active region and at least one third active region defining a peripheral region; a first dielectric layer disposed on the first The active area, the second active area and the third active area include a patterned area corresponding to the first Two active regions; a capping layer disposed on the first dielectric layer; a second dielectric layer disposed on the capping layer; a plurality of first metal layers penetrating through the second dielectric layer, the The capping layer is electrically connected with the first dielectric layer and the first active regions; at least one second metal layer penetrates the second dielectric layer, the capping layer and the first dielectric layer and is connected with the first dielectric layer The two active regions are electrically connected; and at least one third metal layer runs through the second dielectric layer, the cover layer and part of the first dielectric layer and corresponds to the third active region, wherein the at least one third metal layer The bottom of the metal layer is located above the bottom of the at least one second metal layer. The semiconductor structure of claim 9, wherein each of the first metal layers has a constant width. The semiconductor structure according to claim 9, further comprising: a first barrier layer disposed on at least a part of the sidewall and bottom of the patterned region; and a second barrier layer disposed on the sidewall of each of the first metal layers and at least a portion of the sidewall of the second metal layer. The semiconductor structure according to claim 11, wherein the second metal layer includes: a first connection part connected to the second active region; a filling part filled in the patterned region and connected to the first connection part; and a second connecting portion disposed on the filling portion and connected to the filling portion; wherein the second barrier layer is disposed on the sidewalls of the first connecting portion and the second connecting portion. The semiconductor structure according to claim 12, wherein the width of the second connection portion is greater than the width of the first connection portion. The semiconductor structure according to claim 12, wherein the second barrier layer is further disposed on the sidewall of the filling portion. The semiconductor structure of claim 9, wherein the first metal layers and the second metal layers comprise tungsten or copper.

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