KR20010064044A - Method for fabricating a Liquid crystal display - Google Patents

Abstract

PURPOSE: A method for manufacturing a liquid crystal display device is provided to achieve a stable manufacturing process by preventing defects caused by short between a gate wiring and a pixel electrode. CONSTITUTION: The first metal layer is deposited on a substrate. A gate wiring(200) is formed by patterning the first metal layer using the first mask. A gate insulating layer(202), a pure semiconductor layer(204), an impurity semiconductor(206) and the second and third metal layers are sequentially deposited on the entire surface of the substrate. The second and third metal layers are patterned by using the second mask, thereby forming a source and drain electrode, the first and second gate wiring protecting sections(208,210) and a semiconductor channel. A protective layer(212) is deposited on the second and third metal layers. After covering the source and drain electrode and the channel section with the third mask, a part of the drain electrode is exposed. A transparent conductive electrode is deposited on the substrate. Then, a storage capacitor is formed by overlapping the transparent conductive electrode with a part of the gate wiring(200).

Description

Method for fabricating a liquid crystal display

The present invention relates to an image display device, and more particularly, to a manufacturing method of a liquid crystal display (LCD) including a thin film transistor (TFT) and a liquid crystal display device according to the manufacturing method. will be.

In particular, the present invention relates to a method of manufacturing by reducing the number of masks used in manufacturing a liquid crystal display, and a liquid crystal display manufactured by the method.

The driving principle of the liquid crystal display device uses the optical anisotropy and polarization property of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Accordingly, when the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal due to optical anisotropy to express image information.

Currently, the active matrix liquid crystal display (AM-LCD) in which the above-described thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner has attracted the most attention due to its excellent resolution and ability to implement video.

In general, the structure of a liquid crystal panel, which is a basic component of a liquid crystal display, will be described.

1 is a cross-sectional view showing a cross section of a general liquid crystal panel.

In the liquid crystal panel 20, two substrates 2 and 4 having various kinds of elements are formed to correspond to each other, and the liquid crystal layer 10 is interposed between the two substrates 2 and 4. .

The liquid crystal panel 20 includes an upper substrate 4 having a color filter representing a color and a lower substrate 2 having a switching circuit capable of converting a molecular arrangement direction of the liquid crystal layer 10.

The upper substrate 4 includes a color filter layer 8 for implementing color and a common electrode 12 covering the color filter layer 8. The common electrode 12 serves as one electrode for applying a voltage to the liquid crystal 10. The lower substrate 2 has a thin film transistor S serving as a switching function and a pixel electrode 14 serving as an electrode for receiving a signal from the thin film transistor S and applying a voltage to the liquid crystal 10. It is composed of

The portion where the pixel electrode 14 is formed is called the pixel portion P. FIG.

In order to prevent leakage of the liquid crystal 10 injected between the upper substrate 4 and the lower substrate 2, sealants (sealant) is formed at the edges of the upper substrate 4 and the lower substrate 2. It is sealed with).

Referring to the operation and configuration of the lower substrate 2 in Figure 2 showing a plan view of the lower substrate 2 shown in FIG. 1 as follows.

The pixel electrode 14 is formed on the lower substrate 2, and the data line 24 and the gate line 22 are formed in the vertical and horizontal alignment directions of the pixel electrode 14, respectively.

In the active matrix liquid crystal display device, a thin film transistor S, which is a switching element for applying a voltage to the pixel electrode 14, is formed at one portion of the pixel electrode 14. The thin film transistor S includes a gate electrode 26, source and drain electrodes 28 and 30, and a portion of the gate wire 22 defines a portion of the gate electrode 26, and the source electrode 28. ) Is connected to the data line 24.

In addition, data pads 23 and gate pads 21 are formed at one ends of the data line 24 and the gate line 22, respectively, to drive the thin film transistor S and the pixel electrode 14, respectively. It is connected to a driving circuit (not shown).

The drain electrode 30 is electrically connected to the pixel electrode 14 through the drain contact hole 30 ′.

In addition, a storage capacitor C _st is formed in a portion of the gate line 22 to store charge together with the pixel electrode 14.

The operation of the active matrix liquid crystal display device described above is as follows.

When a voltage is applied to the gate electrode 26 of the switching thin film transistor S, the data signal is applied to the pixel electrode 14, and when the signal is not applied to the gate electrode 26, the voltage is applied to the pixel electrode 14. This is not authorized.

The manufacturing process of the liquid crystal panel constituting the liquid crystal display device is a complex process of several complex steps. In particular, the lower substrate on which the thin film transistor S is formed must go through several mask processes.

The performance of the final product is determined by this complex manufacturing process. Preferably, the simpler the process, the less likely it is that defects will occur. That is, since a number of major elements that determine the performance of the liquid crystal display are formed on the lower substrate, the manufacturing process should be simplified.

In general, the manufacturing process of the lower substrate is often determined by what material is used for each device to be made or designed according to the specification.

For example, in the past, a small liquid crystal display was not a problem, but in the case of a large area liquid crystal display of 12 inches or more, the resistivity value of the material used for the gate wiring is an important factor in determining the superiority of the image quality. Therefore, in the case of a large area liquid crystal display element, it is preferable to use a metal with low resistance, such as aluminum or an aluminum alloy.

In general, an inverted staggered type structure of a thin film transistor used in a liquid crystal display is generally used. This is because the structure is simple and the performance is excellent.

In addition, the reverse staggered thin film transistor is divided into a back channel etch type (EB) and an etch stopper type (ES) according to a channel forming method, and a simple back channel etch type structure is applied. The liquid crystal display device manufacturing process will be described.

Hereinafter, a manufacturing process of a conventional active matrix liquid crystal display device will be described with reference to FIGS. 3A to 3E. 3A to 3E are cross-sectional views taken along cut lines A-A and B-B of FIG. 2 for ease of description.

First, a foreign material or an organic material is removed from the substrate 1, and the metal film is deposited by sputtering after cleaning to improve the adhesion between the metal film of the gate material to be deposited and the glass substrate. .

3A is a step of forming a gate electrode 26 and a capacitor first electrode 22 by patterning with a first mask after the metal film deposition. The gate electrode 26 material, which is important for the operation of the active matrix liquid crystal display, is mainly composed of aluminum having low resistance to reduce the RC delay, but pure aluminum has low chemical resistance to corrosion and is healed in subsequent high temperature processes. In the case of aluminum wiring, it is used in the form of an alloy or a laminated structure is applied because it causes a wiring defect problem due to the formation of the hi-lock. The gate electrode 26 and the capacitor first electrode 22 have the same pattern and correspond to the gate wiring, and are functionally referred to as the gate electrode 26 and the capacitor first electrode 22.

Next, referring to FIG. 3B, after forming the gate electrode 26 and the capacitor first electrode 22, an insulating film 50 is deposited over the top and the entire exposed substrate. In addition, amorphous silicon (a-Si: H: 52), which is a semiconductor material, and amorphous silicon (n ⁺ a-Si: H: 54) containing impurities are deposited on the gate insulating film 50 in succession.

After the deposition of the semiconductor material, a pattern is formed with a second mask to form an active layer 55 and a semiconductor island 53 having the same shape as the active layer.

The amorphous silicon 54 containing the impurity is to reduce the contact resistance between the metal layer to be formed later and the active layer 55.

Thereafter, as shown in FIG. 3C, a metal layer is deposited and patterned with a third mask to form a source electrode 28 and a drain electrode 30. The data line 24 connected to the source electrode 28 is formed at the same time as the source and drain electrodes 28 and 30.

In addition, the capacitor second electrode 58 is formed on the capacitor first electrode 22 so as to overlap with a portion of the capacitor first electrode 22. In other words, the data line 24, the source electrode 28, the drain electrode 30, and the capacitor second electrode 58 are formed in the third mask process.

The ohmic contact layer existing between the source electrode 28 and the drain electrode 30 is removed using the source and drain electrodes 28 and 30 as a mask. If the ohmic contact layer between the source electrode 28 and the drain electrode 30 is not removed, a serious problem may occur in the electrical characteristics of the thin film transistor S, and a great problem may occur in performance.

Careful attention is required to removing the ohmic contact layer. In actual etching of the ohmic contact layer, since there is no etch selectivity with the active layer formed thereunder, the active layer is overetched by about 500 Å. The etching uniformity directly affects the characteristics of the thin film transistor S .

Thereafter, as shown in FIG. 3D, an insulating film is deposited and patterned with a fourth mask to form a protective film 56 to protect the active layer 55. The passivation layer 56 may adversely affect the characteristics of the thin film transistor due to the unstable energy state of the active layer 55 and the residual material generated during etching, so that the inorganic silicon nitride layer (SiN _x ) or the silicon oxide layer (SiO ₂ ) or the like may be adversely affected. It is formed of inorganic BCB (Benzocyclobutene).

The passivation layer 56 requires high light transmittance, properties of a moisture resistant and durable material.

A process of forming a contact hole during patterning of the passivation layer 56 is added. The data pad contact hole 23, the drain contact hole 30 ′, and the storage contact hole 58 ′ are respectively formed.

The data pad contact hole 23 is for contact between the transparent conductive film to be created in a later process and the data line 42, and the drain contact hole 30 ′ and the storage contact hole 58 ′ are pixel electrodes. For contact with

The process illustrated in FIG. 3E is a process of forming a pixel electrode 14 by depositing a transparent conductive oxide (TCO) and patterning it with a fifth mask. ITO (Indium Tin Oxide) is mainly used as the transparent conductive material. The pixel electrode 14 is in contact with the capacitor second electrode 58 and is in electrical contact with the drain electrode 30 through the drain contact hole 30 ′.

By the above-described process, the thin film transistor substrate of the liquid crystal display device is completed.

The manufacturing method of the active matrix liquid crystal display described above is a five mask method used basically. However, when the gate electrode is used as aluminum in the process of forming the thin film transistor, at least two masks are needed to solve the problem of hillock that may occur on the aluminum surface. Therefore, at least five to six mask processes are required to construct the thin film transistor substrate.

The mask process used in manufacturing a thin film transistor substrate used in a liquid crystal display device involves various processes such as cleaning, deposition, baking, and etching. Therefore, even if the mask process is shortened once, the manufacturing time is considerably reduced, which is advantageous in terms of production yield and manufacturing cost.

Therefore, the manufacturing method of the liquid crystal display which reduces the number of masks in the manufacturing process of the above conventional liquid crystal display device was researched / developed.

4A to 4D are process diagrams illustrating a process of manufacturing a thin film transistor array panel using only four masks in the method of manufacturing a liquid crystal display device.

First, FIG. 4A illustrates the steps of depositing a first metal and forming a gate electrode 102 using a first mask. When the gate electrode 102 is formed, the adjacent gate wiring 101 is also formed at the same time. The adjacent gate wiring 101 serves as an electrode of a storage capacitor later.

As the first metal used to form the gate electrode 102, chromium (Cr), molybdenum (Mo), or the like may be generally used.

FIG. 4B sequentially deposits the gate insulating layer 150 and the semiconductor layers 152 and 154 over the first metals 101 and 102 patterned with the first mask and the entire surface of the exposed substrate, and then the semiconductor ( 152, 154) shows a step of depositing a protective film 158 after depositing a second metal in succession over the entire upper surface of the layer and patterning with a second mask. In this case, the semiconductor layers 152 and 154 may be classified into a pure semiconductor layer 152 and a semiconductor 154 layer containing impurities.

In other words, the process illustrated in FIG. 4B is a combination of various processes, in which a second metal is deposited and patterned with a second mask to form the source and drain electrodes 110 and 108 and the gate wiring protection electrode 156. Form.

The exposed impurity semiconductor layer 154 is removed using the patterned second metal (source and drain electrodes and gate wiring protection electrodes) as a mask to form a channel between the source electrode 110 and the drain electrode 108. (Channel) is formed.

In more detail, the semiconductor layer 154 containing impurities, which are part of the semiconductor layer, is removed using the source and drain electrodes patterned by the second mask and the gate wiring protection electrode as masks.

After removing the semiconductor layer 154 containing the impurity, a protective film 158 is formed.

FIG. 4C is a diagram illustrating a process that can be said to be the most important part in manufacturing a liquid crystal display using only four masks.

4C illustrates that the passivation layer 158 is patterned with a third mask to form a drain contact hole 114 to expose the source and drain electrodes 110 and 108 and a portion of the drain electrode. All parts are etched.

At this time, the region where the patterned protective film exists is the region B shown in Fig. 4C. The patterned passivation layer covers the upper portion of the channel portion CH.

In addition, after the protective layer patterning, the second metal layer formed on the portion excluding the patterned protective layer B and the semiconductor layer formed thereunder are simultaneously etched.

The drain contact hole 114 is formed at a predetermined position on the drain electrode 108. The drain contact hole 114 is formed to communicate from an upper portion of the patterned passivation layer B to an upper portion of the gate insulating layer.

In this case, the portion to be etched may be divided into two regions. That is, the protection layer may be divided into a region A in which the passivation layer, the pure semiconductor layer, and the gate insulation layer are etched, and a region C in which the passivation layer, the second metal, and the semiconductor layer are etched.

That is, the region etched in the third mask process may be divided into two parts. That is, the area A and the area C, which are only the portions that are finally etched, are described. In the area A, the passivation layer 158, the pure semiconductor layer 152, and the gate insulating layer 150 are simultaneously etched to form a substrate ( 1) is an exposed region, and in the C region, the passivation layer 158, the gate wiring protection unit 156 which is the second metal layer, and the impurity and pure semiconductor layers 154 and 152 are etched to finally expose the gate insulation layer 150. Area.

In other words, the A region and the C region are etched at the same time, and the reason why the gate insulating layer is finally exposed to the C region is that the second metal layer is etched when the C region is etched. This is because the metal layer prevents etching of the gate insulating film formed under the metal layer.

Accordingly, the gate insulating film 150 is finally left on the gate wiring 101, thereby preventing damage to the gate wiring 101 due to the exposure of the gate wiring 101, which may occur in a later process.

FIG. 4D is a diagram illustrating a step of forming a pixel electrode 116 by depositing a transparent conductive film and patterning with a fourth mask. In this case, the contact between the drain electrode 108 and the pixel electrode 116 is in side contact with the drain contact hole 114.

The pixel electrode 116 is formed to overlap the gate line 101 by a predetermined area, so as to form a storage capacitor Cst. That is, the storage capacitor Cst is formed at a portion where the gate wiring 101 and the pixel electrode 116 overlap.

As described above, since the liquid crystal display can be manufactured using only four mask processes, the yield of the product can be improved.

The conventional method of manufacturing the liquid crystal display device described above uses the source / drain metal, which is the second metal layer, to expose the gate wiring, which may be a problem in manufacturing the liquid crystal display device using only four masks. It was characterized by a protective box.

However, short defects due to impurities may occur in the manufacturing process of the storage capacitor of FIG. 4D. That is, a problem of the liquid crystal display of the conventional four masks will be described with reference to FIGS. 5A and 5B as follows.

FIG. 5A is a diagram illustrating a step after the second mask process of FIG. 4B centering on a storage capacitor Cst.

As illustrated in the drawing, when the gate wiring protection electrode 156 is formed as the second metal layer, the foreign substance P may fall on the impurity semiconductor layer 154.

The foreign substance P is inhibited from forming the gate wiring protection electrode 156. That is, the gate wiring protection electrode 156 is not formed around the foreign substance P.

As described above, when the gate wiring protection electrode 156 is not formed at any one portion (that is, a portion in which foreign matter is formed), serious defects may be caused.

FIG. 5B is a view illustrating the storage capacitor Cst in the etching process and the pixel electrode formation process of FIGS. 4C and 4D (the etching portion of the region C of FIG. 4C).

As shown in the drawing, when the protective layer 158 and the gate wiring protection electrode 156 in the lower portion of FIG. In this case, the gate electrode 150 is etched because the gate insulating layer 150 does not serve as an etch stop layer. Therefore, when the pixel electrode 116 is formed, the pixel electrode 116 and the gate wiring 101 are shorted to the etched gate insulating layer 150.

As described above, when the pixel electrode 116 and the gate wiring 101 are shorted, the storage capacitor may be defective, which may cause a fatal defect in the image quality of the precursor.

An object of the present invention is to ensure a stable manufacturing process in the liquid crystal display device manufactured by the four masks as described above.

1 is a cross-sectional view showing a cross section corresponding to one pixel portion of a general liquid crystal display device.

2 is a plan view illustrating a plane corresponding to one pixel part of a general liquid crystal display;

3A to 3E are process diagrams showing a process of cross sections along cut lines A-A and B-B of FIG.

4A to 4D are process diagrams illustrating a fabrication process of a cross section corresponding to one pixel portion of a conventional liquid crystal display device of four masks.

5A and 5B illustrate a manufacturing process of the storage capacitor of FIG. 4D.

6A to 7D are process diagrams illustrating a manufacturing process of a storage capacitor of a liquid crystal display according to the present invention.

7 is a cross-sectional view showing a cross section of a thin film transistor according to the present invention;

<Explanation of symbols for the main parts of the drawings>

200: gate wiring 202: gate insulating film

204: pure semiconductor layer 206: impurity semiconductor layer

208: first gate wiring protection electrode 210: second gate wiring protection electrode

201: gate electrode 220: source electrode

222: drain electrode 214: pixel electrode

212: protective film 230: drain contact hole

In order to achieve the above object, the present invention includes a first step comprising a substrate; Depositing a first metal layer on the substrate and patterning with a first mask to form a gate wiring; A third step of sequentially depositing a gate insulating film, a pure semiconductor layer, an impurity semiconductor layer, and second and third metal layers over the entire surface of the substrate on which the gate wiring is formed; Patterning the second and third metal layers with a second mask to form source and drain electrodes, first and second gate line protection parts, and a semiconductor channel; Depositing a protective film over the entire surface of the second and third metal layers patterned with the second mask; A sixth step of covering the source and drain electrodes and the channel portion with a third mask, patterning a portion of the drain electrode to be exposed, and etching a portion other than the patterned protective layer; Depositing a transparent conductive electrode over the entire substrate including the data line and source and drain electrodes; And forming an storage capacitor by overlapping the transparent conductive electrode with a portion of the gate line, and patterning the pixel electrode by contacting the drain electrode with a fourth mask to form a pixel electrode. Provide a method.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the method of manufacturing a liquid crystal display according to the present invention, a defect of a storage capacitor that may occur in a liquid crystal display manufactured by a conventional four mask is deposited twice over a metal layer used as a gate wiring protection electrode and a source and drain electrode. To solve this problem.

Therefore, in the manufacturing method of the liquid crystal display device of the conventional 4 mask, detailed description of a similar process is abbreviate | omitted.

In addition, since the present invention solves the defects of the storage capacitor unit, a description will be given focusing on the storage capacitor.

6A through 6D are process diagrams illustrating a process of manufacturing a storage capacitor in the liquid crystal display according to the present invention.

First, FIG. 6A is a diagram illustrating a step of forming the gate wiring 200 on the substrate 1 using the first metal layer.

In general, the storage capacitor is composed of two electrodes and a dielectric layer formed between the two electrodes, and the gate wiring 200 serves as one of the two electrodes.

FIG. 6B sequentially deposits a gate insulating film 202, a pure semiconductor layer 204, an impurity semiconductor layer 206, a second metal layer, and a third metal layer on the gate wiring 200, and the second and third metal layers. Are etched to form first and second gate wiring protection electrodes 208 and 210, respectively.

Although not shown, the second and third metal layers are formed of source and drain electrodes, respectively (described in FIG. 7).

After the first and second gate wiring protection electrodes 208 and 210 are formed, the impurity semiconductor layer 206 adjacent to the first gate wiring protection electrode 208 is etched using the mask as a mask. Accordingly, the impurity semiconductor layer 206 is removed at portions except the lower portions of the first and second gate wiring protection electrodes 208 and 210.

A protective film 212 is formed on the second gate wiring protection electrode 210.

6C is a portion of the gate line 200 except the gate insulating layer 202 to be etched to form a dielectric layer of the storage capacitor in a process similar to that of FIG. 4C illustrating a conventional method of manufacturing a liquid crystal display.

Here, in the present invention, two layers of metal are used to form the gate wiring protection electrode.

That is, a third metal layer is additionally deposited on the second metal layer to remove defects generated in the first gate wiring protection electrode 208 by foreign matter P ₁ , which may be generated when the second metal layer is formed. The second gate wiring protection electrode 210 is formed.

In addition, even if the foreign material P ₂ is formed in the second gate wiring protection electrode 210, a defect does not occur by the first gate wiring protection electrode 208 formed under the second gate wiring protection electrode 210.

In other words, if the gate wiring protection electrode is formed of a single metal layer, the gate insulating film 202 may be damaged in the process of FIG. 6C due to the foreign matter. Even if this occurs, the gate insulating layer 202 is not damaged because the gate wiring protection electrodes compensate for this.

FIG. 6D illustrates a step of forming the pixel electrode 214 on the gate insulating layer 202.

Here, the pixel electrode 214 overlapping the gate line 200 functions as the other electrode of the storage capacitor. In addition, the gate insulating layer 202 formed on the gate line 200 may function as a dielectric layer of the storage capacitor.

The thickness of the second and third metal layers is preferably 500 Pa or more.

In addition, after forming the second metal layer, if the foreign matter formed on the second metal layer is removed by cleaning and the third metal layer is formed, the protective effect of the gate insulating layer will be further increased.

7 is a cross-sectional view illustrating a thin film transistor as a switching element of a liquid crystal display according to the present invention.

As shown in the drawing, the gate electrode 201 of the first metal layer is formed on the substrate 1, and the gate insulating layer 202 is formed on the gate electrode 201.

In addition, an active layer 205 is formed on the gate insulating layer 202 on the gate electrode 201, and source and drain electrodes 220 and 222 are formed of second and third metal layers on the active layer 205. .

In addition, a passivation layer 212 is formed on the source and drain electrodes 220 and 222, and the passivation layer 212 on the drain electrode 222 communicates from the passivation layer 212 to the lower gate insulating layer 202. The drain contact hole 230 is formed.

In addition, a pixel electrode 214 in contact with the drain electrode 22 through the drain contact hole 230 is formed in the passivation layer 212.

Here, the source and drain electrodes 220 and 222 are made of double metals of second and third metals, respectively.

In addition, the drain electrode 222 and the pixel electrode 214 are in contact with the side surface of the drain electrode 222 through a drain contact hole penetrating through the drain electrode 222.

Since the drain electrode 22 is formed of two layers of metal, the contact area of the pixel electrode in contact with the side surface is larger than that of the liquid crystal display device manufactured by the conventional four masks.

Therefore, in the liquid crystal display according to the present invention, the contact resistance between the drain electrode and the pixel electrode is reduced to less than half of the conventional art.

When the liquid crystal display is manufactured by the embodiments of the present invention described above has the following characteristics.

First, when the liquid crystal display device is manufactured by the method of manufacturing the liquid crystal display device according to the embodiments of the present invention, the manufacturing time is shortened because only four mask processes may be manufactured.

Second, since the thin film transistor substrate can be configured with four masks, it is possible to prevent a decrease in yield due to misalignment.

Third, there is a cost reduction effect due to the reduction of the manufacturing process of the liquid crystal display device.

Fourth, the short-circuit defect of the storage capacitor, which may be caused by manufacturing the liquid crystal display device in the fourth mask process, is finally formed by using the gate wiring protection electrodes using the second and third metal layers to form the gate insulating layer, thereby causing storage capacitors caused by foreign substances. There is an advantage to reduce the defects.

Fifth, the liquid crystal display according to the present invention has an advantage of reducing the increase in contact resistance that may occur during side contact between the pixel electrode and the drain electrode by increasing the thickness of the drain electrode in side contact.

Claims (8)

A first step comprising a substrate; Depositing a first metal layer on the substrate and patterning with a first mask to form a gate wiring; A third step of sequentially depositing a gate insulating film, a pure semiconductor layer, an impurity semiconductor layer, and second and third metal layers over the entire surface of the substrate on which the gate wiring is formed; Patterning the second and third metal layers with a second mask to form source and drain electrodes, first and second gate line protection parts, and a semiconductor channel; Depositing a protective film over the entire surface of the second and third metal layers patterned with the second mask; A sixth step of covering the source and drain electrodes and the channel portion with a third mask, patterning a portion of the drain electrode to be exposed, and etching a portion other than the patterned protective layer; Depositing a transparent conductive electrode over the entire substrate including the data line and source and drain electrodes; An eighth step of forming a storage capacitor by forming the transparent conductive electrode to overlap with a portion of the gate wiring, and forming a pixel electrode by patterning with a fourth mask to contact the drain electrode Array substrate manufacturing method of the liquid crystal display device comprising a. An array of liquid crystal display devices manufactured by the method for manufacturing a liquid crystal display device of claim 1. The method according to claim 1, The transparent conductive electrode is a material selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO) array substrate manufacturing method of a liquid crystal display device. The method according to claim 1, The storage capacitor includes a gate wiring as one electrode, a pixel electrode overlapping the gate wiring as another electrode, and a gate insulating layer interposed between the gate wiring and the pixel electrode overlapping the gate wiring as a dielectric layer. Array substrate manufacturing method of the. The method according to claim 1, Forming the semiconductor channel further comprises removing the exposed impurity semiconductor layer after patterning the second metal layer. The method according to claim 1, The etched region of the portion excluding the patterned passivation layer on the source and drain electrodes of the fourth step is divided into two parts, a region in which the patterned second and third metal layers exist and a region in which the patterned second and third metal layers do not exist. An array of liquid crystal display devices in which the protective layer, the second and third metal layers, and the pure semiconductor layer are etched and the region in which the patterned second and third metal layers do not exist are etched in the protective film, impurities, and the pure semiconductor layer and the gate insulating layer. Substrate manufacturing method. The method according to claim 1, And forming a drain contact hole communicating the passivation layer, the drain electrode, the impurity, and the pure semiconductor layer in the sixth step such that the drain electrode and the pixel electrode contact each other. The method according to claim 7, And the contact between the drain electrode and the pixel electrode is in contact with the side surface of the drain electrode exposed to the inner diameter of the drain contact hole through the drain contact hole communicating with the drain electrode.