KR20010059006A - A method for forming a fuse of a semiconductor device - Google Patents
A method for forming a fuse of a semiconductor device Download PDFInfo
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- KR20010059006A KR20010059006A KR1019990066384A KR19990066384A KR20010059006A KR 20010059006 A KR20010059006 A KR 20010059006A KR 1019990066384 A KR1019990066384 A KR 1019990066384A KR 19990066384 A KR19990066384 A KR 19990066384A KR 20010059006 A KR20010059006 A KR 20010059006A
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- poly layer
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- contact plug
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- 238000000034 method Methods 0.000 title claims abstract description 31
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 239000010410 layer Substances 0.000 claims abstract description 74
- 239000002184 metal Substances 0.000 claims abstract description 19
- 239000011229 interlayer Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 239000010408 film Substances 0.000 claims 5
- 239000010409 thin film Substances 0.000 claims 1
- 230000010354 integration Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/62—Protection against overvoltage, e.g. fuses, shunts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체소자의 퓨즈 형성방법에 관한 것으로, 특히 고전압에서 드레인 접합영역의 브레이크다운 전압 ( breakdown voltage ) 에 안정적으로 동작할 수 있는 트랜지스터를 구현하는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a fuse of a semiconductor device, and more particularly, to a technique for implementing a transistor capable of stably operating at a breakdown voltage of a drain junction region at a high voltage.
일반적으로, 전 공정을 다 거친 웨이퍼는 바로 테스트를 하여 리페어 ( repair ) 를 하게 된다.In general, wafers that have been through the entire process are tested and repaired immediately.
그러나, 패키지가 되고 나면 리페어가 불가능해 진다. 이렇게 패키지를 하고 난 후에 페일이 나는 칩이 전체의 5 퍼센트 정도 된다.However, once packaged, repair is impossible. After this package, the failing chip is about 5 percent of the total.
그리하여, 요즘은 패키지를 하고 난 후에도 리페어가 가능하도록 안티 퓨즈 ( anti-fuse ) 를 사용하고 있다.Thus, these days, anti-fuse is used to repair even after package.
그러나, 이것은 기존의 메모리 칩에서 사용하지 않던 고전압을 필요로 하게 된다.However, this requires a high voltage that is not used in conventional memory chips.
그래서, 기존의 주변회로부의 트랜지스터 드레인에 걸리던 전압보다 훨씬 높은 전압이 걸리게 된다.Therefore, a voltage much higher than that of the transistor drain of the existing peripheral circuit part is applied.
기존에 사용하는 트래지스터는, 웰을 구성하고 그 웰에 트랜지스터 채널용으로 이온주입을 다시 실시한다. 이렇게 형성된 트랜지스터는 채널 농도가 높기 때문에 문턱전압이 대략 1 볼트 근방이다.A conventionally used transistor forms a well and performs ion implantation again in the well for the transistor channel. The transistor formed in this way has a high channel concentration, and thus the threshold voltage is about 1 volt.
그런데 반도체소자의 퓨즈 형성방법를 위해 마스크 공정을 추가하게 되면 비용 증가뿐만아니라 프로세스 시간도 증가하기 때문에 양산에는 적용할 수 없다.However, the addition of a mask process for the method of forming a fuse of a semiconductor device is not applicable to mass production because it increases not only the cost but also the process time.
그리고, 다른 일반적인 트랜지스터 때문에 채널쪽 농도를 마음대로 바꿀수가 없다.And, because of other common transistors, the channel side concentration cannot be changed at will.
도 1 은 종래기술에 따른 반도체소자의 퓨즈 형성방법을 도시한 단면도로서,히타치 ( hitachi ) 회사에서 사용하고 있는 퓨즈 형성방법을 도시한 것이다.FIG. 1 is a cross-sectional view illustrating a fuse forming method of a semiconductor device according to the prior art, and illustrates a fuse forming method used by Hitachi.
상기 퓨즈는, 폴리층(11)을 형성하고 상기 폴리층(11) 상측에 콘택되는 금속배선(15)을 형성한다.The fuse forms a poly layer 11 and forms a metal wiring 15 contacting the poly layer 11.
이때, 상기 금속배선(15)은 상기 폴리층(11)과 콘택플러그(13)를 통하여 접속된다.In this case, the metal wiring 15 is connected to the poly layer 11 through the contact plug 13.
상기 퓨즈의 동작은 폴리층(12)과 금속배선(15) 사이에 강한 바이어스를 가해 금속배선(15)을 끊는 방법으로 실시된다. (도 1)The operation of the fuse is performed by applying a strong bias between the poly layer 12 and the metal wiring 15 to break the metal wiring 15. (Figure 1)
상기한 바와같이 종래기술에 따른 반도체소자의 퓨즈 형성방법은, 회로 구현시 고전압으로 인하여 트랜지스터의 특성이 열화되고 이를 해결하기 위하여 추가되는 마스크 공정시 공정시간이 증가되어 반도체소자의 생산성을 저하시키는 문제점이 있으며, 평면적인 구조를 가지고 있어 레이아웃 상의 면적이 크고 그에 따른 반도체소자의 고집적화를 어렵게 하는 문제점이 있다.As described above, the fuse forming method of a semiconductor device according to the prior art has a problem that the characteristics of the transistor are deteriorated due to a high voltage when the circuit is implemented, and a process time is increased during an additional mask process to solve the problem, thereby lowering the productivity of the semiconductor device. In addition, there is a problem in that the planar structure has a large area on the layout, and thus high integration of the semiconductor device is difficult.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 금속배선을 반도체소자의 퓨즈로 사용하는 대신에 금속배선 콘택플러그를 퓨즈로 사용하여 소자 내부에서 발생되는 저전압으로 끊을 수 있는 구조를 형성함으로써 반도체소자의 레이아웃 면적을 감소시키고 저전압으로 퓨즈 동작을 구현할 수 있어 고전압으로 인한 반도체소자의 특성 열화를 방지하고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시키며 반도체소자의 고집적화를 가능하게 하는 반도체소자의 퓨즈 형성방법을 제공하는데 그 목적이 있다.The present invention is to solve the above problems of the prior art, by using a metal contact plug as a fuse instead of using a metal wiring as a fuse of the semiconductor device to form a structure that can be broken by a low voltage generated inside the device semiconductor Formation of fuses of semiconductor devices can be achieved by reducing the layout area of the device and implementing fuse operation at low voltage, thereby preventing deterioration of characteristics of semiconductor devices due to high voltages, thereby improving the characteristics and reliability of semiconductor devices, and enabling high integration of semiconductor devices. The purpose is to provide a method.
도 1 은 종래기술에 따른 반도체소자의 퓨즈 형성방법을 도시한 단면도.1 is a cross-sectional view showing a fuse forming method of a semiconductor device according to the prior art.
도 2a 및 도 2b 는 본 발명의 원리를 설명하기 위한 반도체소자의 퓨즈 형성방법을 도시한 단면도.2A and 2B are sectional views showing a fuse forming method of a semiconductor device for explaining the principle of the present invention.
도 3a 내지 도 3e 는 본 발명의 제1실시예 내지 제5실시예에 따른 반도체소자의 퓨즈 형성방법를 도시한 단면도 및 평면도.3A to 3E are cross-sectional views and a plan view showing a fuse forming method of a semiconductor device according to the first to fifth embodiments of the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
11,21,31,41,51 : 제1폴리층 13,25a,25b,33,43 : 콘택플러그11,21,31,41,51: First poly layer 13,25a, 25b, 33,43: Contact plug
15,23a,23b : 금속배선15,23a, 23b: metal wiring
17 : 금속배선 절단부분, 퓨즈 절단부분17: metal wire cutting part, fuse cutting part
27,35,47,53a,53b : 제2폴리층 45,57 : 제3폴리층27,35,47,53a, 53b: second poly layer 45,57: third poly layer
55 : 제1콘택플러그 59 : 제2콘택플러그55: first contact plug 59: second contact plug
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 퓨즈 형성방법는,In order to achieve the above object, a method of forming a fuse of a semiconductor device according to the present invention,
제1폴리층이 형성된 반도체기판 상부를 평탄화시키는 제1층간절연막을 형성하는 공정과,Forming a first interlayer insulating film to planarize the upper portion of the semiconductor substrate on which the first poly layer is formed;
상기 제1층간절연막 상부에 제2폴리층을 형성하는 공정과,Forming a second poly layer on the first interlayer insulating film;
상기 제2폴리층 상부에 제2층간절연막을 형성하는 공정과,Forming a second interlayer insulating film on the second poly layer;
상기 제2층간절연막과 제1층간절연막을 통하여 상기 제1폴리층에 콘택되는 금속배선 콘택플러그를 형성하되, 상기 제2폴리층과 일정폭 중접되게 형성되어 상기 제2폴리층 하측의 콘택플러그가 상기 제2폴리층 상측의 콘택플러그보다 작은 임계면적으로 구비되는 공정을 포함하는 것을 특징으로한다.A metal wiring contact plug is formed to be in contact with the first poly layer through the second interlayer insulating film and the first interlayer insulating film, and the contact plug under the second poly layer is formed to be in contact with the second poly layer at a predetermined width. And a critical area smaller than that of the contact plug above the second poly layer.
한편, 이상의 목적을 달성하기 위한 본 발명의 원리를 도 2 를 참고로 하여 설명하면 다음과 같다.On the other hand, the principle of the present invention for achieving the above object will be described with reference to FIG.
먼저, 반도체기판 상부에 제1폴리층(21)을 형성한다.First, the first poly layer 21 is formed on the semiconductor substrate.
그리고, 상기 제1폴리층(21) 상부를 평탄화시키는 제1층간절연막(도시안됨)을 형성하고, 그 상부에 제2폴리층(27)을 형성한다.A first interlayer insulating film (not shown) is formed to planarize an upper portion of the first poly layer 21, and a second poly layer 27 is formed thereon.
그 다음, 상기 제2폴리층(27) 상부에 제2층간절연막(도시안됨)을 형성한다.Next, a second interlayer insulating film (not shown) is formed on the second poly layer 27.
그리고, 상기 제1폴리층(21)이 노출되도록 금속배선 콘택홀을 형성하되, 상기 금속배선 콘택홀과 상기 제2폴리층(27)이 일정폭 중첩되도록 형성함으로써 바이어스가 가해지는 통로 ( path ) 는 금속배선(23a), 금속배선 콘택플러그(25a), 제1폴리층(21), 금속배선 콘택플러그(25b) 및 금속배선(23b)의 순서로 이루어 진다.In addition, a metal wiring contact hole is formed to expose the first poly layer 21, but the metal wiring contact hole and the second poly layer 27 are formed to overlap a predetermined width so that a bias is applied. Is formed in the order of the metal wiring 23a, the metal wiring contact plug 25a, the first poly layer 21, the metal wiring contact plug 25b and the metal wiring 23b.
상기한 콘택공정으로 인하여, 상기 제2폴리층(27) 하측에 형성되는 콘택홀은 상기 제2폴리층(27) 상측에 형성되는 콘택홀의 크기보다 작게 형성된다.Due to the above contact process, the contact hole formed below the second poly layer 27 is smaller than the size of the contact hole formed above the second poly layer 27.
여기서, 상기 제2폴리층(27)은 후속공정에서 바이어스가 가해질때 높은 저항이 유발되도록 하는 역할을 하여 상기 제2폴리층(27) 하측에 형성되는 콘택플러그(25a)가 끊어질 수 있도록 한다.Here, the second poly layer 27 serves to cause high resistance when a bias is applied in a subsequent process so that the contact plug 25a formed under the second poly layer 27 may be broken. .
그리고, 상기 제1폴리층(21) 하부에 절연막(29)을 형성하여 후속 콘택공정시 공정을 안정화시키고 바이어스 인가시 끊어지는 부분의 저항을 증가시킬 수도 있다. (도 2)In addition, the insulating layer 29 may be formed under the first poly layer 21 to stabilize the process during the subsequent contact process and to increase the resistance of the portion that is broken when the bias is applied. (Figure 2)
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 3a 내지 도 3e 는 본 발명의 제1,2,3,4,5실시예에 따른 반도체소자의 퓨즈 형성방법을 도시한 사시도로서, 상기 도 2 의 ⓐ 부분에서 콘택플러그와 제2폴리층만을 도시한 것이다.3A to 3E are perspective views illustrating a fuse forming method of a semiconductor device according to the first, second, third, fourth, and fifth embodiments of the present invention, in which only the contact plug and the second poly layer are shown in part 2 of FIG. It is shown.
도 3a 는 제2폴리층(27)이 중첩된 콘택플러그(25a)를 도시한 사시도로서, 상기 제2폴리층(27)의 하측에 형성된 콘택플러그(25a)가 상기 콘택플러그에 중첩되어 반원형태로 형성된 것을 도시한다.FIG. 3A is a perspective view illustrating a contact plug 25a in which a second poly layer 27 is overlapped. A contact plug 25a formed under the second poly layer 27 overlaps the contact plug to form a semicircular shape. It shows that formed into.
여기서, ⓧ 는 제2폴리층(27) 하측에 구비되는 콘택플러그(25a)의 단면도이다.Is a cross-sectional view of the contact plug 25a provided below the second poly layer 27.
도 3b 는 상기 제2폴리층(27) 하측에 구비되는 콘택플러그(25a)의 형태가 상기 상기 도 3a 에서 보다 적게 형성된 것을 도시한 사시도이다.3B is a perspective view showing that the shape of the contact plug 25a provided below the second poly layer 27 is smaller than that of FIG. 3A.
여기서, ⓨ 는 제2폴리층(27) 하측에 구비되는 콘택플러그(25a)의 단면도이다.Here, ⓨ is a sectional view of the contact plug 25a provided below the second poly layer 27.
도 3c 는 상기 도 2 의 원리를 이용하여 복수개의 퓨즈를 형성한 것을 도시한 사시도로서, 각각의 제1폴리(31)에 콘택되는 금속배선 콘택플러그(33)를 형성하되, 복수개의 콘택플러그와 중첩되는 제2폴리층(35)을 형성한 것이다.FIG. 3C is a perspective view illustrating the formation of a plurality of fuses using the principle of FIG. 2, wherein the plurality of contact plugs 33 are formed to contact the first poly 31. The overlapping second poly layer 35 is formed.
이때, 상기 제2폴리층(35)은 불순물이 도핑되지않은 폴리실리콘층으로서, 절연특성을 갖는 층이다.In this case, the second poly layer 35 is a polysilicon layer which is not doped with impurities and has an insulating property.
그리고, 상기 제2폴리층(35)은 다른 절연막으로 형성할 수도 있다.The second poly layer 35 may be formed of another insulating film.
도 3d 는 상기 도 3c 와 같은 구조로 제1폴리층(41)에 콘택되는 금속배선 콘택플러그(43)와 중첩되는 제2,3폴리층(47,45)을 형성한 것을 도시한 사시도로서, 상기 제2,3폴리층(47,45)은 상기 도 3c 에서 제2폴리층을 적층구조로 형성한 형태를 갖는 것이다.FIG. 3D is a perspective view illustrating the formation of second and third poly layers 47 and 45 overlapping the metal wire contact plugs 43 contacting the first poly layer 41 in the same structure as in FIG. 3C. The second and third poly layers 47 and 45 have a form in which the second poly layer is formed in a laminated structure in FIG. 3C.
도 3e 는 서로 다른 단차를 갖는 제1,2,3폴리층(51,53,57)에 형성된 다수개의 퓨즈를 도시한 사시도로서,FIG. 3E is a perspective view illustrating a plurality of fuses formed on the first, second, and third poly layers 51, 53, and 57 having different steps.
제1폴리층(41)에 콘택되며 제2폴리층(53a)에 중첩되는 제1콘택플러그(55)를 형성하고, 상기 제2폴리층(53b)에 콘택되며 제3폴리층(57)에 중첩되는 제2콘택플러그(59)를 형성한 것이다.A first contact plug 55 is formed to be in contact with the first poly layer 41 and overlap the second poly layer 53a, and is in contact with the second poly layer 53b and to the third poly layer 57. The second contact plug 59 overlapping with each other is formed.
이때, ⓑ 와 ⓒ 부분이 서로 다른 퓨즈를 구성하거나, 하나의 퓨즈를 형성할 수 있다.In this case, ⓑ and ⓒ may form different fuses, or may form one fuse.
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 퓨즈 형성방법은, 저전압으로 동작 가능하며 수직형 구조를 갖춰 적은 면적으로 고집적화를 가능하게 하는 퓨즈를 형성함으로써 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 효과를 제공한다.As described above, the fuse forming method of the semiconductor device according to the present invention improves the characteristics and reliability of the semiconductor device by forming a fuse that is operable at a low voltage and has a vertical structure to enable high integration with a small area. It provides an effect that enables high integration of semiconductor devices.
Claims (6)
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019990066384A KR100359158B1 (en) | 1999-12-30 | 1999-12-30 | A method for forming a fuse of a semiconductor device |
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| KR1019990066384A KR100359158B1 (en) | 1999-12-30 | 1999-12-30 | A method for forming a fuse of a semiconductor device |
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| JPH05129441A (en) * | 1991-10-31 | 1993-05-25 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
| JPH065707A (en) * | 1992-06-22 | 1994-01-14 | Oki Electric Ind Co Ltd | Fuse for semiconductor integrated circuit |
| JPH08316428A (en) * | 1995-05-22 | 1996-11-29 | Seiko Epson Corp | Semiconductor device |
| US5776826A (en) * | 1996-05-06 | 1998-07-07 | International Business Machines Corporation | Crack stop formation for high-productivity processes |
| KR100246191B1 (en) * | 1997-08-27 | 2000-03-15 | 김영환 | Method for manufacturing multi-layer anti-fuse of semiconductor device |
| US6242789B1 (en) * | 1999-02-23 | 2001-06-05 | Infineon Technologies North America Corp. | Vertical fuse and method of fabrication |
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