JPH08316428A - Semiconductor device - Google Patents

Abstract

PURPOSE: To reduce the leak current of an antifuse element in the state of non-current-conduction, by covering with an insulating film a part of a connection hole in which an amorphous cylinder layer is in contact with a metal wiring layer. CONSTITUTION: A first insulating film 202 and a first metal wiring layer 203 are formed on semiconductor 201. The first metal wiring layer 203 is covered with a second insulating film 204. A first connection hole 205 is made in the upper part of the first metal wiring layer 203 of the insulating film 204. A part of the surface of the first metal wiring layer 203 which surface is exposed by the first connection hole 205 is covered with a third insulating film 206. An amorphous silicon layer 207 is deposited so as to cover at least all the part of the bottom of the first connection hole 205 which part is not covered with the third insulating film 206. A second metal wiring layer 208 is formed on the amorphous silicon layer 207, and an antifuse is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable semiconductor device having an antifuse element.

[0002]

2. Description of the Related Art The structure of a conventional semiconductor device having an anti-fuse element will be described with reference to FIG. 1 by taking an example in which the anti-fuse element is provided between metal wiring layers. 1A and 1B are views showing the structure of the anti-fuse element. FIG. 1A is a plan view and FIG. 1B is a sectional view taken along line AA of FIG. A first insulating film 102 and a first metal wiring layer 103 are formed on a semiconductor 101. The first metal wiring layer 103 is the second insulating film 104.
The second insulating film 104 is covered with the first connection hole 1
05 is open. Further, an amorphous silicon layer 106 is formed so as to cover the first connection hole 105,
A second metal wiring layer 107 is formed from above.
The amorphous silicon layer 106 is formed on the bottom of the first connection hole 105 at the first metal wiring layer 103 and the second metal wiring layer 10.
It is sandwiched between 7. The above is the structure of the conventional anti-fuse element. In addition to the case where the anti-fuse element is provided between the metal wiring layers as shown in FIG. 1, there are cases where the anti-fuse is provided between the semiconductor and the metal wiring layer. In a semiconductor device having three or more metal wiring layers, the antifuse element may be provided between any metal wiring layers.

Normally, in an antifuse element, the amorphous silicon layer 106 has an insulating property in the as-formed state, and the first metal wiring layer 103 and the second metal wiring layer 10 are formed.
It is in a non-conducting state during 7. Here, when a voltage higher than a certain value is applied between the first metal wiring layer 103 and the second metal wiring layer 107 (hereinafter, the voltage at this time is referred to as a program voltage of the antifuse), the amorphous silicon layer 10
6 changes to a conductive state, and the first metal wiring layer 103 and the second metal wiring layer 103
The metal wiring layer 107 of is in a state of being electrically connected,
This state is maintained. In a semiconductor device having an antifuse element, a desired circuit and function can be obtained by applying a program voltage only to a necessary antifuse element to bring it into a conductive state. The normal operating voltage of the semiconductor device having the antifuse element is always kept lower than the program voltage of the antifuse element, and the state of the antifuse element does not change during normal use.

The change in the conduction state due to the application of the program voltage to the anti-fuse element is that a current flows through the amorphous silicon layer when the program voltage is applied, and at this time, the amorphous silicon and the metal of the metal wiring layer are alloyed with each other. It is thought to be due to. Then, alloying does not occur in the entire area where the amorphous silicon and the metal are in contact with each other, and for some reason, probably when the program voltage is applied, electric field concentration is likely to occur in the bent portion of the amorphous silicon layer or the metal wiring layer. Thus, alloying occurs only in a small part of the contact area between amorphous silicon and metal. Therefore, the dependence of the program voltage of the anti-fuse element on the area of the contact portion between the amorphous silicon and the metal is small.

[0005]

Although it has been stated that the anti-fuse element in the state before the application of the program voltage is in the non-conducting state, it is not actually in the completely insulating state but in the normal operating voltage. Even at, a small leakage current flows. Normally, a semiconductor device having an anti-fuse element has a unit of thousands or tens of thousands of anti-fuse elements. Therefore, even if the leakage current of each anti-fuse element is extremely small, it is generally considered as a whole. The amount of current cannot be ignored, and the power consumption of the semiconductor device as a whole is increased. Therefore, the leakage current in the non-conducting state of the anti-fuse element (hereinafter simply referred to as leakage current)
It is one of the effective methods to reduce the power consumption of the semiconductor device having the anti-fuse element.

Here, as a method of reducing the leakage current of the anti-fuse element, one is to increase the film thickness of the amorphous silicon layer, and the other is the contact area between the amorphous silicon layer of the anti-fuse element and the metal wiring layer ( Less than,
This area is called the element area of the antifuse element. However, this does not mean the area occupied by the element. ) Can be reduced. This is because the leakage current of the anti-fuse element has a characteristic that it largely depends on the element area and the film thickness of the amorphous silicon layer.

However, increasing the film thickness of the amorphous silicon layer increases the program voltage of the anti-fuse element and increases the design or use restrictions of the semiconductor device having the anti-fuse element, which is not practical. Further, reducing the element area of the antifuse element is nothing but reducing the diameter of the first connection hole 105 in the antifuse element having the conventional structure of FIG. It is practically impossible to reduce the diameter of the connection hole, which is often set, unless the capacity of the manufacturing apparatus is improved. Therefore, it is difficult to reduce the leakage current of the anti-fuse element, There is a problem that the power consumption of the semiconductor device having the anti-fuse element cannot be reduced.

[0008]

Therefore, in the semiconductor device of the present invention, an anti-fuse element in which the element area is reduced by covering a part of the connection hole which was conventionally in contact with the amorphous silicon layer and the metal wiring layer with an insulating film. , Or having an anti-fuse element whose element area is reduced by covering a part of the connection hole with a metal wiring layer,
(EN) Provided is a semiconductor device which has a small leakage current in a non-conducting state of an antifuse element regardless of measures such as improvement of the capability of a manufacturing apparatus, and thus consumes less power and has the same program voltage as that of a conventional antifuse element. The purpose is to

[0009]

The structure of a semiconductor device according to the present invention will be described in detail below with reference to the drawings.

2A and 2B are views for explaining the structure of an anti-fuse element included in the semiconductor device of the present invention. FIG. 2A is a plan view and FIG. 2B is a section A-A in FIG. 2A. FIG. Further, FIG. 2 shows a structure in which an anti-fuse element is provided between metal wiring layers.

A first insulating film 202 and a first metal wiring layer 203 are formed on a semiconductor 201. The first metal wiring layer 203 is covered with a second insulating film 204, and a first connection hole 205 is formed in a portion of the second insulating film 204 above the first metal wiring layer 203. . Further, the third insulating film 206 is formed so as to cover a part of the bottom of the first connection hole 205, that is, a part of the surface of the first metal wiring layer 203 exposed by the first connection hole 205. An amorphous silicon layer 207 is deposited and molded so as to cover at least a portion of the bottom of the first connection hole 205 which is not covered with the third insulating film 206, and a second metal wiring layer 208 is formed thereon. And forms an anti-fuse element. In FIG. 2, the amorphous silicon layer 207 is the first contact hole 2
However, it is not necessary to cover the entire surface, and it is formed so that at least the first metal wiring layer 203 and the second metal wiring layer 208 do not come into direct contact with each other.
The first metal wiring layer 203 and the second metal wiring layer 208 are connected to other elements such as transistor elements and other wiring layers as needed to form a circuit, and the semiconductor device is formed as a whole.

In the antifuse element of the present embodiment, the third insulating film 2 is larger than the element area (contact area between the amorphous silicon layer and the metal wiring layer) of the conventional antifuse element.
Since the element area is small by the amount covered with 06, the leakage current is small. Note that as the element area of the anti-fuse element, the smaller area of the contact areas of the amorphous silicon layer and the metal wiring layers above and below it may be considered. This is because, of the current flowing through the amorphous silicon layer, the component in the surface direction is small and can be ignored when viewed from the component in the film thickness direction of the amorphous silicon layer.

The material of each portion in this embodiment will be described. The first metal wiring layer 203 is a multilayer film composed of four layers including a titanium layer, a titanium nitride layer, an aluminum alloy layer, and an alloy layer of titanium and tungsten from the bottom. Yes, the first insulating film 2
02 and the second insulating film 204 are made of silicon oxide (SiO 2
2), silicon nitride (SiNx) is used here for the third insulating film 206. In addition, the second metal wiring layer 2
Reference numeral 08 is a multilayer film including a titanium layer, a titanium nitride layer, an aluminum alloy layer, and a titanium nitride layer from the bottom. The uppermost titanium / tungsten alloy layer of the first metal wiring layer 203 and the lowermost titanium layer of the second metal wiring layer 208 are alloyed with an aluminum alloy layer and an amorphous silicon layer without applying a program voltage. It has a role of suppressing the reaction, and titanium nitride may be used for the uppermost layer of the first metal wiring layer 203.

Although silicon in the amorphous state is basically used as the silicon forming the amorphous silicon layer 207, the function as an antifuse can be provided by using amorphous silicon containing microcrystals or polycrystalline silicon. In order to improve the characteristics as an anti-fuse element, that is, in order to improve the insulation in the non-conducting state, and to reduce the resistance in the conducting state,
Nitrogen may be mixed into the silicon forming the amorphous silicon layer 207.

In FIG. 2, the anti-fuse element is provided between the first metal wiring layer and the second metal wiring layer counting from the bottom on the semiconductor, but three or more metal wiring layers are provided. ,
Even when an anti-fuse element is provided between any two layers of the metal wiring layer and the semiconductor, the element area of the anti-fuse can be reduced by using the same configuration as that of the present embodiment, and therefore the anti-fuse element area can be reduced. Power consumption of a semiconductor device having a fuse element can be reduced. This also applies to another embodiment described later.

FIG. 3 is a diagram for explaining another embodiment of the present invention, showing the structure of the antifuse element included in the semiconductor device of the present invention. 3A is a top view and FIG. 3B is FIG.
It is a longitudinal cross-sectional view between AA.

In FIG. 3, a third insulating film 304 is formed on the first metal wiring layer 303 formed on the first insulating film 302 on the semiconductor 301, and the third insulating film 304 is formed.
A second connection hole 305 is opened in the. A second insulating film 306 is provided thereover, and a first connection hole 307 is opened in the second insulating film 306. First connection hole 30
7, the position of the second connection hole 305 is offset, and part of the opening of the bottom of the first connection hole 307 is covered by part of the third insulating film 304. An amorphous silicon layer 308 is formed so as to cover the first connection hole 307, and a second
The metal wiring layer 309 is formed. The second metal wiring layer 309 faces the first metal wiring layer 303 with the amorphous silicon layer 308 sandwiched between the opening portions of both the second connection hole 305 and the first connection hole 307. Although the amorphous silicon layer 308 covers the entire surface of the second connection hole 305 in FIG. 3, it does not necessarily have to cover the entire surface, and at least the first metal wiring layer 303 and the second metal wiring layer 3 are formed.
It is formed so that 09 does not touch it directly. In FIG. 3, the third insulating film 304 is formed on the entire surface excluding the opening of the second connection hole 305, but the first insulating film 302 other than the portion overlapping the opening of the first connection hole 307. Is not always necessary and can be removed.

The material of each part of the antifuse element shown in FIG. 3 is the same as that of the antifuse element shown in FIG. 2 having the same name.

Also in the example of FIG. 3, the element area (the area where the first metal wiring layer and the amorphous silicon layer are in contact with each other) is smaller and the leakage current is smaller than that of the antifuse element having the conventional structure.

Still another embodiment of the present invention will be described with reference to FIG. FIG. 4A is a plan view of the anti-fuse element, and FIG. 4B is a sectional view taken along line AA of FIG.

A first insulating film 402 and a first metal wiring layer 403 are sequentially formed on the semiconductor 401 from the bottom. The first metal wiring layer 403 is covered with the second insulating film 404,
A first connection hole 405 is formed in a portion of the second insulating film 404 above the first metal wiring layer 403. The amorphous silicon layer 406 is formed so as to cover the first connection hole 405.
Is formed, and the second metal wiring layer 407 is formed thereon. The second metal wiring layer 407 is arranged so that at least one end crosses the bottom surface of the first connection hole 405.

The element area of the anti-fuse element of this embodiment is such that the first metal wiring layer 403 and the second metal wiring layer 407 face each other across the amorphous silicon layer 406 in the bottom portion of the first connection hole 405. The area of the antifuse element is smaller than the area of the connection hole, and therefore the leakage current is also small.

FIGS. 5 and 6 to be described below are examples in which, in the semiconductor device of the present invention, an anti-fuse element is formed at a connection portion of a so-called plug structure in which a buried metal is used for connection between semiconductors or metal wiring layers. .

FIG. 5 shows the structure of an anti-fuse element in the case where the semiconductor device of the present invention has interconnections of a so-called plug structure. FIG. 5A is a plan view, and FIG. 5B is FIG.
It is sectional drawing between AA of.

In FIG. 5, a first insulating film 502 and a first metal wiring layer 503 are formed in order from the bottom on a semiconductor 501. The second insulating film 504 and the second
Has a first connecting hole 505 formed in the insulating film 504 of the first insulating film 504, and the first connecting hole 505 is a buried metal (hereinafter referred to as a plug).
It is embedded at 506. Tungsten metal is often used as the material of the plug 506. Plug 506
Is covered with an amorphous silicon layer 507, and a third insulating film 508 is formed thereover so as to overlap a part of the top of the plug 506. Further, a second metal wiring layer 509 is formed so as to face the plug 506 with the amorphous silicon layer 507 sandwiched therebetween to form an anti-fuse element.

In the embodiment of FIG. 5, the third insulating film 508 is used.
By setting the above, the element area of the anti-fuse element, which is originally the same as the area of the top of the plug 506, can be reduced to reduce the leakage current, and the program voltage mainly depends on the film thickness of the amorphous silicon layer 507. Does not affect much. Therefore, the semiconductor device having the anti-fuse element having the structure as shown in FIG.
The power consumption is smaller than that of a semiconductor device having an anti-fuse element that does not have 8, and the program voltage remains almost unchanged.

FIG. 6 is a view for explaining another example of the antifuse element in the case where the semiconductor device of the present invention has a so-called plug-structure interconnection connection, which is different from FIG. FIG. 6A is a plan view illustrating the structure of the anti-fuse element, and FIG. 6B is a sectional view taken along line AA of FIG.

In FIG. 6, a first insulating film 602 and a first metal wiring layer 603 are sequentially formed on the semiconductor 601 from the lower layer, and a first connection hole 605 is formed in the upper second insulating film 604. It is open. The first connection hole 605 is filled with a plug 606, and the top of the plug 606 is covered with an amorphous silicon layer 607. Further, the second metal wiring layer 608 is formed so as to overlap only a part of the top portion of the plug 606 with the amorphous silicon layer 607 interposed therebetween to form an anti-fuse element.

In the anti-fuse element of FIG. 6, the element area is the portion where the second metal wiring layer 608 and the top of the plug 606 overlap, and the element when the second metal wiring layer 608 completely overlaps the top of the plug 606. It is clear that it is smaller than the area.

The material of each part of the antifuse shown in FIGS. 4 to 6 is the same as the correspondingly named part shown in FIG. 2 except for the plug (embedded metal).

[0031]

As described above, according to the present invention, in the semiconductor device having the anti-fuse element, the element area of the anti-fuse element can be reduced without improving the performance of the semiconductor manufacturing apparatus. Therefore, the power consumption can be reduced as compared with the conventional semiconductor device having the antifuse. Further, since it is not necessary to change the film thickness of the amorphous silicon layer that mainly determines the program voltage of the antifuse element, it is possible to obtain a semiconductor device having an antifuse element in which the program voltage is the same as the conventional one.

[Brief description of drawings]

1A and 1B are views showing a structure of an anti-fuse element included in a conventional semiconductor device, in which FIG. 1A is a plan view and FIG. 1B is a sectional view taken along line AA in FIG.

2A and 2B are diagrams showing a structure of an anti-fuse element included in a semiconductor device of the present invention, FIG. 2A is a plan view, and FIG. 2B is a sectional view taken along line AA in FIG.

FIG. 3 is a diagram showing another example of the structure of the anti-fuse element included in the semiconductor device of the present invention, FIG.
(B) is sectional drawing between AA of (a).

FIG. 4 is a diagram showing another example of the structure of the anti-fuse element included in the semiconductor device of the present invention, FIG.
(B) is sectional drawing between AA of (a).

FIG. 5 is a diagram showing a structure of an anti-fuse element included in the semiconductor device of the present invention, which is an example of a so-called plug structure. (A) is a top view, (b) is a sectional view between AA of (a).

FIG. 6 is a diagram showing a structure of an anti-fuse element included in the semiconductor device of the present invention, which is another example of a so-called plug structure. (A) is a top view, (b) is a sectional view between AA of (a).

[Explanation of symbols]

101, 201, 301, 401, 501, 601
..Semiconductor 102, 202, 302, 402, 502, 602.
..First insulating films 103, 203, 303, 403, 503, 603
..First metal wiring layer 104, 204, 306, 404, 504, 604
..Second insulating film 105, 205, 307, 405, 505, 605
..First connection holes 106, 207, 308, 406, 508, 607
..Amorphous silicon layer 107, 208, 309, 407, 509, 608.
..Second metal wiring layer 206, 304, 507 ... Third insulating film 305 ... Second connection hole 506, 606 ... Plug (embedded metal)

Claims (4)

[Claims] 1. A semiconductor layer or a first metal wiring layer, at least a first insulating film covering the semiconductor layer or the first metal wiring layer, and a connection hole formed in the first insulating film. A second insulating film that covers a part of the bottom of the connection hole, an amorphous silicon layer that covers at least a portion of the bottom of the connection hole that is not covered by the second insulating film, the semiconductor layer or the first A semiconductor device comprising an anti-fuse element including a first metal wiring layer and a second metal wiring layer facing the connection hole with the amorphous silicon layer interposed therebetween. 2. A semiconductor layer or a first metal wiring layer, at least a first insulating film covering the semiconductor layer or the first metal wiring layer, and a connection hole formed in the first insulating film. A buried metal that fills the connection hole and connects to the first metal wiring layer, a second insulating film that covers a part of the top of the buried metal, and at least the second insulation of the top of the buried metal. A semiconductor device comprising an anti-fuse element including an amorphous silicon layer that covers all portions not covered with a film, and a second metal wiring layer that faces the embedded metal with the amorphous silicon layer interposed therebetween. 3. A semiconductor layer or a first metal wiring layer, at least a first insulating film covering the semiconductor layer or the first metal wiring layer, and a connection hole formed in the first insulating film. The amorphous silicon layer that covers the connection hole and the second semiconductor layer that faces the connection hole with the semiconductor layer or the first metal wiring layer sandwiching the amorphous silicon layer, and has at least one end in the bottom portion of the connection hole. A semiconductor device having an anti-fuse element including a metal wiring layer. 4. At least a semiconductor layer or a first metal wiring layer, a first insulating film covering the semiconductor layer or the first metal wiring layer, and a connection hole formed in the first insulating film. A buried metal that fills the connection hole and connects to the first metal wiring layer; an amorphous silicon layer that covers the top of the buried metal; and a part of the buried metal that faces the buried amorphous metal layer. A semiconductor device having an anti-fuse element including a second metal wiring layer.