KR100246191B1 - Method for manufacturing multi-layer anti-fuse of semiconductor device - Google Patents

Method for manufacturing multi-layer anti-fuse of semiconductor device Download PDF

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KR100246191B1
KR100246191B1 KR1019970041490A KR19970041490A KR100246191B1 KR 100246191 B1 KR100246191 B1 KR 100246191B1 KR 1019970041490 A KR1019970041490 A KR 1019970041490A KR 19970041490 A KR19970041490 A KR 19970041490A KR 100246191 B1 KR100246191 B1 KR 100246191B1
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conductor
layer
forming
insulating layer
fuse
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KR1019970041490A
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KR19990018323A (en
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김진수
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김영환
현대반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

본 발명은 전도체와 전도체 사이에 형성되어 일정 이상의 과전압이 가해지면 도통되는 반도체 장치의 안티퓨즈 제조방법에 관한 것으로, 기판 상에 제1전도체를 형성하는 공정과; 기판 상에 제1전도체를 덮는 절연층을 형성하는 단계와, 절연층을 패터닝하여 제1전도체의 소정 부분을 노출시키는 접촉홀을 형성하는 단계와, 접촉홀 내에 제1전도체와 접촉된 플러그를 형성하는 단계와, 절연층 상에 플러그를 덮는 유전체층을 형성하는 단계, 절연층 상에 유전체층을 덮도록 제2전도체를 형성하는 단계로 이루어진 제2공정과; 제2공정을 적어도 2번 반복하여 수행하는 제3공정을 구비한 것이 특징이다.The present invention relates to a method for manufacturing an anti-fuse of a semiconductor device formed between a conductor and a conductor is applied when a predetermined overvoltage is applied, the method comprising: forming a first conductor on a substrate; Forming an insulating layer covering the first conductor on the substrate, patterning the insulating layer to form a contact hole exposing a predetermined portion of the first conductor, and forming a plug in contact with the first conductor in the contact hole. And forming a dielectric layer covering the plug on the insulating layer, and forming a second conductor on the insulating layer to cover the dielectric layer; And a third step of repeating the second step at least twice.

따라서, 본 발명에서는 안티퓨즈를 적층하여 형성함으로써 안티퓨즈 어레이가 차지하는 면적을 줄임에 따라 전체 칩의 면적을 줄이고 안티퓨즈의 효율성을 증가시킬 수 있는 잇점이 잇다.Therefore, in the present invention, by stacking the anti-fuse, the area occupied by the anti-fuse array has the advantage of reducing the area of the entire chip and increasing the efficiency of the anti-fuse.

Description

반도체 장치의 다층의 안티퓨즈 제조방법Manufacturing method of multi-layer antifuse of semiconductor device

본 발명은 반도체 장치의 안티퓨즈(Antifuse) 제조방법에 관한 것으로써, 특히 제조가 용이하고 사이즈 축소화가 가능하도록 적층하기에 적당한 반도체 장치의 다층의 안티퓨즈 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an antifuse of a semiconductor device, and more particularly, to a method for manufacturing a multilayer antifuse of a semiconductor device suitable for stacking so as to facilitate manufacturing and to reduce size.

반도체 장치에서 안티퓨즈는 소자 제조 공정이 완료된 후에 외부에서 메모리 소자 등의 프로그램을 할 수 있도록 동작하는 것으로써 전도체 사이에 일정전압 이상을가하면 도통되는 비정질실리콘과 같은 유전체층을 사용한 구조이며, 반도체 기억장치의 에프피지에이(FPGA; Field Programmable Gate Array)에 적용된다.Anti-fuse in semiconductor devices operates to program the memory devices from the outside after the device manufacturing process is completed, and is a structure using a dielectric layer such as amorphous silicon that is conductive when a certain voltage or more is applied between conductors. Is applied to a Field Programmable Gate Array (FPGA).

제1(a)도 내지 제1(d)도는 종래의 반도체 장치의 안티퓨즈의 제조공정도이다.1 (a) to 1 (d) are manufacturing process diagrams of an antifuse of a conventional semiconductor device.

제1(a)도를 참조하면, 기판(100) 상에 TiN/Al/TiW 합금을 순차적으로 증착한 후 패터닝하여 소정간격인 제1금속배선(101)을 형성한다.Referring to FIG. 1 (a), the TiN / Al / TiW alloy is sequentially deposited on the substrate 100, and then patterned to form a first metal wiring 101 having a predetermined interval.

상기에서 기판(100)은 반도체기판에 불순물 확산영역(도시되지 않음)이 형성되거나, 또는, 하부의 다른 배선(도시되지 않음)이 형성된 구조를 가지며, 이 확산영역 또는 하부의 다른 배선은 제1금속배선(101)과 접촉되어 전기적으로 연결된다. 이 후, 이 제1금속배선(101)은 메모리소자 등에 접촉된다.The substrate 100 has a structure in which an impurity diffusion region (not shown) is formed in the semiconductor substrate or another wiring (not shown) is formed in the lower portion of the semiconductor substrate. In contact with the metal wiring 101 is electrically connected. Thereafter, the first metal wiring 101 is in contact with a memory element or the like.

이어서, 제1금속배선(101) 상에 각각의 제1금속배선 사이의 갭(gap)을 채워 표면을 평탄화하기 위해 SOG(Spin On Glass)를 이용하는 데, 유기물질인 SOG는 하층의 무기물질을 부식시킬 우려가 있기 때문에 그 사이에 절연층을 형성한 후, 도포한다. 즉, 제1금속배선(101) 상에 갭을 얇게 채우도록 소정두께의 제1절연층(102)을 형성한다.Subsequently, SOG (Spin On Glass) is used to fill the gap between each of the first metal wires on the first metal wire 101 to planarize the surface. Since it may corrode, an insulating layer is formed in between, and it apply | coats. That is, the first insulating layer 102 having a predetermined thickness is formed on the first metal wiring 101 so as to fill the gap thinly.

다음에 제1절연층(102) 상에 제1금속배선 사이의 갭을 완전히 채우도록 SOG(Spin On Glass)(104)를 도포하여 제1금속배선(101)의 표면을 평탄화한 후, 제1절연층(102) 상에 충분한 두께로 제2절연층(106)을 형성한다.Next, the surface of the first metal wiring 101 is planarized by applying a spin on glass (SOG) 104 on the first insulating layer 102 so as to completely fill the gap between the first metal wirings. The second insulating layer 106 is formed on the insulating layer 102 to a sufficient thickness.

이 후, 제2절연층(106) 상에 제1금속배선(101)을 노출시키는 접촉홀(H,H-1)을 형성한다.Thereafter, contact holes H and H-1 exposing the first metal wiring 101 are formed on the second insulating layer 106.

제1(b)도를 참조하면, 접촉홀(H,H-1) 내에 베리어메탈층(108)을 형성한 후, 베리어메탈층(108)이 형성된 접촉홀(H)을 채우도록 스퍼터링(sputtering) 방법을 이용하여 텅스텐(W)을 증착하여 플러그(plug)(110)를 형성한다.Referring to FIG. 1 (b), after forming the barrier metal layer 108 in the contact holes H and H-1, sputtering is performed to fill the contact hole H in which the barrier metal layer 108 is formed. Tungsten (W) is deposited using the method to form a plug 110.

이 때, 베리어메탈층(108)은 하층의 제1금속배선(101)과 플러그(110) 간의 부착력이 좋지 못한 점을 보완하기 위한 것이다.At this time, the barrier metal layer 108 is to compensate for the poor adhesion between the first metal wiring 101 and the plug 110 of the lower layer.

제1(c)도를 참조하면, 제2절연층(106) 상에 비정질실리콘을 증착한 후, 포토리소그래피 방법으로 플러그(110)를 덮는 유전체층(112)을 형성한다.Referring to FIG. 1C, after depositing amorphous silicon on the second insulating layer 106, a dielectric layer 112 covering the plug 110 is formed by a photolithography method.

제1(d)도를 참조하면, 유전체층(112)이 형성된 제2절연층(106) 상에 스퍼터링 방법에 의해 제2금속층을 형성한 다음, 포토리소그래피 방법을 적용하여 유전체층(112)을 덮는 제2금속배선(114)을 형성한다.Referring to FIG. 1 (d), a second metal layer is formed on the second insulating layer 106 on which the dielectric layer 112 is formed by sputtering, and then the photolithography method is applied to cover the dielectric layer 112. The two metal wiring 114 is formed.

여기에서, 접촉홀(H,H-1)과 접촉홀에 충전된 플러그(110,111) 및 제2금속배선(114)은 제1금속배선(101)과의 전기적 연결을 위한 것이다.Here, the plugs 110 and 111 and the second metal wires 114 filled in the contact holes H and H-1 and the contact holes are for electrical connection with the first metal wires 101.

상기에서, 유전체층(112)을 비정질실리콘으로 사용할 경우, 프로그램 시, 일정이상의 과전압을 가했을 때 비정질실리콘의 실리사이드화를 위해 제1플러그(110,111) 또는 제2금속배선(114) 중 적어도 하나는 실리콘과 반응하여 실리사이드를 형성하는 금속으로 형성하여야 한다.In the above, when the dielectric layer 112 is used as amorphous silicon, at least one of the first plugs 110 and 111 or the second metal wiring 114 is formed of silicon and silicon to silicide the amorphous silicon when a predetermined overvoltage is applied during programming. It should be formed of a metal that reacts to form silicide.

상기에서 형성된 종래의 유전체층은 안티퓨즈로, 제1금속배선(101)과 제2금속배선(114)에 일정이상의 과전압을 걸어주면, 제2금속배선(114)과 접촉되는 비정질 실리콘의 네 모서리 부분이 실리사이드화된다.The conventional dielectric layer formed above is an anti-fuse, and the four corner portions of the amorphous silicon contacting the second metal wiring 114 when a predetermined voltage or more is applied to the first metal wiring 101 and the second metal wiring 114. Is silicided.

그리고 실리사이드화된 비정질실리콘인 안티퓨즈에 의해 하부의 제1금속배선(101)과 상부의 제2금속배선(114)이 전기적으로 도통하게 된다.The lower first metal interconnection 101 and the upper second metal interconnection 114 are electrically connected to each other by the anti-fuse of silicided amorphous silicon.

그러나, 종래의 안티퓨즈의 제조방법에는 하나의 안티퓨즈를 하나의 메모리 소자에 연결시키어 프로그램할 수 있도록 동작되므로, 안티퓨즈 어레이 면적이 커지며, 그에 따라 칩면적이 커지는 문제점이 발생되었다.However, in the conventional method of manufacturing antifuse, since one antifuse is operated to be connected to one memory device for programming, an antifuse array area is increased, and thus a chip area is generated.

이와 같은 문제점을 개선하기 위해 안출된 것으로써, 본 발명의 목적은 안티퓨즈의 사이즈를 축소가 가능한 반도체 장치의 안티퓨즈 제조방법을 제공하려는 것이다.In order to solve such a problem, an object of the present invention is to provide an anti-fuse manufacturing method of a semiconductor device capable of reducing the size of the anti-fuse.

상술한 목적을 달성하기 위한 본 발명의 반도체 장치의 다층의 안티퓨즈 제조방법은 전도체와 전도체 사이에 형성되어 일정 이상의 과전압이 가해지면 도통되는 반도체 장치의 안티퓨즈 제조방법에 관한 것으로, 기판 상에 제1전도체를 형성하는 공정과; 기판 상에 제1전도체를 덮는 절연층을 형성하는 단계와, 절연층을 패터닝하여 제1전도체의 소정 부분을 노출시키는 접촉홀을 형성하는 단계와, 접촉홀 내에 제1전도체와 접촉된 플러그를 형성하는 단계와, 절연층 상에 플러그를 덮는 유전체층을 형성하는 단계, 절연층 상에 유전체층을 덮도록 제2전도체를 형성하는 단계로 이루어진 제2공정과; 제2공정을 적어도 2번 반복하여 수행하는 제3공정을 구비한 것이 특징이다.The multi-layer anti-fuse manufacturing method of the semiconductor device of the present invention for achieving the above object relates to an anti-fuse manufacturing method of a semiconductor device is formed between the conductor and the conductor and is conductive when a certain voltage or more is applied. Forming a conductor; Forming an insulating layer covering the first conductor on the substrate, patterning the insulating layer to form a contact hole exposing a predetermined portion of the first conductor, and forming a plug in contact with the first conductor in the contact hole. And forming a dielectric layer covering the plug on the insulating layer, and forming a second conductor on the insulating layer to cover the dielectric layer; And a third step of repeating the second step at least twice.

제1(a)도 내지 제1(d)도는 종래기술에 따른 반도체장치의 안티퓨즈 제조공정을 도시한 단면도.1 (a) to 1 (d) are cross-sectional views showing an antifuse manufacturing process of a semiconductor device according to the prior art.

제2(a)도 내지 제2(e)도는 본 발명에 따른 반도체 장치의 안티퓨즈 제조공정을 도시한 단면도.2 (a) to 2 (e) are cross-sectional views showing an antifuse manufacturing process of a semiconductor device according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

100,143,200,214,222 : 금속배선 102,202 : 제1절연층100,143,200,214,222: Metal wiring 102,202: First insulating layer

104,204 : SOG 106,206 : 제2절연층104,204: SOG 106,206: second insulating layer

108,208,216 : 베리어메탈층 110,111,210,211 : 플러그108,208,216: Barrier metal layer 110,111,210,211: Plug

112,212,220 : 유전체층112,212,220: dielectric layer

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

제2(a)도 내지 제2(e)도는 본 발명에 따른 다층의 안티퓨즈 제조공정도이다.2 (a) to 2 (e) is a multi-layer anti-fuse manufacturing process according to the present invention.

제2(a)도를 참조하면, 기판(200) 상에 TiN/Al/TiW 합금을 순차적으로 증착한 후 패터닝하여 소정간격인 제1금속배선(201)을 형성한다.Referring to FIG. 2 (a), the TiN / Al / TiW alloy is sequentially deposited on the substrate 200 and then patterned to form a first metal wiring 201 at predetermined intervals.

상기에서 기판(200)은 반도체기판에 불순물 확산영역(도시되지 않음)이 형성되거나, 또는, 하부의 다른 배선(도시되지 않음)이 형성된 구조를 가지며, 이 확산영역 또는 하부의 다른 배선은 제1금속배선(201)과 접촉되어 전기적으로 연결된다. 이 후, 이 제1금속배선(201)은 메모리소자 등에 접촉된다.The substrate 200 has a structure in which an impurity diffusion region (not shown) is formed in the semiconductor substrate or another wiring (not shown) is formed in the lower portion of the semiconductor substrate. In contact with the metal wiring 201 and electrically connected. Thereafter, the first metal wiring 201 is in contact with a memory element or the like.

다음에, 제1금속배선(201) 상에 제1금속배선 사이에 형성된 좁은 폭의 갭을 채워 표면을 평탄화하기 위해서는 SOG를 이용하는 데, 유기물질인 SOG는 하층의 무기물질을 부식시킬 수 있으므로, 하층을 노출시키는 갭 사이에 절연층을 형성한 후, SOG를 증착하여 제1금속배선 사이의 갭을 채워 표면을 평탄화한다.Next, SOG is used to planarize the surface by filling a narrow gap formed between the first metal interconnections on the first metal interconnection 201, and SOG, which is an organic material, may corrode the inorganic material of the lower layer. After forming an insulating layer between the gaps exposing the lower layer, SOG is deposited to fill the gap between the first metal wirings to planarize the surface.

즉, 제1금속배선(201) 상에 갭을 얇게 채우도록 제1절연층(202)을 형성한다. 다음에, 제2절연층(202) 상에 갭을 완전히 채우도록 SOG를 도포한 후, 표면을 평탄화한다.That is, the first insulating layer 202 is formed on the first metal wiring 201 so as to fill the gap thinly. Next, after SOG is applied to completely fill the gap on the second insulating layer 202, the surface is planarized.

이어서, 제1절연층(202) 상에 충분한 두께의 제2절연층(206)을 형성한 후, 제1금속배선(201)을 노출시키는 제1접촉홀(H-2,H-3)을 형성한다.Subsequently, after forming the second insulating layer 206 having a sufficient thickness on the first insulating layer 202, the first contact holes H-2 and H-3 exposing the first metal wiring 201 are formed. Form.

제2(b)도를 참조하면, 제2절연층(206) 상에 제1접촉홀(H-2,H-3)을 얇게 채우도록 제1베리어메탈층(208)을 형성한다. 이 후, 제1베리어메탈층(208) 상에 제1접촉홀(H-2,H-3)을 채우도록 텅스텐을 스퍼터링 방법으로 증착하여 상기 제1접촉홀(H-2,H-3)에 제1베리어메탈층(208)과 텅스텐의 적층층이 충전되도록 한다. 그런 후, 제1접촉홀(H-2,H-3) 외 부위의 제1베리어메탈층(208)과 텅스텐을 제거하여 제1플러그(210,211)를 형성한다.Referring to FIG. 2B, a first barrier metal layer 208 is formed on the second insulating layer 206 so as to fill the first contact holes H-2 and H-3 thinly. Thereafter, tungsten is deposited by sputtering to fill the first contact holes H-2 and H-3 on the first barrier metal layer 208, thereby forming the first contact holes H-2 and H-3. The first barrier metal layer 208 and the tungsten layer are filled. Thereafter, the first barrier metal layer 208 and the tungsten outside the first contact holes H-2 and H-3 are removed to form first plugs 210 and 211.

다음에, 제1플러그(210,211)이 형성된 제2절연층(206) 상에 비정질실리콘을 증착한 후, 제1플러그(210)를 덮도록 포토리소그래피 방법으로 제1유전체층(212)을 형성한다.Next, after the amorphous silicon is deposited on the second insulating layer 206 on which the first plugs 210 and 211 are formed, the first dielectric layer 212 is formed by photolithography to cover the first plug 210.

이어서, 노출된 제2절연층(206) 상에 제2금속층을 형성한 후, 포토리소그래피방법을 적용하여 제1유전체층(212) 및 플러그(211)를 덮는 제2금속배선(214)을 형성한다. 여기에서, 제1접촉홀(H-2,H-3)과 제1접촉홀에 충전된 제1플러그(210) 및 제2금속배선(214)은 제1금속배선(201)과의 전기적 연결을 위한 것이다.Subsequently, after the second metal layer is formed on the exposed second insulating layer 206, a photolithography method is applied to form a second metal wiring 214 covering the first dielectric layer 212 and the plug 211. . The first plug 210 and the second metal wire 214 filled in the first contact holes H-2 and H-3 and the first contact hole are electrically connected to the first metal wire 201. It is for.

상기에서, 제1유전체층(212)을 비정질실리콘으로 사용할 경우, 일정 이상의 과전압을 가했을 때 비정질실리콘을 실리사이드화시키기 위해 제1플러그(210) 또는 제2금속배선(214) 중 적어도 하나는 실리콘과 반응하여 실리사이드를 형성하는 금속으로 형성하여야 한다.In the above, when the first dielectric layer 212 is used as amorphous silicon, at least one of the first plug 210 or the second metal wiring 214 reacts with silicon in order to silicide the amorphous silicon when a predetermined overvoltage is applied. To form a silicide.

이 유전체층(212)은 이 후에 과전압을 걸어주게 되면 전기적으로 도통하게 되는 안티퓨즈가 된다.The dielectric layer 212 becomes an antifuse which is electrically conductive when an overvoltage is applied thereafter.

제2(c)도를 참조하면, 제2금속배선(214) 상에 제1접촉홀(H-3)과 대응되는 제2접촉홀(H-4)을 형성한다.Referring to FIG. 2C, a second contact hole H-4 corresponding to the first contact hole H-3 is formed on the second metal wire 214.

제2(d)도를 참조하면, 제2접촉홀(H-4) 내에 얇게 채우도록 제2베리어메탈층(216)을 형성한다. 그리고 제2베리어메탈층(216) 상에 제2접촉홀(H-4)을 완전히 채우도록 스퍼터링 방법을 이용하여 텅스텐을 증착하여 상기 제2접촉홀(H-4)에 제2베리어메탈층(216)과 텅스텐의 적층층이 충전되도록 한다. 그런 후, 제2접촉홀(H-4)외 부위의 제2베리어메탈층(216)과 텅스텐을 제거하여 제2플러그(218)를 형성한다.Referring to FIG. 2 (d), the second barrier metal layer 216 is formed to be thinly filled in the second contact hole H-4. In addition, a second barrier metal layer (2) is formed in the second contact hole (H-4) by depositing tungsten using a sputtering method to completely fill the second contact hole (H-4) on the second barrier metal layer (216). 216) and the tungsten layer of tungsten is filled. Thereafter, the second barrier metal layer 216 and the tungsten of the portion outside the second contact hole H-4 are removed to form a second plug 218.

제2(e)도를 참조하면, 제2플러그(218)가 형성된 제2금속배선(214) 상에 비정질실리콘을 증착한 후, 제2플러그(218)을 덮도록 포토리소그래피 방법을 적용하여 제2유전체층(220)을 형성한다.Referring to FIG. 2 (e), after depositing amorphous silicon on the second metal wiring 214 on which the second plug 218 is formed, the photolithography method is applied to cover the second plug 218. The second dielectric layer 220 is formed.

다음에, 제2금속배선(214) 상에 제2금속층을 형성한 후, 제2유전체층(220)을 덮도록 포토리소그래피 방법을 적용하여 제3금속배선(222)을 형성한다.Next, after the second metal layer is formed on the second metal wire 214, the third metal wire 222 is formed by applying a photolithography method to cover the second dielectric layer 220.

여기에서, 제2접촉홀(H-4)과 제2접촉홀에 충전된 제2플러그(218) 및 제3금속배선(222)은 제2금속배선(214)과의 전기적 연결을 위한 것이다.Here, the second plug 218 and the third metal wire 222 filled in the second contact hole H-4 and the second contact hole are for electrical connection with the second metal wire 214.

상기에서, 제2유전체층(220)을 비정질실리콘으로 사용할 경우, 제1유전체층(212)과 마찬가지로, 프로그램시 전압을 가했을 때 비정질실리콘의 실리사이드화를 위해 제2플러그(218) 또는 제3금속배선(222) 중 적어도 하나는 실리콘과 반응하여 실리사이드를 형성하는 금속으로 형성하여야 한다.As described above, when the second dielectric layer 220 is used as amorphous silicon, the second plug 218 or the third metal wiring (silicon) may be used to silicide the amorphous silicon when a voltage is applied during programming, similarly to the first dielectric layer 212. At least one of 222 must be formed of a metal that reacts with silicon to form silicide.

이 제2유전체층(220)에 일정 이상의 과전압을 걸어주게 되면 제2금속배선(214)과 제3금속배선(222)을 전기적으로 도통시키는 역할을 하는 안티퓨즈가 된다.When an overvoltage is applied to the second dielectric layer 220 by a predetermined voltage or more, the second fuse 214 and the third metal wire 222 become antifuses.

본 발명의 반도체 장치의 안티퓨즈의 동작은 종래와 같게, 외부에서 메모리소자등의 프로그램을 위해 전압을 제1금속배선(201)와 제2금속배선(214)에 가하면 제1유전체층(212)인 비정질실리콘이 실리사이드화되어 도통되게 된다.The antifuse operation of the semiconductor device of the present invention is the same as in the prior art. When the voltage is applied to the first metal wiring 201 and the second metal wiring 214 externally for programming of a memory device or the like, Amorphous silicon becomes silicided and becomes conductive.

그리고 전기적으로 도통된 제2금속배선(214)은 제2유전체층(220)인 비정질실리콘이 실리사이드화되어 제3금속배선(222)과 도통하게 된다.In the electrically conductive second metal interconnection 214, the amorphous silicon, which is the second dielectric layer 220, is silicided to conduct the third metal interconnection 222.

따라서, 제1유전체층(212)과 제2유전체층(220)을 통하여 제1금속배선(201) 및 제2금속배선(214) 및 제3금속배선(222)이 서로 전기적으로 도통하게 된다.Therefore, the first metal wiring 201, the second metal wiring 214, and the third metal wiring 222 are electrically connected to each other through the first dielectric layer 212 and the second dielectric layer 220.

상술한 바와 같이, 본 발명의 반도체 장치의 다층의 안티퓨즈 제조방법에서는 다층의 안티퓨즈를 적층하여 형성함에 따라, 안티퓨즈 어레이가 차지하는 면적을 줄임으로써 전체 칩의 면적을 줄이고 안티퓨즈의 효율성을 증가시킬 수 있는 잇점이 있다.As described above, in the method of manufacturing a multi-layer antifuse of the semiconductor device of the present invention, by stacking the multi-layered antifuse, the area of the antifuse array is reduced, thereby reducing the area of the entire chip and increasing the efficiency of the antifuse. There is an advantage to this.

Claims (4)

전도체와 전도체 사이에 형성되어 일정 이상의 과전압이 가해지면 도통되는 반도체 장치의 안티퓨즈 제조방법에 관한 것으로, 기판 상에 제1전도체를 형성하는 공정과; 상기 기판 상에 제1전도체를 덮는 절연층을 형성하는 단계와, 상기 절연층을 패터닝하여 상기 제1전도체의 소정 부분을 노출시키는 접촉홀을 형성하는 단계와, 상기 접촉홀 내에 제1전도체와 접촉된 플러그를 형성하는 단계와, 상기 절연층 상에 플러그를 덮는 유전체층을 형성하는 단계, 상기 절연층 상에 상기 유전체층을 덮도록 제2전도체를 형성하는 단계로 이루어진 제2공정과; 상기 제2공정을 적어도 2번 반복하여 수행하는 제3공정을 구비하는 반도체장치의 다층의 안티퓨즈 제조방법.A method for manufacturing an anti-fuse of a semiconductor device is formed between the conductor and the conductor is applied when a predetermined overvoltage is applied, the method comprising: forming a first conductor on a substrate; Forming an insulating layer covering the first conductor on the substrate, patterning the insulating layer to form a contact hole exposing a predetermined portion of the first conductor, and contacting the first conductor in the contact hole. Forming a plug, forming a dielectric layer covering the plug on the insulating layer, and forming a second conductor on the insulating layer to cover the dielectric layer; And a third step of repeating the second step at least twice. 제1항에 있어서, 상기 유전체층을 비정질실리콘으로 형성하는 것이 특징인 반도체 장치의 다층의 안티퓨즈 제조방법.The method for manufacturing a multilayer antifuse of a semiconductor device according to claim 1, wherein the dielectric layer is formed of amorphous silicon. 제1항에 있어서, 상기 플러그를 상기 베리어메탈층과 텅스텐의 적층된 구조로 형성하는 것이 특징인 반도체 장치의 다층의 안티퓨즈의 제조방법.The method of claim 1, wherein the plug is formed in a stacked structure of the barrier metal layer and tungsten. 제1항 내지 제3항 중 어느 한 항에 있어서, 상기 플러그의 형성은, 상기 접촉홀 부위를 포함한 절연층 상에 베리어메탈층과 텅스텐을 순차로 형성하여 상기 접촉홀에 상기 베리어메탈층과 텅스텐의 적층층이 충전되도록 하고, 상기 접촉홀 외 부위의 베리어메탈층과 텅스텐을 제거하여 형성하는 것이 특징인 반도체 장치의 다층의 안티퓨즈 제조방법.The method according to any one of claims 1 to 3, wherein the plug is formed by sequentially forming a barrier metal layer and tungsten on the insulating layer including the contact hole portion, and thereby forming the barrier metal layer and tungsten in the contact hole. Method of manufacturing a multi-layer anti-fuse of the semiconductor device characterized in that the laminated layer of the filling and the barrier metal layer and the tungsten removed from the outside of the contact hole.
KR1019970041490A 1997-08-27 1997-08-27 Method for manufacturing multi-layer anti-fuse of semiconductor device KR100246191B1 (en)

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