KR100227071B1 - Method of forming metal wiring using antifuse - Google Patents

Method of forming metal wiring using antifuse Download PDF

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Publication number
KR100227071B1
KR100227071B1 KR1019970016124A KR19970016124A KR100227071B1 KR 100227071 B1 KR100227071 B1 KR 100227071B1 KR 1019970016124 A KR1019970016124 A KR 1019970016124A KR 19970016124 A KR19970016124 A KR 19970016124A KR 100227071 B1 KR100227071 B1 KR 100227071B1
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South Korea
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wiring
forming
insulating film
antifuse
interlayer insulating
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KR1019970016124A
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Korean (ko)
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KR19980078562A (en
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김기용
정영수
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구본준
엘지반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2

Abstract

본 발명은 안티퓨즈를 이용한 배선방법에 관한 것으로서 기판 상에 제 1 배선을 형성하는 공정과, 상기 제 1 배선 상에 제 1 안티퓨즈를 형성하는 공정과, 상기 기판상에 상기 제 1 배선 및 제 1 안티퓨즈를 덮도록 제 1 층간절연막을 형성하고 상기 제 1 층간절연막에 상기 제 1 안티퓨즈를 노출시키는 제 1 접촉창을 형성하는 갖는 제 1 층간절연막을 형성하는 공정과, 상기 제 1 접촉창을 채우는 제 1 플러그를 형성하고 상기 제 1 층간절연막 상에 상기 제 1 플러그와 접촉되도록 제 2 배선을 형성하는 공정과, 상기 제 1 층간절연막 상에 상기 제 2 배선을 덮도록 제 2 층간절연막을 형성하고 상기 제 2 층간절연막에 상기 제 2 배선을 노출시키는 제 2 접촉창을 형성하는 공정과, 상기 제 2 접촉창을 채우는 제 2 플러그를 형성하고 상기 제 2 층간절연막 상에 상기 제 2 플러그와 접촉되도록 제 2 안티퓨즈를 형성하는 공정과, 상기 제 2 층간절연막 상에 상기 제 2 안티퓨즈와 접촉되는 제 3 배선을 형성하는 공정을 구비한다. 따라서, 프로그램될 배선과 프로그램되지 않을 배선을 적층시켜 칩의 크기를 감소시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring method using an antifuse, comprising the steps of forming a first wiring on a substrate, forming a first antifuse on the first wiring, and forming the first wiring and the first wiring on the substrate. Forming a first interlayer insulating film to cover the first antifuse, and forming a first interlayer insulating film having a first contact window for exposing the first antifuse to the first interlayer insulating film; and the first contact window Forming a first plug filling the gap, and forming a second wiring on the first interlayer insulating film to be in contact with the first plug; and forming a second interlayer insulating film on the first interlayer insulating film to cover the second wiring. And forming a second contact window exposing the second wiring on the second interlayer insulating film, and forming a second plug filling the second contact window, and forming the second contact window on the second interlayer insulating film. Forming a second antifuse to be in contact with the second plug; and forming a third wiring contacting the second antifuse on the second interlayer insulating film. Therefore, the size of the chip can be reduced by stacking the wiring to be programmed and the wiring not to be programmed.

Description

안티퓨즈를 이용한 배선방법.Wiring method using antifuse.

본 발명은 안티퓨즈를 이용한 배선방법에 관한 것으로서, 특히, 다수 개의 배선들을 적층시켜 선택적으로 전기적으로 연결시켜 프로그램하여 집적도를 향상시킬 수 있는 안티퓨즈를 이용한 배선방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring method using antifuse, and more particularly, to a wiring method using antifuse that can improve the degree of integration by stacking a plurality of wires and electrically connecting them.

도 1a 내지 d는 종래 기술에 따른 안티퓨즈를 이용한 배선방법을 도시하는 공정도이다.1a to d are process diagrams illustrating a wiring method using an antifuse according to the prior art.

도 1a를 참조하면, 기판(11) 상에 TiW 또는 Ti 계열의 화합물 등의 도전성 금속을 증착한 후 포토리쏘그래피(photolithography) 방법으로 패터닝하여 제 1 배선(13)(14)을 형성한다. 상기에서, 기판(11)은 절연막이 형성된 반도체기판일 수도 있다.Referring to FIG. 1A, first wirings 13 and 14 are formed by depositing a conductive metal such as TiW or a Ti-based compound on the substrate 11 and patterning the same by photolithography. In the above, the substrate 11 may be a semiconductor substrate on which an insulating film is formed.

도 1b를 참조하면, 기판(11) 상에 제 1 배선(13)(14)이 덮혀지도록 산화실리콘을 화학기상증착(Chemical Vapor Deposition : 이하, CVD라 칭함) 방법으로 증착하여 층간절연막(15)을 형성한다. 그리고, 층간절연막(15)을 제 1 배선(13)(14)이 노출되도록 패터닝하여 접촉창(17)을 형성한다.Referring to FIG. 1B, the silicon oxide is deposited by chemical vapor deposition (hereinafter, referred to as CVD) to cover the first wirings 13 and 14 on the substrate 11. To form. The interlayer insulating film 15 is patterned so that the first wirings 13 and 14 are exposed to form the contact window 17.

도 1c를 참조하면, 층간절연막(15) 상에 접촉창(17)을 통해 제 1 및 제 2 배선(13)(14)과 접촉되게 불순물이 도핑되지 않은 비정질실리콘을 CVD 방법으로 증착한다. 그리고, 비정질실리콘을 제 1 및 제 2 배선(13)(14)과 접촉되는 부분을 포함하여 접촉창(17)과 대응하는 부분이 잔류하도록 패터닝하여 안티퓨즈(antifuse)(19)(20)을 형성한다.Referring to FIG. 1C, amorphous silicon, which is not doped with impurities, is deposited on the interlayer insulating layer 15 to contact the first and second wires 13 and 14 through the contact window 17. Then, the amorphous silicon is patterned such that portions corresponding to the contact window 17 remain, including portions in contact with the first and second wirings 13 and 14 to form the antifuses 19 and 20. Form.

도 1d를 참조하면, 층간절연막(15)과 안티퓨즈(19)(20) 상에 접촉창(17)이 채워지도록 도전성 금속을 CVD 방법 등으로 증착한 후 패터닝하여 제 2 배선(22)(23)을 형성한다. 상기에서 제 2 배선(22)(23)을 제 1 배선(13)(14)과 동일한 물질로 접촉창(17)을 통해 안티퓨즈(19)(20)와 접촉되도록 형성한다.Referring to FIG. 1D, a conductive metal is deposited on the interlayer insulating film 15 and the antifuse 19, 20 by using a CVD method or the like, and then patterned to form the second wiring 22 (23). ). The second wirings 22 and 23 are formed to be in contact with the antifuse 19 and 20 through the contact window 17 using the same material as the first wirings 13 and 14.

상술한 바와 같이 형성된 서로 대응하는 제 1 배선(13)(14)과 제 2 배선(22)(23)은 안티퓨즈(19)(20)에 의해 전기적으로 분리된다. 그러므로, 패드(도시되지 않음)를 통해 제 2 배선(22)(23) 중 하나에 전압을 인가하고 제 1 배선(13)(14) 중 대응하는 것을 접지시키면 안티퓨즈(19)(20) 중 사이에 형성된 것이 실리사이드(silicide)로 변하게되어 도전체가 된다. 즉, 제 2 배선(22)에 프로그램 전압(programming voltage) 이상의 전압을 인가하고 제 1 배선(13)을 접지시키면 안티퓨즈(19)를 이루는 불순물이 도핑도지 않은 비정질실리콘이 제 1 및 제 2 배선(13)(22)을 이루는 Ti와 반응하여 도전체인 실리사이드로 변하게 된다. 그러므로, 제 1 및 제 2 배선(13)(22)은 선택적으로 전기적으로 연결된다.The first wirings 13 and 14 and the second wirings 22 and 23 corresponding to each other formed as described above are electrically separated by the antifuse 19 and 20. Therefore, if a voltage is applied to one of the second wirings 22 and 23 through a pad (not shown) and the corresponding one of the first wirings 13 and 14 is grounded, the antifuse 19 and 20 may be grounded. What is formed in between turns into silicide and becomes a conductor. That is, when a voltage equal to or greater than a programming voltage is applied to the second wiring 22 and the first wiring 13 is grounded, amorphous silicon that is not doped with impurities forming the antifuse 19 is formed in the first and second wirings. It reacts with Ti which forms (13) and (22), and changes into the silicide which is a conductor. Therefore, the first and second wirings 13 and 22 are selectively electrically connected.

그러나, 종래 기술에 따른 안티퓨즈를 이용한 배선방법은 프로그램될 배선과 프로그램되지 않을 배선이 동일한 수평면 상에 다수 개 형성되므로 칩의 크기가 증가되는 문제점이 있었다.However, the wiring method using an antifuse according to the related art has a problem in that the size of the chip is increased because a plurality of wirings to be programmed and wirings to be programmed are formed on the same horizontal plane.

따라서, 본 발명의 목적은 프로그램될 배선과 프로그램되지 않을 배선을 적층시켜 칩의 크기를 감소시킬 수 있는 안티퓨즈를 이용한 배선방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a wiring method using antifuse which can reduce the size of a chip by stacking wiring to be programmed and wiring not to be programmed.

상기 목적을 달성하기 위한 본 발명에 따른 안티퓨즈를 이용한 배선방법은 기판 상에 제 1 배선을 형성하는 공정과, 상기 제 1 배선 상에 제 1 안티퓨즈를 형성하는 공정과, 상기 기판 상에 상기 제 1 배선 및 제 1 안티퓨즈를 덮도록 제 1 층간절연막을 형성하고 상기 제 1 층간절연막에 상기 제 1 안티퓨즈를 노출시키는 제 1 접촉창을 형성하는 갖는 제 1 층간절연막을 형성하는 공정과, 상기 제 1 접촉창을 채우는 제 1 플러그를 형성하고 상기 제 1 층간절연막 상에 상기 제 1 플러그와 접촉되도록 제 2 배선을 형성하는 공정과, 상기 제 1 층간절연막 상에 상기 제 2 배선을 덮도록 제 2 층간절연막을 형성하고 상기 제 2 층간절연막에 상기 제 2 배선을 노출시키는 제 2 접촉창을 형성하는 공정과, 상기 제 2 접촉창을 채우는 제 2 플러그를 형성하고 상기 제 2 층간절연막 상에 상기 제 2 플러그와 접촉되도록 제 2 안티퓨즈를 형성하는 공정과, 상기 제 2 층간절연막 상에 상기 제 2 안티퓨즈와 접촉되는 제 3 배선을 형성하는 공정을 구비한다.A wiring method using an antifuse according to the present invention for achieving the above object comprises the steps of forming a first wiring on a substrate, forming a first antifuse on the first wiring, and Forming a first interlayer insulating film to cover the first wiring and the first antifuse, and forming a first interlayer insulating film having a first contact window exposing the first antifuse on the first interlayer insulating film; Forming a first plug filling the first contact window and forming a second wiring on the first interlayer insulating film so as to contact the first plug; and covering the second wiring on the first interlayer insulating film. Forming a second contact window for forming a second interlayer insulating film and exposing the second wiring to the second interlayer insulating film, forming a second plug filling the second contact window, and forming the second layer A step of forming a second anti-fuse in contact with said second plug in the insulating film, and a step of forming a third wiring that is in contact with the second anti-fuse on the second interlayer insulating film.

이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 d는 종래 기술에 따른 안티퓨즈를 이용한 배선방법을 도시하는 공정도.1a to d are process drawings showing a wiring method using an antifuse according to the prior art.

도 2a 내지 e는 본 발명에 따른 안티퓨즈를 이용한 배선방법을 도시하는 공정도.2a to e is a process chart showing a wiring method using an anti-fuse according to the present invention.

* 도면의 주요 부분에 대한 부호의 간단한 설명* Brief description of symbols for the main parts of the drawing

31 : 기판 33, 34 : 제 1 배선31: substrate 33, 34: first wiring

36 : 평탄화막 38 : 제 1 안티퓨즈36: planarization film 38: first anti-fuse

40 : 제 1 층간절연막 42 : 제 1 접촉창40: first interlayer insulating film 42: first contact window

44 : 제 1 플러그 46 : 제 2 배선44: first plug 46: second wiring

48 : 제 2 층간절연막 50 : 제 2 접촉창48: second interlayer insulating film 50: second contact window

52 : 제 2 플러그 54 : 제 2 안티퓨즈52: second plug 54: second anti-fuse

56 : 제 3 배선56: third wiring

도 2a 내지 e는 본 발명에 따른 안티퓨즈를 이용한 배선방법을 도시하는 공정도이다.2A to 2E are process diagrams illustrating a wiring method using antifuse according to the present invention.

도 2a를 참조하면, 기판(31) 상에 TiW 또는 Ti 계열의 화합물 등의 도전성 금속을 증착한 후 포토리쏘그래피 방법으로 패터닝하여 제 1 배선(33)(34)을 형성한다. 상기에서, 기판(11)은 절연막이 형성된 반도체기판일 수도 있다. 상기에서 제 1 배선(33)(34)을 2개로 형성하였으나 다수 개로 형성할 수도 있다.Referring to FIG. 2A, the first wirings 33 and 34 are formed by depositing a conductive metal such as TiW or a Ti-based compound on the substrate 31 and patterning the photolithography method. In the above, the substrate 11 may be a semiconductor substrate on which an insulating film is formed. In the above description, two first wirings 33 and 34 are formed, but a plurality of first wirings 33 and 34 may be formed.

도 2b를 참조하면, 기판(31) 상에 제 1 배선(33)(34)이 덮혀지도록 CVD방법으로 산화실리콘을 증착한다. 그리고, 산화실리콘을 제 1 배선(33)(34)의 표면이 노출되도록 에치백하여 제 1 배선(33)(34) 사이에 평탄화막(36)을 형성한다.Referring to FIG. 2B, silicon oxide is deposited by the CVD method so that the first wirings 33 and 34 are covered on the substrate 31. The silicon oxide is etched back to expose the surfaces of the first wirings 33 and 34 to form a planarization film 36 between the first wirings 33 and 34.

도 2c를 참조하면, 기판(31) 상에 제 1 배선(33)(34) 및 평탄화막(36)이 덮히도록 불순물이 도핑되지 않은 비정질실리콘을 CVD 방법으로 증착한다. 그리고, 비정질실리콘을 제 1 및 제 2 배선(33)(34)의 표면에 잔류하도록 패터닝하여 제 1 안티퓨즈(38)를 형성한다.Referring to FIG. 2C, amorphous silicon, which is not doped with impurities, is deposited by a CVD method to cover the first wirings 33 and 34 and the planarization layer 36 on the substrate 31. The amorphous silicon is then patterned to remain on the surfaces of the first and second wirings 33 and 34 to form the first antifuse 38.

그리고, 상술한 구조의 전 표면 상에 산화실리콘을 CVD 방법으로 증착하여 제 1 층간절연막(40)을 형성한다. 그리고, 제 1 층간절연막(40)을 제 1 안티퓨즈(38)가 노출되도록 패터닝하여 제 1 접촉창(42)을 형성한다.Then, silicon oxide is deposited on the entire surface of the structure described above by CVD to form a first interlayer insulating film 40. The first interlayer insulating layer 40 is patterned to expose the first antifuse 38 to form a first contact window 42.

도 2d를 참조하면, 제 1 접촉창(42) 내에 제 1 안티퓨즈(38)와 접촉되는 제 1 플러그(44)를 형성한다. 상기에서, 제 1 플러그(44)를 제 1 층간절연막(40) 상에 제 1 접촉창(42)을 채워 제 1 안티퓨즈(36)(37)과 접촉되도록 텡스텐(W) 또는 티타늄(Ti) 등의 도전성 금속을 증착하고 제 1 층간절연막(40)이 노출되어 제 1 접촉창(42)에만 잔류하도록 에치백하여 형성한다.Referring to FIG. 2D, a first plug 44 in contact with the first antifuse 38 is formed in the first contact window 42. In the above, the first plug 44 fills the first contact window 42 on the first interlayer insulating film 40 so that the first plug 44 contacts the first antifuse 36 or 37 so that the first plug 44 or the titanium (Ti) can be contacted. And a conductive metal such as e) and are etched back so that the first interlayer insulating film 40 is exposed and remains only in the first contact window 42.

그리고, 제 1 층간절연막(40) 상에 제 1 플러그(44)와 접촉되는 제 2 배선(46)을 형성한다. 상기에서, 제 2 배선(46)은 제 1 층간절연막(40) 상에 제 1 배선(33)(34)과 동일한 Tiw 또는 Ti 계열의 화합물 등의 도전성 금속을 증착한 후 제 1 플러그(44)와 접촉되게 제 1 접촉창(42)과 대응하는 부분만 남도록 포토리쏘그래피 방법으로 패터닝하므로써 형성된다.A second wiring 46 is formed on the first interlayer insulating film 40 to be in contact with the first plug 44. In the above description, the second wiring 46 is formed on the first interlayer insulating film 40 by depositing a conductive metal such as Tiw or a Ti-based compound, which is the same as the first wiring 33, 34. And by patterning by photolithography such that only the portion corresponding to the first contact window 42 remains in contact with the first contact window 42.

그리고, 제 1 층간절연막(40) 상에 산화실리콘을 CVD 방법으로 제2배선(46)을 덮도록 증착하여 제2층간절연막(48)을 형성한다. 그리고, 제 2 층간절연막(48)을 제 2 배선(46)이 노출되도록 패터닝하여 제 2 접촉창(50)을 형성한다.Then, silicon oxide is deposited on the first interlayer insulating film 40 to cover the second wiring 46 by CVD to form a second interlayer insulating film 48. The second interlayer insulating film 48 is patterned to expose the second wiring 46 to form a second contact window 50.

도 2e를 참조하면, 제 2 접촉창(50) 내에 제 2 배선(46)와 접촉되는 제 2 플러그(52)를 형성한다. 상기에서, 제 2 플러그(52)는 제 1 플러그(44)와 동일한 방법으로 제 2 층간절연막(48) 상에 제 2 접촉창(50)을 채워 제 2 배선(46)과 접촉되도록 텡스텐(W) 또는 티타늄(Ti) 등의 도전성 금속을 증착하고 제 2 층간절연막(48)이 노출되어 제 2 접촉창(50)에만 잔류하도록 에치백하므로써 형성된다.Referring to FIG. 2E, a second plug 52 in contact with the second wire 46 is formed in the second contact window 50. In the above, the second plug 52 fills the second contact window 50 on the second interlayer insulating film 48 in the same manner as the first plug 44 so as to be in contact with the second wiring 46. It is formed by depositing a conductive metal such as W) or titanium (Ti) and etching back so that the second interlayer insulating film 48 is exposed and remains only in the second contact window 50.

그리고, 제 2 층간절연막(48) 상에 불순물이 도핑되지 않은 비정질실리콘을 증착한 후 제 2 플러그(52)와 접촉되도록 제 2 접촉창(50)과 대응하는 부분만 잔류하도록 패터닝하여 제 2 안티퓨즈(54)를 형성한다. 그 다음, 제 2 층간절연막(48) 상에 제 2 안티퓨즈(54)와 접촉되도록 제 3 배선(56)을 형성한다. 상기에서, 제 3 배선(56)은 제 1 배선(33)(34) 및 제 2 배선(46)과 동일한 물질을 증착하고 제 2 안티퓨즈(54)와 접촉되게 패터닝하므로써 형성된다.After depositing amorphous silicon that is not doped with impurities on the second interlayer insulating film 48, the second anti-pattern is patterned so that only the portion corresponding to the second contact window 50 remains to be in contact with the second plug 52. The fuse 54 is formed. Next, a third wiring 56 is formed on the second interlayer insulating film 48 to be in contact with the second antifuse 54. In the above, the third wiring 56 is formed by depositing the same material as the first wiring 33, 34 and the second wiring 46 and patterning it in contact with the second antifuse 54.

상기에서, 제 3 배선(56)을 제 1 배선(33)(34)과 동일하게 패터닝하여 2개 이상 다수 개로 분리할 수도 있다.In the above, the third wiring 56 may be patterned in the same manner as the first wiring 33 and the 34 to be separated into two or more.

상술한 안티퓨즈를 이용한 배선방법에서 제 2 배선(46)은 패드(도시되지 않음)에 연결되는 것으로 제 1 배선(33)(34)과 제 1 안티퓨즈(38)에 의해, 그리고, 제 3 배선(56)과 제 2 안티퓨즈(54)에 의해 전기적으로 분리된다.In the wiring method using the antifuse described above, the second wiring 46 is connected to a pad (not shown) by the first wirings 33 and 34 and the first antifuse 38, and the third wiring. It is electrically separated by the wiring 56 and the second antifuse 54.

그러므로, 패드를 통해 제 2 배선(46)에 전압을 인가하고 제 1 배선(33)(34) 및 제 3 배선(56) 중 어느 하나를 접지시켜 제 1 안티퓨즈(38) 또는 제 2 안티퓨즈(54)를 실리사이드로 변화시킨다. 즉, 제 2 배선(46)에 7∼12V 정도의 프로그램전압을 인가하고 제 1 배선(33)을 접지시키면 제 1 안티퓨즈(38)가 제 1 배선(33) 및 제 1 플러그(44)와 반응하여 실리사이드로 변화시켜 도전체로 만든다. 이 때, 제 1 안티퓨즈(38)는 제 1 배선(33)과 제 1 플러그(44)가 중첩되는 부분만 실리사이드로 변화되어 도전체가 되며 제 1 배선(34)과 플러그(44)가 중첩되는 부분은 변화되지 않는다. 따라서, 제 2 배선(46)과 제 1 배선(33)은 전기적으로 연결되어 프로그램된다.Therefore, the first antifuse 38 or the second antifuse is applied by applying a voltage to the second wiring 46 through the pad and grounding either one of the first wiring 33, 34 and the third wiring 56. Change 54 to silicide. That is, when a program voltage of about 7 to 12V is applied to the second wiring 46 and the first wiring 33 is grounded, the first antifuse 38 is connected to the first wiring 33 and the first plug 44. It reacts and changes to silicide into a conductor. At this time, the first anti-fuse 38 is changed to silicide only in a portion where the first wiring 33 and the first plug 44 overlap with each other to become a conductor, and the first wiring 34 and the plug 44 overlap each other. The part does not change. Thus, the second wiring 46 and the first wiring 33 are electrically connected and programmed.

또한, 제 1 배선(34) 및 제 3 배선(56)도 제 1 배선(33)과 같이 선택적으로 제 2 배선(44)과 전기적으로 연결할 수도 있다.In addition, the first wiring 34 and the third wiring 56 may also be electrically connected to the second wiring 44 selectively like the first wiring 33.

따라서, 본 발명은 프로그램될 배선과 프로그램되지 않을 배선을 적층시켜 칩의 크기를 감소시킬 수 있는 잇점이 있다.Therefore, the present invention has the advantage that the size of the chip can be reduced by stacking the wiring to be programmed and the wiring not to be programmed.

Claims (6)

기판 상에 제 1 배선을 형성하는 공정과, 상기 제 1 배선 상에 제 1 안티퓨즈를 형성하는 공정과, 상기 기판상에 상기 제 1 배선 및 제 1 안티퓨즈를 덮도록 제 1 층간절연막을 형성하고 상기 제 1 층간절연막에 상기 제 1 안티퓨즈를 노출시키는 제 1 접촉창을 형성하는 갖는 제 1 층간절연막을 형성하는 공정과, 상기 제 1 접촉창을 채우는 제 1 플러그를 형성하고 상기 제 1 층간절연막 상에 상기 제 1 플러그와 접촉되도록 제 2 배선을 형성하는 공정과, 상기 제 1 층간절연막 상에 상기 제 2 배선을 덮도록 제 2 층간절연막을 형성하고 상기 제 2 층간절연막에 상기 제 2 배선을 노출시키는 제 2 접촉창을 형성하는 공정과, 상기 제 2 접촉창을 채우는 제 2 플러그를 형성하고 상기 제 2 층간절연막 상에 상기 제 2 플러그와 접촉되도록 제 2 안티퓨즈를 형성하는 공정과, 상기 제 2 층간절연막 상에 상기 제 2 안티퓨즈와 접촉되는 제 3 배선을 형성하는 공정을 구비하는 안티퓨즈를 이용한 배선방법.Forming a first wiring on the substrate, forming a first antifuse on the first wiring, and forming a first interlayer insulating film to cover the first wiring and the first antifuse on the substrate And forming a first interlayer insulating film having a first contact window exposing the first antifuse to the first interlayer insulating film, and forming a first plug filling the first contact window. Forming a second wiring on the insulating film so as to be in contact with the first plug; forming a second interlayer insulating film on the first interlayer insulating film to cover the second wiring; and forming the second wiring on the second interlayer insulating film. Forming a second contact window exposing the second contact window, and forming a second plug filling the second contact window and forming a second antifuse to contact the second plug on the second interlayer insulating film. And forming a third wiring in contact with the second antifuse on the second interlayer insulating film. 청구항 1에 있어서, 상기 제 1, 제 2 및 제 3 배선을 TiW 또는 Ti 계열의 화합물로 형성하는 안티퓨즈를 이용한 배선방법.The wiring method according to claim 1, wherein the first, second, and third wirings are formed of a TiW or Ti-based compound. 청구항 1에 있어서, 상기 제 1 배선을 2개 이상 다수 개로 형성하는 안티퓨즈를 이용한 배선방법.The wiring method according to claim 1, wherein the first wiring is formed in two or more. 청구항 3에 있어서, 상기 제 1 배선 사이에 평탄화막을 형성하는 공정을 더 구비하는 안티퓨즈를 이용한 배선방법.The wiring method using antifuse according to claim 3, further comprising a step of forming a planarization film between the first wirings. 청구항 4에 있어서, 상기 평탄화막을 산화실리콘으로 형성하는 안티퓨즈를 이용한 배선방법.The wiring method according to claim 4, wherein the planarization film is formed of silicon oxide. 청구항 1에 있어서, 상기 제 1 및 제 2 안티퓨즈를 불순물이 도핑되지 않은 비정질실리콘으로 형성하는 안티퓨즈를 이용한 배선방법.The wiring method of claim 1, wherein the first and second antifuses are formed of amorphous silicon that is not doped with impurities.
KR1019970016124A 1997-04-29 1997-04-29 Method of forming metal wiring using antifuse KR100227071B1 (en)

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