KR20010037569A - System Stabilizing Circuit - Google Patents

Abstract

PURPOSE: A system stabilization circuit is provided to implement a watchdog function of a reset IC by using a PLD(Programmable Logic Device) so that it can prevent a router from falling into an unlimited loop. CONSTITUTION: The circuit comprises a CPU(21), a PLD(22), a timer(23) and a reset IC(24). The CPU(21) receives an interrupt signal from the PLD(22), reads and records a watchdog address range allocated in an address map, and outputs an address strobe signal(/PADS) via an inner address strobe terminal. The PLD(22) generates an interrupt signal(/INT0), outputs the interrupt signal to the CPU(21), decodes the address strobe signal(/PADS) from the CPU(21), and transmits a corresponding watchdog signal(/WATCH_DOG) in a low level to the reset IC(24). The timer(23) outputs clock signals(TIME_INT) by a regular frequency to the PLD(22). The reset IC(24) resets the system in the case that the watchdog signal(/WATCH_DOG) is not driven from the PLD(22) for a time.

Description

System Stabilizing Circuit

The present invention relates to a system stabilization circuit, and more particularly, to a system stabilization circuit for implementing a watchdog function of a reset IC in an PLD using an interrupt.

In general, one of the most commonly used techniques for stabilizing the system is a watch dog. The watch dog is described as follows.

First, as shown in FIG. 1 as a configuration of a system stabilization circuit associated with a watchdog, a CPU 11, a reset IC 12, and a PLD 13 for controlling each chip are formed. have.

There are three cases of the reset condition of the reset IC 12. There are a power monitor, a push button reset, and a watchdog timer.

First, for the power monitor, if the Select 5% or 10% VCC Detect (TOL) pin of the reset IC 12 is connected to the power supply (VCC), the reset IC (12) is powered by the system. Will be monitored and reset below 4.5 (V).

Secondly, in the case of reset of the corresponding push button, when the 'low' level signal is input to the push button reset pin (/ PBRST) of the corresponding reset IC 12, the reset IC 12 resets the system. do. In this case, normally, when a read operation or a write operation is performed on the address area allocated to the address map in the corresponding PLD 13, a 'low' level signal is input to the corresponding push button reset pin (/ PBRST).

Third, in the case of a watchdog timer, when the Time Delay Set (TD) pin of the reset IC 12 is connected to a power supply (VCC), the reset IC 12 is typically the input of the watchdog pin (/ WD). If there is no Falling Edge input during (Typical) 1.2 (s) and Maximum (500) ms, it will reset.

When using the watchdog timer function which is the third condition to stabilize the system among the reset conditions, an address strobe signal (Address Strobe) of the corresponding CPU 11 which is output every time the address is driven by the CPU 11 The signal dog / AS) was used as the input of the watch dog pin (/ WD) to utilize the watch dog timer function.

However, conventionally, when using the watchdog function, by using the hardware address strobe signal of the CPU, the system does not go down when the CPU does not give an address because there is no traffic in the actual system. Although not present, the reset IC will reset because the watchdog pin input does not have a falling edge for up to 500 (ms). As a result, there is a problem that the user can lower the reliability of the product and ensure the stability in terms of NMS (Network Management System).

In order to solve the above-described problems, the present invention is to fall into an endless loop in software in a system such as a router (Local Area Network) -WAN (Wide Area Network) connection equipment (Router) In order to prevent the system from operating stably and to shut down, in the abnormal operation of the system, the reset IC uses the watchdog of the reset IC that the system itself actively resets itself and restarts from the beginning. Implementing watchdog functions using interrupts using PLDs and peripheral logic can improve system stability, enable more stable remote control in terms of NMS, and improve product reliability from the user's point of view. have.

1 is a block diagram showing a conventional system stabilization circuit.

2 is a block diagram showing a system stabilization circuit according to an embodiment of the present invention.

FIG. 3 is an exemplary diagram illustrating an address map in which a watch dog address is assigned in FIG. 2; FIG.

FIG. 4 is a diagram illustrating timing of signals between components in FIG. 2. FIG.

Explanation of symbols on the main parts of the drawings

21: Central Processing Unit (CPU)

22: PLD (Programmable Logic Device)

23: Timer

24: reset integrated circuit (IC)

In order to achieve the above object, the present invention provides a system stabilization circuit having a reset IC which resets a system when there is no driving of a watchdog signal for a predetermined time, and generates a clock signal of a predetermined period. Giving timer; A logic circuit unit generating an interrupt signal using the clock signal generated by the timer, decoding the address strobe signal, and applying the watchdog signal to the reset IC; And a CPU which processes an interrupt of the interrupt signal generated by the PLD and outputs an address strobe signal to the PLD.

The CPU may be configured to receive an interrupt every predetermined period and to record an arbitrary value in a watchdog address area allocated to an address map.

The PLD decodes an address strobe signal applied from the CPU and inputs the watchdog signal to the reset IC at a 'low' level when a write operation is performed at a address area allocated to an address map in the CPU. It is characterized by.

The present invention provides system stabilization logic using an interrupt method, and provides an interrupt method using a logic equation (Equation). Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 2, the system stabilization circuit according to the embodiment of the present invention includes a CPU 21, a PLD 22, a timer 23, and a reset IC 24.

The CPU 21 receives an interrupt signal (/ INT0) from the PLD 22 and performs a read operation or a write operation on the watchdog address area assigned to the address map for interrupt processing through an internal address strobe terminal. The address strobe signal / PADS is outputted to the PLD 22.

The PLD 22 generates an interrupt signal / INT0 according to the clock signal TIME_INT applied from the timer 23, outputs the interrupt signal / INT0 to the CPU 21, and an address straw applied from the CPU 21. The decoded signal dog (/ PADS) is decoded and the decoded watchdog signal / WATCH_DOG is applied to the watchdog terminal (/ WD) input of the reset IC 24 at a 'low' level.

The timer 23 uses a general commercially available timer chip in a system board, and outputs a clock signal TIME_INT to the PLD 22 at intervals of a predetermined period. Here, the clock signal TIME_INT has a cycle of 62.5 (ms).

The reset IC 24 resets the system when the watchdog signal / WATCH_DOG is not driven from the PLD 22 for a predetermined time.

Referring to the operation of the system stabilization circuit according to an embodiment of the present invention configured as described above are as follows.

First, program a clock signal (TIME_INT) of 62.5 (ms) cycle to PLD (22) using general commercial timer chip in system board, eg 'N82C54' of Intel Corporation. The PLD 22 generates an interrupt signal / INT0 according to the clock signal TIME_INT and outputs the interrupt signal / INT0 to the interrupt pin / INT0 in the CPU 21.

At this time, when the CPU 21 receives the interrupt signal / INT0 from the PLD 22, the CPU 21 detects the falling edge of the interrupt and receives the interrupt every 62.5 (ms). That is, the CPU 21 writes an arbitrary value in the watchdog address area allocated to the address map as shown in FIG. 3 to interrupt processing of the interrupt signal (/ INT0) applied from the PLD 22. Take care of it. 3 is a diagram illustrating an address map in which a watchdog address is assigned to '0x5000 0000' as an example.

Accordingly, when the address strobe signal / PADS applied from the CPU 21 is decoded by the PLD 22 and a write operation is performed on the address area, the PLD 22 uses a watchdog signal / WATCH_DOG. Is inputted to the watchdog terminal (/ WD) of the reset IC 24 at a 'low' level.

At this time, if the watchdog signal / WATCH_DOG applied from the PLD 22 is not driven for a maximum of 500 ms, the reset IC 24 may be in an infinite loop or may not operate. Then reset the system. Here, since the watchdog function has a time of 500 ms, if the CPU 21 fails to perform the interrupt processing up to eight times, the CPU 21 resets the interrupt signal so that the CPU 21 interrupts the interrupt signal (Interrupt Priority). / INT0) interrupts can also be considered.

4 is a diagram illustrating timing of signals transmitted and received between components, and a preset signal (/ PRESET) is a reset signal in a system board input to the PLD 22 and an address strobe signal (/ PADS). And a read and write signal / PRD is a signal of the CPU 21 input to the PLD 22, a clock signal TIME_INT is a signal of the timer 23 input to the PLD 22, The interrupt signal / INT0 and the ready signal / PREADY are signals output from the PLD 22 to the CPU 21, and the watchdog signal / WATCH_DOG is the reset IC 24 at the PLD 22. This signal is output as

As described above, in using the watchdog function that the system itself actively resets its own system to restart from the beginning in response to an abnormal operation of the system, conventionally, the actual system using a hardware address strobe signal of the CPU Even if there is no traffic and the CPU does not output the address, it resets the system even if the CPU does not output the address. It is possible to improve the system stability by implementing the PLD using interrupts, and much more stable remote control in terms of NMS, and improve the reliability of the product from the user's point of view.

Claims (3)

A system stabilization circuit comprising a reset IC for resetting a system when there is no driving of a watchdog signal for a predetermined time, A timer for generating a clock signal of a predetermined period; A logic circuit unit generating an interrupt signal using the clock signal generated by the timer, decoding the address strobe signal, and applying the watchdog signal to the reset IC; And a CPU which processes an interrupt of the interrupt signal generated by the PLD and outputs an address strobe signal to the PLD. The method of claim 1, And processing the CPU by receiving an interrupt every predetermined period and writing an arbitrary value to the watchdog address assigned to the address map. The method of claim 1, The PLD decodes the address strobe signal applied from the CPU and inputs the watchdog signal to the reset IC at a 'low' level when a write operation is performed in a address area allocated to an address map in the CPU. System stabilization circuit.