KR100429265B1 - Common communication interface by programable logic divice - Google Patents

Abstract

The present invention is a CPU for the overall control of the system and performing basic operations, a plurality of devices providing additional functions to the system through packet data transmission and reception with the CPU, connected between the plurality of devices and the CPU, interrupts from each device When received, it is possible to determine the type of the interrupt by using the state information of the device, and wait until the packet transmitted from the device is one complete packet data according to the determination result, and then perform the transmission and reception at once. It is characterized by consisting of a logic device.

According to the present invention, since the device buffer is small, an interrupt is generated several times to transmit and receive data to and from the CPU. The data is collected and transmitted to the CPU at once from the PLD to reduce the interrupt time of the CPU, and to perform system basic operations. By providing time, the effect of improving the performance of the system is expected.

Description

Common communication interface by programmable logic divice}

The present invention relates to an interface for transmitting and receiving between a CPU and a peripheral device, and in particular, a programmable logic device for reducing the load on the CPU and increasing the overall speed by allowing the programmable logic device to transmit and receive data between the CPU and the peripheral device. It relates to a common transmission and reception interface using.

The buffer of each device is used to transmit and receive data between the CPU of the system and the peripheral communication devices.

1 is a block diagram showing a configuration for transmitting and receiving between a conventional CPU and a peripheral device.

Referring to FIG. 1, in the data transmission and reception between the CPU 10 and the CPU 10 and the peripheral devices 1, 2 (20, 30) for performing overall control and operation of the system, the devices 1, 2 The buffer configured at (20, 30) is used.

For example, in order to transmit data from the device 1 20 to the CPU 10, the device 1 20 sends an interrupt signal indicating that there is data to transmit to the CPU 10.

Accordingly, the CPU 10 analyzes the received interrupt and knows that the device 1 10 wants to transmit data, and accesses the device 1 20 using a polling command to receive data in a buffer. Done. The polling command inquires of a plurality of terminal apparatuses sequentially from a computer or a terminal control apparatus whether there is a transmission request, and instructs the terminal apparatus to start transmission if there is a request. The transmission control method inquired about.

On the other hand, since the buffer of the device 1 20 is not large enough to store one complete packet, the data received by the CPU 10 is a part of the complete packet.

Therefore, the device 1 20 stores the next data in the buffer and sends an interrupt signal to the CPU 10 to request the data to be received.

As described above, in order to transmit one complete packet to the CPU 10, the device 1 20 must send an interrupt signal several times, and the CPU 10 also issues a polling command several times and the device 1 ( 20) must be accessed.

In addition, when the CPU 10 transmits data to the device 2 30, the CPU 10 must divide and transmit data to the buffer of the device 2 20 several times in order for the CPU 10 to transmit one packet data.

This is because the buffer of the device 2 30 is not large enough to store one packet so that the CPU 10 uses interrupts and polling multiple times to prevent an error such as overrun or underrun. To send.

However, the data transmission / reception method as described above is a software data transmission / reception method in which the CPU 10 needs to access and work with the devices 1, 2 (20, 30) several times for data transmission / reception. As the CPU load increases, the time for executing basic operations of the system operation is reduced, resulting in a decrease in system performance.

In order to solve the above problems, the present invention does not perform data transmission and reception between the CPU and the peripheral device using interrupt and polling instructions using a small buffer of the device as in the prior art, and a program between the device and the CPU is executed. A programmable logic device (PLD) is further configured to allow the PLD to collect data from the device little by little and send and receive data to and from the CPU to the CPU, thereby reducing the load on the CPU and reducing interrupt time. The goal is to provide a common transmit / receive interface using a programmable logic device that can increase system performance by minimizing the CPU's time to execute basic tasks by minimizing it.

1 is a block diagram showing a system configuration for transmitting and receiving data between a conventional CPU and a peripheral device.

2 is a block diagram illustrating a system configuration according to a common transmit / receive interface using a PLD according to an embodiment of the present invention.

3 is a block diagram showing the configuration of the PLD of FIG.

4 is a flowchart illustrating an operation procedure for allowing a CPU to receive data from a device in a common transmit / receive interface using a PLD according to an embodiment of the present invention.

5 is a flowchart illustrating an operation procedure of a CPU transmitting data to a device in a common transmit / receive interface using a PLD according to an embodiment of the present invention.

CPU for overall control and basic operation of the system according to the present invention; A plurality of devices for providing additional functions to the system through the packet data transmission and reception with the CPU; And connected between the plurality of devices and the CPU, each device When an interrupt is received from the device, the type of the interrupt is determined by using the state information of the corresponding device, and the packet transmitted from the device is waited until the complete packet data is transmitted according to the determination result. And a programmable logic device.

Advantageously, said programmable logic device comprises:

A device interface unit connected to a plurality of peripheral devices and providing an interface for transmitting and receiving data and device state information with each device;

A device state unit which stores device state information received by the device interface unit;

An interrupt controller for controlling interrupt signals for data transmission and reception between the plurality of devices and the CPU;

A main controller configured to determine an interrupt received by the interrupt controller to transmit and receive data from a device;

A reception buffer for temporarily storing data transmitted from the plurality of devices;

A transmission buffer for temporarily storing data transmitted from the CPU to the device;

A buffer agent managing data storage and deletion of the receiving buffer and the transmitting buffer;

A CPU interface unit in charge of interfacing with the CPU;

And a logic state unit indicating overall state information of the PLD.

A common transmit / receive interface using a programmable logic device according to the present invention configured as described above will be described with reference to the accompanying drawings.

2 is a block diagram illustrating a system configuration based on a common transmit / receive interface using a PLD according to an embodiment of the present invention.

2, the present invention configures the PLD 40 between the CPU 10 and the peripheral devices 1, 2 (20, 30), and from the devices 1, 2 (20, 30) in the PLD 40; It waits until the received data becomes one packet and transmits it to the CPU 10 at once.

At this time, the device has a status register for transmitting and receiving a packet, each of which has a slightly different nature and name, but has the status information required for the PLD to operate, so no matter what device and the PLD is connected to the mapping in the device interface configured in the PLD If you do it well, you can send / receive smoothly.

The configuration of the PLD 40 will be described in detail with reference to FIG. 3.

3 is a block diagram showing the configuration of the PLD of FIG.

Referring to FIG. 3, a device interface unit 42 connected to a plurality of peripheral devices 20 and 30 to provide an interface for transmitting and receiving data and device state information with each device, and the device interface unit 42. A device state unit 41 for storing device state information received by the controller; an interrupt controller 44 for controlling an interrupt signal for data transmission and reception between the plurality of devices 20 and 30 and the CPU 10; and the interrupt A main controller 43 for determining the interrupt received by the controller 44 to transmit and receive data from the device, a reception buffer 47 for temporarily storing data transmitted from the plurality of devices, and the CPU 10 Transmit buffer 46 for temporarily storing data to be transmitted from the device to the device, and buffer A for managing data storage and deletion of the receive buffer 47 and the transmit buffer 46 And a logic state unit 49 representing overall state information of the PLD 40, and a CPU interface unit 48 that is in charge of the interface with the CPU 10. .

4 and 5 operate data transmission and reception between the device and the CPU in the common transmission / reception interface using the PLD configured as described above.

4 is a flowchart illustrating an operation procedure of allowing a CPU to receive data from a device in a common transmit / receive interface using a PLD according to an embodiment of the present invention, and FIG. 5 is a common transmit / receive interface using a PLD according to an embodiment of the present invention. Is a flow chart showing the operation procedure of the CPU sending data to the device.

First, referring to FIG. 4, when data is received from the device 1 20 (S101), an interrupt is generated to receive the received data from the CPU 10 (S102).

The interrupt is transmitted to the interrupt control section 44 of the PLD 40 (S103), and the main control section 43 of the PLD 40 knows that a new interrupt has been received by the interrupt control section 44, and determines the type of interrupt. In order to update the device status information to the device interface unit 42 in order to (S104).

According to the update command, when the device interface unit 42 detects the state of the device and stores the state of the device in the device state unit 41 (S105), the interrupt received by the main control unit 43 according to the device state is the device 1 ( In step 20), it is determined whether an interrupt is received that a part of new packet data is received or an interrupt that the last data of the packet data is received (S106). If the interrupt is that a part of new packet data is received, the reception buffer of the device 1 (20) is Loading (S107), the buffer agent 45 instructs to store the loaded data in the reception buffer 47 (S108).

However, if the interrupt is an interrupt indicating the reception of the last data of the packet, the main controller 43 loads the data stored in the reception buffer of the device 1 20 (S109), and instructs the buffer agent 45 to instruct the reception buffer. After storing the loaded data at 47 (S110), the PLD status unit 49 is to indicate that there is packet data to be transmitted to the reception buffer 47 (S111).

The interrupt controller 44 transmits an interrupt to the CPU 10 (S112), so that the CPU 10 receives a packet of the reception buffer 47 through the CPU interface unit 48 (S113).

In addition, the CPU 10 deletes the contents of the reception buffer 47 after receiving the data of the reception buffer 47 (S114), so as to receive data from another device.

This means that even when the data stored in the reception buffer 47 is wrong data, the reception buffer 47 is emptied and enters a state waiting for another interrupt.

On the other hand, if the type of interrupt in step S106 is an interrupt indicating an error or other event not related to data reception, the PLD status unit 49 displays an event of another part (S114), and interrupts the CPU ( 10) (S115).

An operation when the CPU 10 receiving data from the device transmits data to the device 2 30 as described above will be described in detail as follows.

Referring to FIG. 5, in order to transmit one complete packet from the CPU 10 to the device 2 30, first, packet data is stored in the transmission buffer 46 of the PLD 40 (S201), and the PLD state unit In operation S202, an indication that there is a packet to be transmitted to the device 2 30 is made.

If the PLD status section 49 indicates that there is data in the transmission buffer, the main control section 43 needs to know whether the status of the device 2 30 can transmit data, so that the device interface section 42 In step S203, the device interface unit 42 checks the states of the devices 20 and 30 and updates the device state unit 41 (S204).

The main controller 43 looks at the updated information of the device status unit 41, determines whether data can be transmitted to the device 2 30 (S205), and continues until it becomes a state capable of transmitting data. Periodically waiting for the device interface unit 42 to update the device status unit 41.

When the data can be transmitted to the device 2 (30) (S205), the main control unit 43 is adapted to store the data stored in the transmission buffer 46 of the PLD in accordance with the size of the transmission buffer of the device 2 (30). The data is divided (S206) and transmitted to the transmission buffer of the device 2 (30) (S207).

The main control unit 43 repeats the device status check and data transmission until the data transmission is completed, and when the transmission is completed (S208), after receiving an interrupt indicating whether the data transmission is normally completed from the device 2 (30) ( In step S209, when an interrupt is received that data transmission is normally completed, the PLD status unit 49 indicates that data transmission is completed (S210), and the transmission buffer 46 is emptied (S211).

If there is an interrupt regarding the packet transmission error from the device 2 (30), the main control unit 43 transmits the packet again from the beginning (S203 to S211).

As described above, by using the transmit buffer and the receive buffer in the PLD, the data received from the device to the CPU are collected and transferred to the CPU at once, and the data transmitted from the CPU to the device are stored at once and transmitted in a separate manner. The more time you take for basic operations, the better the performance of your system.

As described above, the common transmit / receive interface using the PLD according to the present invention transmits an interrupt signal to the CPU several times by using a small buffer provided in the device when transmitting data from the device to the CPU. The problem that the CPU has not enough time for the basic operation of the system due to the problem that the data has to be transmitted several times even when the CPU transmits data to the device has caused a problem of poor performance of the system. It connects PLD to transmit / receive data transmitted / received to / from CPU several times at once, minimizing interrupt processing time in CPU and making much time to use for basic operation of system. It can be effected.

Claims (5)

A CPU for overall control and basic operation of the system; A plurality of devices providing additional functions to the system by transmitting and receiving packet data with the CPU; Connected between the plurality of devices and the CPU, when an interrupt is received from each device, the type of the interrupt is determined using the state information of the corresponding device, and according to the determination result, a packet transmitted from the corresponding device is one complete. A common transmit / receive interface using a PLD, comprising a programmable logic device that waits for packet data and then transmits and receives at a time. The device of claim 1, wherein the programmable logic device is A device interface unit connected to a plurality of peripheral devices and providing an interface for transmitting and receiving data and device state information with each device; A device state unit which stores device state information received by the device interface unit; An interrupt controller for controlling interrupt signals for data transmission and reception between the plurality of devices and the CPU; A main controller configured to determine an interrupt received by the interrupt controller to transmit and receive data from a device; A reception buffer for temporarily storing data transmitted from the plurality of devices; A transmission buffer for temporarily storing data transmitted from the CPU to the device; A buffer agent managing data storage and deletion of the receiving buffer and the transmitting buffer; A CPU interface unit in charge of interfacing with the CPU; And a logic state unit indicating overall state information of the PLD. In the method for performing packet data transmission and reception using a PLD provided between a plurality of devices and the CPU, Generating an interrupt by generating packet data to be transmitted from the device to the CPU; If an interrupt generated in the device is received in a PLD, determining the received interrupt type by using status information of the device in the PLD; If it is determined that the interrupt is an interrupt for receiving the last packet of the packet data, loading the packet data stored in the device and storing the packet data in the reception buffer, indicating a waiting for a transmission packet, and transmitting the interrupt to the CPU; And receiving the stored packet data and deleting the contents of the reception buffer when the interrupt transmitted from the PLD is received by the CPU. 4. The method of claim 3, wherein if the interrupt is an interrupt for receiving a packet of a portion of the packet data, the packet is stored in a receiving buffer and the next packet is received. The method of claim 3, wherein the packet data is transmitted from the CPU to a device. Storing, at a CPU, the packet data in a transmission buffer of a PLD, and indicating that there is data to be transmitted to a device; Updating the state information of a destination device to which the packet data is to be transmitted in the PLD, and if possible, dividing the packet data into packets according to a buffer size of the device; Transmitting all the divided packets, receiving an interrupt for transmission completion from the device, indicating completion of packet data transmission, and deleting contents of the transmission buffer. Common transmit and receive interface method.