KR19990010664A - System reset circuit and method through command - Google Patents

Abstract

end. The technical field to which the invention described in the claims belongs:

The present invention relates to a system having a central processing unit and a console connected thereto.

I. The technical problem the invention is trying to solve:

In order to reset the system having the central processing unit, there were a program method and an operator directly operating the reset switch.

All. The gist of the solution of the invention:

The present invention sets and outputs a specific bit of an address when a reset command is applied from the console, and resets an address strobe signal when the address is applied, and outputs a reset signal for resetting the system when the reset state is maintained for a predetermined time. In order to implement the system reset circuit and method through the command.

la. Important uses of the invention:

System reset circuit and method via command.

Description

System reset circuit and method through command

The present invention relates to a system having a central processing unit, and more particularly, to a reset circuit and a method for resetting the system by a command applied from a console.

In general, in a system having a central processing unit (hereinafter referred to as a CPU), the reset signal of the CPU and the control chip must be applied for a predetermined time given for initialization of the chip when the power is initially supplied. do.

In the conventional system, a separate reset switch has to be provided and operated by the operator directly on / off when the reset switch is reset. At this time, when the operator needs to reset the system away from the system, the operator approaches the system and has a troublesome problem of turning on / off by directly operating the reset switch.

Also, if you try to create a reset routine in software rather than a reset switch, it is difficult to create a routine to reboot in an operating system (OS) or if the tasks are alive before the reboot, It may cause a malfunction.

Accordingly, an object of the present invention for solving the above problems is to provide a reset circuit that hardware resets the system when a command to reset the system is input at the console.

Another object of the present invention is to provide a reset method for hardware reset of a system when a command to reset the system is input from a console.

In order to achieve the above object, the present invention sets and outputs a specific bit of an address when a reset command is applied from a console, and resets the address strobe signal when the address is applied to maintain the system when the reset state is maintained for a predetermined time. A system reset circuit and method are implemented through a command to output a reset signal for resetting.

1 is a schematic block diagram of a system according to an embodiment of the present invention.

FIG. 2 is a detailed configuration diagram of the reset detection and application circuit shown in FIG.

3 is a reset timing diagram according to an embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic block diagram of a system according to an embodiment of the present invention. A console 110 is connected to the system 120 through an RS-232C port.

The console 110 refers to an operation table having various displays for the operator of the system 120 to monitor the operating state of the system 120 or a key for applying a command to the system 120.

The system 120 includes a central processing unit (CPU) 10, an MFP 12, a memory 14, a peripheral chip 16, a reset detection and application circuit 18, and a reset as shown in FIG. Switch 20 or the like. The CPU 10 controls the overall operation of the system 120. The memory 14 stores control programs and various data used in the system 120. The peripheral chip 16 may collectively refer to various chips used in the system 120. The reset switch 18 is a switch that is turned on / off by an operator's operation for resetting the system 120. The reset detection and application circuit 18 detects the application of data in which a specific bit is set from the CPU 10 and outputs a reset signal.

FIG. 2 is a diagram showing the detailed configuration of the reset detection and application circuit 18 shown in FIG.

The reset detection and application circuit 18 includes an address decoding unit 30, a flip-flop (F / F) 32, a watchdog timer 38, as shown in FIG. Inverter 40 and two D flip-flops (DF / F) 34 and 36.

The address decoding unit 30 decodes a specific address and outputs a chip select (CS) signal. The F / F 32 buffers the data DATA applied from the CPU 10 using the CS signal as the clock signal. The D F / F 34 outputs the buffered data using the CS signal as a clock signal. In the D F / F 36, the data SRES applied from the D F / F 34 is applied to the reset terminal CD, and an address strobe AS is applied to the input terminal D. The watchdog timer 38 monitors the signal Q applied from the D F / F 36 and outputs a reset signal RESET signal when the low state is maintained for a predetermined time. The inverter 40 inverts the reset signal and applies the reset signal to the reset terminal CD of the D F / F 34.

3 is a reset timing diagram according to a process of generating a reset signal in FIG. 2.

Hereinafter, an embodiment according to the present invention will be described in detail with reference to the above-described configuration.

When the operator of the system wants to reset the system by rebooting, a command hardware reset is input through the console 110 to request the system to be rebooted. The command entered by the operator is applied to the system 120 via the RS-232C port.

The CPU 10 of the system 120 receives a reset command from the console 110 and sets a specific bit of a specific address (eg, 10000000h).

The address where the specific bit is set is applied to the address decoding unit 30 of FIG. 2, and the address decoding unit 30 decodes the applied address and outputs a CS signal.

The CS signal is applied as a clock signal of the D F / F 34, and outputs the data applied through the F / F 32 to the output terminal Q when the clock signal rises. That is, as shown in FIG. 3, the high level DATA applied to the input terminal is read at the point where the CS signal rises and outputs the high level SRES.

The SRES signal is applied as a reset signal of the D F / F 36. The D F / F 36 receives an AS signal and outputs the signal according to a clock in order to monitor whether the CPU 10 of the system 120 operates normally. However, when the SRES signal is applied and reset, the AS signal is not output. That is, as shown in FIG. 3, the SRES signal is reset at the rising edge, so that the AS signal is not output and the low level Q signal is output.

At this time, the watchdog timer 38, which is receiving the Q signal output from the DF / F 36, stops the system 120 when the AS signal is not applied and the low level Q signal is maintained until a predetermined time elapses. Outputs a reset signal for resetting. The watchdog timer 38 used a DS1232 manufactured by Dallas Semiconductor. That is, as shown in FIG. 3, when a predetermined time T has elapsed at the point where the Q signal falls, the high level reset signal is inverted to a low level and output.

When a reset signal for resetting the system 120 is output, the reset signal is applied to the reset terminal CD of the D F / F 34 through the inverter 40.

When the inverted reset signal is applied by the inverter 40, the D F / F 34 is reset and falls on the falling edge. As a result, the SRES signal goes low again, and the reset of the D F / F 36 is canceled and the system 120 reboots. That is, as shown in FIG. 3, the SRES signal falls on the falling edge at the point where the RESET signal falls, and the SRES signal in the low state is output.

By the above-described operation, the operator of the system 120 can reboot the system 120 at any time using the console 110.

As described above, the present invention provides a convenience for the operator of the system by providing a reset detection unit in front of the watchdog timer to reset the system by instructing the console when a system malfunction is required as well as a CPU malfunction.

Claims (2)

A reset circuit for resetting a system by a reset command applied from a console, the reset circuit comprising: an address decoding unit configured to decode an address input by setting a specific bit from a central processing unit by applying the reset command, and output a chip select signal; A first D flip flop that outputs the address value using a chip select signal as a clock signal, and an address strobe signal input for monitoring a malfunction of the central processing unit, and reset by a signal applied from the first D flip flop A watchdog timer for monitoring the 2D flip flop and the signal applied from the 2D flip flop and outputting a reset signal for resetting the system when the address strobe signal is not applied for a predetermined time; An inverter that is inverted and applied as a reset signal of the first flip flop. That the system reset circuit with an instruction according to claim. A method of resetting a system by a reset command applied from a console, the method comprising: setting and outputting a specific bit of an address when the reset command is applied, decoding the address, and outputting a chip select signal; Resetting an address strobe signal for monitoring a malfunction by reading the address value using a selection signal as a clock signal, and outputting a reset signal for resetting the system when the reset state is maintained for a predetermined time; And resetting the address strobe signal by inverting the reset signal.