KR20010029072A - Driving method of plasma display panel - Google Patents

Abstract

PURPOSE: A method of driving a plasma display panel is provided to allow the panel to have a uniform luminance characteristic on all portions of screen surface by controlling discharge sustaining time periods to be different from one another. CONSTITUTION: An apparatus for driving a plasma display panel(10) includes a timing signal generating part(80), a scanning electrode driving part(20), a sustaining electrode driving part(40), a luminance memory(110), and a microprocessor(120). The timing signal generating part(80) generates timing data which determine a luminance of the panel(10). The scanning electrode driving part(20) and the sustaining electrode driving part(40) generate a sustaining pulse according to the timing data and provide the sustaining pulse to scanning electrodes and sustaining electrodes to maintain cell discharges. The luminance memory(110) stores luminance compensating values corresponding to the scanning electrodes. The microprocessor(120) which is programmed to perform a method according to the present invention controls the discharging time periods of each of discharge cells based on the luminance compensating values stored in the luminance memory(120). The microcomputer (120) divides one frame into Y sub-fields and converts image data into digital data of X bits. And, the microcomputer(120) provides the X bits to each of the sub-fields.

Description

Driving method of plasma display panel {Driving method of plasma display panel}

The present invention relates to a method of driving a plasma display panel. More particularly, the entire panel is uniformly adjusted by adjusting the discharge holding time for each row electrode differently according to the luminance correction value set for each row electrode. It is intended to have a luminance characteristic.

As is well known, in the plasma display panel, two substrates are coupled at a predetermined distance, discharge gas is filled therein, and a plurality of row electrodes and column electrodes are arranged orthogonal to each other to form a plurality of discharge cells. The discharge is obtained by controlling the applied voltage, and the amount of light is controlled by changing the length of the discharge time.

In each discharge cell of such a plasma display panel, an address discharge is generated between a row electrode and a column electrode (hereinafter referred to as an "address electrode") to address a pixel, between two row electrodes, that is, a scan electrode and Sustain discharge, which is induced between the sustain electrode and maintains discharge light emission, and erasure discharge, which stops light emission of the discharged cell, are selectively induced.

As an example according to the related art of the apparatus for driving the plasma display panel, the driving apparatus shown in the block diagram in FIG. 1 will be described below.

The scan electrode and the address electrode of the panel 10 are insulated so as to independently apply a driving voltage to each individual electrode, and are connected to the scan electrode driving circuit 20 and the first and second address electrode driving circuits 30. The sustain electrodes are all connected in parallel and commonly connected to the sustain electrode driving circuit 40.

The microprocessor 50 controls the entire system according to external signals (CLOCK, BLANK, Hsync, Vsync) and a scanning method, and the data array unit 60 is inputted by R and G under the control of the microprocessor 50. The B image signal data is rearranged in order from the upper bit to the lower bit in the order of the pixels arranged in the panel 10. The sorted data is stored in the frame memory 70 for each bit.

The reference address of the frame memory 70 is sequentially increased according to the scanning method, and the image signal is output to the panel 10. The timing signal generator 80 applies a high voltage pulse to the scan electrode, the sustain electrode, and the address electrode. Timing data, a transmission clock, and a latch signal are output to each of the driving circuits 20, 30, and 40, whereby a driving pulse is applied to each of the electrodes so that address discharge and sustain discharge selectively induced in a plurality of discharge cells. And an image is displayed on the panel 10 by erasure discharge.

On the other hand, the driving method of the plasma display panel performed by such a driving apparatus is largely divided into a selective light method and a selective erasure method depending on whether a selected cell is turned on or off when specifying a pixel address.

In the selective write method, a selected cell is turned on with an address discharge and then sustain discharge is generated by a predetermined number of times to maintain the discharge light emission. Then, an erase discharge is caused by erasing discharge. Because of this coexistence, a process of allowing the space charge to be formed in advance while maintaining the same wall voltage condition of all cells by the reset discharge before the address discharge in order to match the wall charge state to obtain a stable address discharge.

However, in the selective write method, since the wall charge is sufficiently formed only when the pulse applied to the address electrode has a width of about 3 μs, the scanning time of about 3 μs per line is required.

Moreover, as the resolution increases, the amount of data required for processing increases so that all data must be processed within an extremely limited time in order to drive a high resolution plasma display panel.

Therefore, the panel 10 must be driven by using a plurality of driving circuits after dividing the screen into a plurality of screens, thereby increasing the cost.

In the selective erasure method, all cells are first discharged and turned on, and then selected cells are turned off by address discharge, and then other cells are sustained by sustain discharge. In particular, all cells are required before address discharge addressing pixels. The light must be discharged.

In this case, the pulse width of the address discharge for turning off the selected cell in the state where all the cells are write discharged is about 1 ms.

Accordingly, the selective erasure method can be driven at a relatively higher speed than the selective write method. That is, when driving a high resolution plasma display panel having a large amount of data required per second, per frame, and per data electrode, the selective erasure method is more suitable than the selective light method.

In addition, according to the method of implementing one frame, which is one screen, it is divided into a subframe method and a subfield method. Among the subframe methods, one frame is divided into X subframe screens to implement 2 ^X gray scales. Each subframe has a luminance relative ratio 1: 2: 4: 8: 16: 32: 64:. A number of scan electrodes proportional to is included.

In the subfield method, one frame is divided into Y subfields to implement 2 ^X gray scales as shown in FIG. 2 (where X≤Y). The image data is digitized and supplied to each subfield, and the luminance relative ratio is 1: 2: 4: 8: 16: 32: 64: ... for each subfield. The luminance values which are proportional to each other correspond to each other, so that images corresponding to 0 to 2 ^X −1 gradations are displayed in a combination of several subfields.

For example, as shown in FIG. 2, one frame is divided into _eight subfields SF _{1 to} SF ₈ , and then proportional to 1: 2: 8: 16: 32: 64: 128 for each subfield. When the luminance values are associated with each other, the image corresponding to the gradation data 0 to 255 is displayed by the combination of several subfields, and 256 gradations can be realized.

That is, the first sub-field (SF ₁₎ is supplied to the least significant bit D _0-bit gray-scale data of the gray-scale data (D ₀ ~D ₇₎ of each cell in each cell, and the second to the eighth sub-field (SF ₂ ~SF ₈ ) is of the cell for each of _{D 1, D 2, D 3} , D 4, D 5, D 6, D 7 by supplying bit gradation data for each cell set for each subfield (SF ₁ ~SF ₈₎ sustain period Luminescence is maintained to display an image.

In this case, the luminance value of each subfield is determined by the number of sustain discharges induced between the scan electrodes S _{1 to} S _m and the sustain electrode in the sustain period, that is, the discharge sustain time. A number of sustain pulses in proportion to the luminance value is applied, and in particular, the same number of sustain pulses are applied to all scan electrodes S _{1 to} S _m in one subfield.

According to the related art as described above, the same number of sustain pulses are applied to the scan electrodes S _{1 to} S _m by the scan electrode driving circuit 20 in the sustain period of each subfield, causing the same number of sustain discharges. It can be seen that gradation is implemented by a combination of several of these subfields.

However, conventionally, the same number of sustain pulses are applied to all scan electrodes when displaying images with the same gradation on the entire panel, causing the same number of sustain discharges, i.e. the brightness of the entire panel even when the discharge of all the cells is maintained for the same time. There was a problem that the values had different distributions for each region.

This is because the luminous efficiency of all the discharge cells is not the same due to the thickness of the phosphor coated in the discharge cell, the formation height of the barrier rib, or the difference in the characteristics of the electrode. As a result, the entire panel has different luminance characteristics for each region.

Accordingly, the present invention proposes to solve the problems of the prior art as described above, and the number of sustain pulses for each scan electrode in the sustain period for each subfield is determined according to the luminance correction value set for each scan electrode in consideration of the luminous efficiency of the discharge cell. The purpose of the present invention is to make the entire panel have uniform luminance characteristics by differently applying the discharge sustain time differently for each scan electrode.

1 is a block diagram of a plasma display panel driving apparatus according to the prior art,

2 is a block diagram of a frame according to a plasma display panel driving method according to the prior art,

3 is a block diagram of a driving apparatus for performing a method of driving a plasma display panel according to the present invention;

4 is a configuration diagram of a frame according to a method of driving a plasma display panel according to the present invention.

<Description of the code | symbol about the principal part of drawing>

20: scan electrode driving circuit, 80: timing signal generator, 110: luminance memory, 120: microprocessor

A method of driving a plasma display panel according to the present invention for achieving these objects is to divide one frame into Y subfields to implement 2 ^X gradations, and to supply corresponding bits among the X bit image data to each subfield. In allocating the discharge sustain time of the selected discharge cell for image display to the Y subfields according to the weight of the bit (where X ≦ Y):

The discharge holding time is,

The row electrodes may be adjusted for each subfield according to the luminance characteristics of the discharge cells.

In this case, since the discharge holding time is adjusted differently for each scan electrode in the sustain period for each subfield because of the luminance characteristics of the discharge cells, that is, the luminous efficiency, the number of sustain discharges is different in the discharge cells having different thicknesses or the like. This causes the entire panel to have uniform luminance characteristics.

There may be a plurality of embodiments of the present invention. Hereinafter, the most preferred embodiment will be described in detail with reference to the accompanying drawings.

This preferred embodiment allows for a better understanding of the objects, features and advantages of the present invention.

Incidentally, in the exemplary drawings of the present invention, the same components as in the prior art may be denoted by the same reference numerals and may not be described.

3 is a block diagram of a driving apparatus for performing a method of driving a plasma display panel according to an embodiment of the present invention. The timing signal generator 80 outputs timing data for determining a luminance value of the panel 10. According to the timing data, the scan electrode driving circuit 20 and the sustain electrode driving circuit 40 which apply a sustain pulse for maintaining the discharge of the corresponding cell between the scan electrode and the sustain electrode, and the scan electrodes of the panel 10. A luminance memory 110 having a luminance correction value set therein and a microprocessor 120 for controlling the entire system according to a driving scheme programmed to adjust the discharge holding time of the discharge cells for each scan electrode according to the luminance correction value. .

4 is a configuration diagram of a frame according to a method of driving a plasma display panel according to the present invention, and is represented by representing only three subfields.

As described above, the panel driving method according to the present invention divides one frame into Y subfields to implement 2 ^X gray scales (where X≤Y), and digitizes externally input image data with X bits. Bits are supplied to each subfield, and the sustain periods among the write periods, address periods, sustain periods, and erase periods constituting each subfield are allocated differently according to the bit weights of the image data, and again according to the brightness characteristics of the discharge cells. The scan fields S _{1 to} S _m are adjusted differently for each subfield.

Hereinafter, a process in which an image is displayed by the selective erasure method by the driving apparatus of the plasma display panel as shown in FIG. 3 and one frame has the configuration as shown in FIG. 4 will be described.

First, the R, G, and B image signal data are rearranged in order from the upper bit to the lower bit in the order of the pixels arranged in the panel 10 by the data arranging unit 60 controlled by the microprocessor 120. Each bit is stored in the frame memory 70.

The reference address of the frame memory 70 is sequentially increased by the microprocessor 120 that controls the entire system according to the basic setting value, and the image signal is output to the panel 10. The timing signal generator 80 Outputs timing data, a transfer clock, and a latch signal for applying high voltage pulses to the scan electrodes S _{1 to} S _m , the sustain electrodes and the address electrodes to the driving circuits 20, 30, and 40.

In this case, one frame, which is one screen, is divided into Y subfields to implement 2 ^X gray scales (where X≤Y), and each subfield has a corresponding bit among the X bit image data stored in the frame memory 70. Are supplied respectively.

In each subfield, a write pulse is applied between all the scan electrodes S _{1 to} S _m and the sustain electrode in the write period so that all of the discharge cells are light discharged and the address electrodes of the corresponding cells to be increased in the address period. Erasing scan pulses are sequentially applied between the scan electrodes S _{1 to} S _m to generate an erasure discharge in the corresponding cells, so that the light emission discharges of the corresponding cells disappear. In the sustain period, all scan electrodes S ₁ to S m are erased. A sustain pulse is applied between S _m ) and the sustain electrode so that the cell to which the erase scan pulse is not applied in the address period maintains the light emission discharge. Here, the sustain period of each subfield is allocated differently according to the bit weight of the image data.

After that, when the allocated sustain period is completed, the erase pulses are sequentially applied to all the scan electrodes S _{1 to} S _m in the erase period, and thus the erase discharge is sequentially induced in the corresponding cells that were kept discharged in the sustain period. The light emission discharge of the cell is maintained for the same time and then disappears. That is, the same number of sustain pulses are applied to all scan electrodes S _{1 to} S _m in one subfield.

By the above process, one frame is completed and an image is displayed on the panel 10. As described above, light emission of all the discharge cells is caused due to the thickness of the phosphor coated in the discharge cell, the formation height of the partition wall, or the characteristic difference of the electrode. Due to the unequal efficiency, the entire panel is caused by the same number of sustain discharges, that is, even though the light emitting discharges of all the cells are maintained for the same time, the luminance values have different distributions for each region.

On the other hand, the operator measures the luminance difference for each area of the panel 10 using a separate luminance meter and then sets the luminance correction value for each scan electrode to minimize the luminance difference for each area and stores it in the luminance memory 110. .

Then, in subsequent frames, the microprocessor 120 controls the entire system according to the luminance correction value for each scan electrode stored in the luminance memory 110, and thus the length of the sustain period in each subfield for each scan electrode S _{1 to} S _m . Adjust it. That is, the write period and the address period are performed by the same process as described above. In the sustain period, when the discharge efficiency of the discharge cell is higher than the average value, the number of sustain pulses applied to the corresponding scan electrode is decreased and the emission efficiency is lower than the average value. In this case, the number of sustain pulses applied to the corresponding scan electrode is increased to allocate different discharge sustain times for each subfield for each of the scan electrodes S _{1 to} S _m .

That is, in the state in which the luminance correction value for each scan electrode is stored in the luminance memory 110, the discharge holding time inversely proportional to the light emission efficiency of the discharge cell is allocated for each of the scan electrodes S _{1 to} S _m , and thus the scan electrode driving circuit in the erase period. The erase pulse applied to the scan electrodes S _{1 to} S _m at 20 changes its temporal position according to the luminance correction value.

Therefore, even when the overall luminous efficiency of the panel 10 is not the same, the overall luminance value has the same distribution.

While specific embodiments of the invention have been described and illustrated above, it will be apparent that the invention may be embodied in various modifications by those skilled in the art.

Such modified embodiments should not be individually understood from the technical spirit or the prospect of the present invention, and such modified embodiments should fall within the appended claims of the present invention.

As described above, in the present invention, since the discharge retention time is adjusted differently for each scan electrode in each sustain period in consideration of the luminance characteristics of the discharge cells, that is, the luminous efficiency, the discharge cells have different thicknesses in the discharge cells having different thicknesses. There is an effect that the number of sustain discharges is induced so that the entire panel has a uniform luminance characteristic.

Claims (1)

One frame is divided into Y subfields to implement 2 ^X gradations, a corresponding bit is supplied to each subfield among X-bit image data, and the discharge holding time of the selected discharge cell for image display is assigned to the weight of the bit. In assigning to the Y subfields (where X ≦ Y): The discharge holding time is, And a row electrode for each subfield according to the luminance characteristics of the discharge cells.