KR20010027084A - Method of forming a semiconductor device - Google Patents

Method of forming a semiconductor device Download PDF

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Publication number
KR20010027084A
KR20010027084A KR1019990038661A KR19990038661A KR20010027084A KR 20010027084 A KR20010027084 A KR 20010027084A KR 1019990038661 A KR1019990038661 A KR 1019990038661A KR 19990038661 A KR19990038661 A KR 19990038661A KR 20010027084 A KR20010027084 A KR 20010027084A
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South Korea
Prior art keywords
gate electrode
doped
layer
type
well region
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KR1019990038661A
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Korean (ko)
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이재곤
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박종섭
현대전자산업 주식회사
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Priority to KR1019990038661A priority Critical patent/KR20010027084A/en
Publication of KR20010027084A publication Critical patent/KR20010027084A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to improve a profile in a process for etching an n-type gate electrode and to control performance variation of an n-channel metal-oxide-semiconductor(NMOS) transistor, by forming an excessively-doped phosphosilicate glass(PSG) layer on a polysilicon layer before patterning the n-type gate electrode to perform a diffusion process. CONSTITUTION: After an isolating layer(12) is formed on a semiconductor substrate(11), impurities different from each other are implanted into the semiconductor substrate to form an n-type well region and a p-type well region. After a gate oxide layer(13), a polysilicon layer(14) and an excessively-doped phosphosilicate glass(PSG) layer are sequentially formed on the entire surface, a mask process and an etch process are performed so that the excessively-doped PSG layer is formed only on the p-well region. After a heat treatment is performed to diffuse the excessively-doped PSG layer, a patterning is carried out to form an undoped gate electrode(18) and an n-type doped gate electrode(19) on the n-well and p-well regions, respectively.

Description

반도체 소자 형성방법{Method of forming a semiconductor device}Method of forming a semiconductor device

본 발명은 반도체 소자 형성방법에 관한 것으로 특히, CMOS 트랜지스터 구조의 반도체 소자 형성방법에 관한 것이다.The present invention relates to a method for forming a semiconductor device, and more particularly, to a method for forming a semiconductor device having a CMOS transistor structure.

종래 반도체 소자의 트랜지스터 형성방법을 도 1를 참조하여 설명하면 다음과 같다.A transistor forming method of a conventional semiconductor device will be described with reference to FIG. 1.

도 1을 참조하면, 반도체 기판(11) 상에 LOCOS(Local Oxidation of Silicon) 또는 트렌치(Trench) 공정으로 소자 분리막(12)을 형성한 후 이온 주입 마스크를 이용한 불순물 이온 주입 공정으로 n-웰(Well)영역(Ⅰ) 및 p-웰 영역(Ⅱ)을 형성한다. 그후 PMOS 및 NMOS 트랜지스터가 형성될 선택된 영역 각각에 게이트 산화막(13), 폴리실리콘막(14)을 형성한 후 패터닝 하여 게이트 전극(15 및 16)을 형성한다.Referring to FIG. 1, after forming the device isolation layer 12 on the semiconductor substrate 11 by a local oxide of silicon (LOCOS) or trench process, an n-well ( Well) region I and p-well region II are formed. Thereafter, the gate oxide film 13 and the polysilicon film 14 are formed in each of the selected regions where the PMOS and NMOS transistors are to be formed, and then patterned to form the gate electrodes 15 and 16.

이때, p형 게이트 전극(15)는 소오스/드레인 접합부를 형성하기 위한 불순물 이온 주입 공정으로 도핑을 시킬 수 있다. 그러나, n형 게이트 전극(16)은 소오스/드레인 접합부를 형성하기 위한 알제닉(As) 이온 주입 공정만으로 충분한 도핑을 할 수 없기 때문에 게이트 전극 패터닝 전에 P31를 이용한 NMOS 트랜지스터가 형성될 지역에 이온 주입 공정을 실시한다.In this case, the p-type gate electrode 15 may be doped by an impurity ion implantation process for forming a source / drain junction. However, since the n-type gate electrode 16 cannot be sufficiently doped only by an Alzenic (As) ion implantation process for forming a source / drain junction, P is not formed before the gate electrode patterning.31Using An ion implantation process is performed in the region where the NMOS transistor is to be formed.

그러나, 게이트 전극 패터닝 전에 실시하는 이온 주입공정은 게이트 전극 패터닝 시 이온공정에 의한 손상 및 과도한 도핑 농도에 의해 도 1에 도시된 n형 게이트 전극(16)과 같은 변형된 식각 프로필을 형성하게 되는 원인이 된다. 그 결과 NMOS 트랜지스터의 퍼포먼스(Performance) 변화가 PMOS 트랜지스터에 비교해 커지게 되는 문제점이 발생된다.However, the ion implantation process performed before the gate electrode patterning causes the deformed etching profile such as the n-type gate electrode 16 shown in FIG. 1 due to the damage caused by the ion process and excessive doping concentration during the gate electrode patterning. Becomes As a result, a problem arises in that the performance change of the NMOS transistor becomes larger than that of the PMOS transistor.

따라서, 종래 게이트 패터닝 시 이온주입공정에 의한 손상 및 과도한 도핑 농도에 의한 변형된 식각 프로필을 개선하기 위하여 본 발명은 게으트 전극 패터닝 전 이온 주입공정을 하지 않고, 과도한 도프트 PSG를 이용하여 선택적으로 n형 게이트 도핑하여 추후 게이트 식각공정시 프로필을 개선 시킬 수 있는 반도체 소자 형성방법을 제공하는데 그 목적이 있다.Accordingly, the present invention does not perform the ion implantation process before the gate electrode patterning, and selectively uses excessive doping PSG to improve the damage profile caused by the ion implantation process and the modified etching profile due to the excessive doping concentration. An object of the present invention is to provide a method for forming a semiconductor device which can improve a profile during a gate etching process by n-type gate doping.

상기한 목적을 달성하기 위한 본 발명은 반도체 기판 상에 소자 분리막을 형성한 후 상기 반도체 기판 내에 서로 다른 불순물을 주입하여 n 형 및 P 웰 영역을 형성하는 단계와, 전체 상부면에 게이트 산화막, 폴리실리콘막 및 과도한 도프트 PSG막을 순차적으로 형성한 후 상기 p웰 영역 상부에만 상기 과도한 도프트 PSG막이 형성되도록 마스크 및 식각 공정을 실시하는 단계와, 열공정을 실시하여 과도한 도프트 PSG막을 확산시킨 후 n웰 영역 및 p웰 영역 상부면 각각에 언도프 게이트 전극 및 n형 도프트 게이트 전극이 형성되도록 패터닝하는 단계를 포함하여 이루어진 것을 특징으로 한다.The present invention for achieving the above object is formed by forming a device isolation film on a semiconductor substrate and implanting different impurities in the semiconductor substrate to form n-type and P well region, the gate oxide film, poly on the entire upper surface After the silicon film and the excessive doped PSG film are sequentially formed, a mask and an etching process are performed to form the excessive doped PSG film only on the p well region, and a thermal process is performed to diffuse the excessive doped PSG film. and patterning the undoped gate electrode and the n-type doped gate electrode to be formed on the upper surfaces of the n well region and the p well region, respectively.

도 1는 종래 반도체 소자 형성방법을 설명하기 위한 소자의 단면도.1 is a cross-sectional view of a device for explaining a method of forming a conventional semiconductor device.

도 2a 내지 도 2d는 본 발명에 따른 반도체 소자 형성방법을 설명하기 위한 소자의 단면도.2A to 2D are cross-sectional views of devices for explaining a method of forming a semiconductor device in accordance with the present invention.

〈도면의 주요 부분에 대한 부호 설명〉<Description of Signs of Major Parts of Drawings>

11 : 반도체기판 12 : 소자 분리막11: semiconductor substrate 12: device isolation film

13 : 게이트 산화막 14 : 폴리실리콘막13 gate oxide film 14 polysilicon film

15 : n형 게이트 전극 16 : p형 게이트 전극15 n-type gate electrode 16 p-type gate electrode

17 : 과도한 도프트 PSG막 18 : 언도프트 게이트 전극17: excessive doped PSG film 18: undoped gate electrode

19 : n형 도프트 게이트 전극19: n-type doped gate electrode

이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2d는 본 발명에 따른 반도체 소자 형성방법을 설명하기 위한 소자의 단면도이다.2A to 2D are cross-sectional views of devices for describing a method of forming a semiconductor device in accordance with the present invention.

도 2a를 참조하면, 반도체 기판(11) 상에 LOCOS(Local Oxidation of Silicon) 또는 트렌치 (Trench)공정으로 소자 분리막(12)을 형성한 후 이온 주입 마스크를 이용한 불순물 이온 주입 공정으로 n-웰(Well)영역(Ⅰ) 및 p-웰 영역(Ⅱ)을 형성한다. 그후 PMOS 및 NMOS 트랜지스터가 형성될 선택된 영역 각각에 게이트 산화막(13), 폴리실리콘막(14)을 형성한다.Referring to FIG. 2A, the device isolation layer 12 is formed on a semiconductor substrate 11 by a local oxide of silicon (LOCOS) or trench process, and then n-well (by an impurity ion implantation process using an ion implantation mask). Well) region I and p-well region II are formed. A gate oxide film 13 and a polysilicon film 14 are then formed in each of the selected regions where the PMOS and NMOS transistors are to be formed.

도 2b는 전체 상부면에 과도한 도프트 PSG막(17)을 300 내지 700Å 두께로 형성한 상태의 단면도이다.FIG. 2B is a cross-sectional view of a state where an excessive doped PSG film 17 is formed to a thickness of 300 to 700 Å on the entire upper surface.

도 2c를 참조하면, p-웰 영역(Ⅱ) 상부에만 과도한 도프트 PSG막(17a)이 형성되도록 마스크 및 식각공정을 실시한 후 800 내지 1000℃ 및 N2가스 분위기에서 25 내지 35 분간 열공정을 실시하여 과도한 도프트 PSG막(17)을 확산 시킨다.Referring to FIG. 2C, a mask and an etching process are performed such that an excessive doped PSG film 17a is formed only on the p-well region (II), followed by a thermal process for 25 to 35 minutes at 800 to 1000 ° C. and an N 2 gas atmosphere. Excessive doped PSG film 17 is diffused.

이때, 폴리실리콘막(14a) 에서의 P31의 확산 정도는 단결정 실리콘에서의 확산 정도 보다 크기 때문에 저온에서도 충분한 도핑이 가능하다. 또한, 상기 과도한 도프트 PSG막(17)은 O3및 TEOS를 이용하여 형성하며 P의 도핑 정도는 5 내지 10 wt% 이다.At this time, since the diffusion degree of P 31 in the polysilicon film 14a is larger than the diffusion degree in single crystal silicon, sufficient doping is possible at low temperatures. In addition, the excessive doped PSG film 17 is formed using O 3 and TEOS and the doping degree of P is 5 to 10 wt%.

도 2d는 게이트 전극이 형성되도록 마스크 및 식각공정을 실시하여 n-웰(Well)영역(Ⅰ) 및 p-웰 영역(Ⅱ) 상부면에 각각에 언도프트 게이트 전극(18) 및 n형 도프트 게이트 전극(19)을 형성한다.FIG. 2D illustrates an undoped gate electrode 18 and an n-type dopant on upper surfaces of the n-well region I and the p-well region II by performing a mask and etching process to form a gate electrode. The gate electrode 19 is formed.

상술한 바와 같이 n형 게이트 전극 패터닝 전에 과도한 도프트 PSG막을 폴리실리콘층 상부면에 형성하여 확산 공정을 실시한다. 그 결과 n형 게이트 전극 식각 공정시 프로필이 개선되고, NMOS 트랜지스터의 퍼포먼스 변화를 억제할 수 있으므로 공정 마진 및 소자의 수율이 증대 되는 효과가 있다.As described above, an excessive doped PSG film is formed on the upper surface of the polysilicon layer before the n-type gate electrode patterning to perform a diffusion process. As a result, the profile is improved during the n-type gate electrode etching process and the performance change of the NMOS transistor can be suppressed, thereby increasing the process margin and the yield of the device.

Claims (3)

반도체 기판 상에 소자 분리막을 형성한 후 상기 반도체 기판 내에 서로 다른 불순물을 주입하여 n 형 및 P 웰 영역을 형성하는 단계와,Forming an isolation layer on the semiconductor substrate and implanting different impurities into the semiconductor substrate to form n-type and P well regions; 전체 상부면에 게이트 산화막, 폴리실리콘막 및 과도한 도프트 PSG막을 순차적으로 형성한 후 상기 p웰 영역 상부에만 상기 과도한 도프트 PSG막이 형성되도록 마스크 및 식각 공정을 실시하는 단계와,Sequentially forming a gate oxide film, a polysilicon film, and an excessive doped PSG film on the entire upper surface, and then performing a mask and etching process so that the excessive doped PSG film is formed only on the p well region; 열공정을 실시하여 과도한 도프트 PSG막을 확산시킨 후 n웰 영역 및 p웰 영역 상부면 각각에 언도프 게이트 전극 및 n형 도프트 게이트 전극이 형성되도록 패터닝하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체 소자의 형성 방법.Performing a thermal process to diffuse the excessive doped PSG film and patterning the undoped gate electrode and the n-type doped gate electrode to be formed in the upper surfaces of the n well region and the p well region, respectively. Formation method of the device. 제 1 항에 있어서,The method of claim 1, 상기 과도한 도프트 PSG막의 P의 도핑은 5 내지 10wt% 로 하고, 300 내지 700Å 두께로 형성하는 것을 특징으로 하는 반도체 소자 형성방법.The doping of the excessive doped PSG film P is 5 to 10wt%, the semiconductor device forming method, characterized in that formed to a thickness of 300 to 700Å. 제 1 항에 있어서, 상기 열공정은 N2가스 분위기에서 800 내지 1000℃의 온도로 25 내지 35분간 실시하는 것을 특징으로 하는 반도체 소자의 형성 방법.The method of claim 1, wherein the thermal process is performed at a temperature of 800 to 1000 ° C. for 25 to 35 minutes in an N 2 gas atmosphere.
KR1019990038661A 1999-09-10 1999-09-10 Method of forming a semiconductor device KR20010027084A (en)

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