KR20010026873A - TFT array substrate of TFT-LCD - Google Patents

Abstract

PURPOSE: The thin film transistor array substrate is provided to obtain a high aperture ratio by forming TFT in a vertical structure having three channel regions. CONSTITUTION: The thin film transistor array substrate includes a transparent insulating substrate. Gate lines(32a,32b) and a data line(38) are alternately arranged on the transparent insulating substrate. Pixel electrodes(34) are positioned in pixel regions of a matrix shape in which the gate line and the data line are alternately arranged. A storage line(40) is arranged in an edge of the pixel regions corresponding to the data line for applying signals to corresponding pixel regions, which is parallel to the data line but is alternately arranged with the gate line. Thin film transistors are included in an interface of the gate line and the data line. A pair of the gate lines for receiving the same scan select signals are provided at one side and other side of one pixel region, and also has homes(T1,T2) within its inside toward corresponding pixel regions. The pixel region has projections(34a,34b) positioned within the home at each of portions neighboring to the pair of gate lines. The thin film transistors are provided on the projection of the pixel electrodes. A pair of thin film transistors are a vertical structure having three channel regions(A,B,C) and simultaneously drive corresponding pixel electrodes.

Description

TFT array substrate of TFT LCDs

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor liquid crystal display device (hereinafter referred to as TFT-LCD). More specifically, a thin film comprising a pair of gate lines and a pair of thin film transistors in one pixel. It relates to a transistor array substrate.

TFT-LCDs used in display devices such as televisions and graphic displays have been developed in place of cathode ray tubes. In particular, since TFT-LCDs having TFTs for each pixel arranged in a matrix form have advantages in that they have high-speed response characteristics and are suitable for high pixel numbers, the display screen comparable to that of a cathode ray tube can be improved in quality, size, and color. It can be realized.

Such a TFT-LCD has a structure in which a TFT array substrate on which a TFT and a pixel electrode are formed, and a color filter substrate on which a color filter and a counter electrode are formed are bonded together through a liquid crystal layer.

FIG. 1 is a cross-sectional view of a TFT array substrate according to the prior art, and as shown, a gate line including a gate electrode 2 is formed on a glass substrate 1, and the gate electrode 2 is formed. The gate insulating film 3 is coated on the entire surface of the glass substrate 1 so as to cover. A semiconductor layer 4 is formed on a portion of the gate insulating film 3 above the gate electrode 2, an ohmic layer 5 is formed on the semiconductor layer 4, and a source / drain electrode is formed on the ohmic layer 5. 6a and 6b are formed to constitute a TFT. In this case, the source / drain electrodes 6a and 6b are formed together when the data line (not shown) disposed perpendicularly to and intersected with the gate line. Subsequently, a pixel electrode 7 made of ITO metal is formed on a portion of the gate insulating film 3 corresponding to the pixel region, and the pixel electrode 7 is in contact with the source electrode 6a.

However, the conventional TFT array substrate as described above has a problem in that the aperture ratio decreases because the TFT occupies a large area in the pixel area, and also due to the low mobility of the amorphous silicon layer, which is a material of the semiconductor layer, it is difficult to manufacture a large screen TFT-LCD. There is difficulty.

On the other hand, as shown in Patent No. 98-61867, "Thin Film Transistor Liquid Crystal Display Device," filed November 23, 1998, with reference to FIGS. It is possible to obtain high mobility while using a silicon layer as a material of the semiconductor layer, and in the case of a TFT array substrate provided with such a TFT, the aperture ratio can be improved by reducing the area of the TFT.

2 is a plan view illustrating a unit cell of a TFT array substrate having a TFT having a vertical structure, FIG. 3 is a cross-sectional view taken along line III-III ′ of FIG. 2, and FIG. 4 is IV- of FIG. 2. It is sectional drawing cut along the IV 'line. Further, reference numeral 10 denotes a glass substrate, 12 gate line, 12a gate electrode, 14 data line, 14a drain electrode, 16 pixel electrode, 17a and 17b ohmic layer, 18 semiconductor layer, 19 gate insulating film , 20 is a storage line, and A, B and C represent channel regions.

However, in the TFT array substrate provided with the TFT of the vertical structure, in spite of the above advantages, there is no particular security against the problem of damage to the gate line and the TFT.

That is, in the large-screen TFT-LCD, more pixels are obtained due to the smaller pixel size. In this case, since the defective rate increases due to the characteristics of the manufacturing process, the repair process increases accordingly. In addition, since the high frequency driving is performed in the large-screen TFT-LCD, the refresh time must be secured.

By the way, the method of forming the TFT in the vertical structure can improve the characteristics of the TFT itself, but when damage is caused to the gate line and the TFT, reliability of the pixel driving cannot be guaranteed, and at the same time, There is a problem that the repair process for damage is difficult.

Accordingly, the present invention devised to solve the above problems, the gate line is formed in a double structure, and by providing two TFTs of each vertical structure for each pixel, the repair process for defects is easily performed. The present invention provides a TFT array substrate which can be used.

1 is a cross-sectional view showing a thin film transistor array substrate according to the prior art.

2 is a plan view illustrating a unit cell of a thin film transistor array substrate having a thin film transistor having a conventional vertical structure.

3 is a cross-sectional view taken along the line III-III ′ of FIG. 2.

4 is a cross-sectional view taken along the line IV-IV ′ of FIG. 2.

5 is a plan view illustrating a unit cell of a thin film transistor array substrate according to an exemplary embodiment of the present invention.

6A to 6D are plan views for each process for explaining a method of manufacturing a thin film transistor array substrate according to an embodiment of the present invention.

FIG. 7 is a cross-sectional view taken along the line VII-VII 'of FIG. 5. FIG.

8 is a plan view illustrating a thin film transistor array substrate according to an embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

31: glass substrate 32a, 32b: gate line

33 gate insulating film 34 pixel electrode

34a: protrusion 35: semiconductor layer

37a: first ohmic layer 37b: second ohmic layer

38: data line 38a: signal electrode

40: storage line 50a, 50b: thin film transistor

A, B, C: Channel area T1, T2: Groove

In order to achieve the above object, the TFT array substrate of the present invention includes a transparent insulating substrate; Gate lines and data lines intersecting and arranged on the transparent insulating substrate; A pixel electrode disposed in each of pixel regions in a matrix form in which the gate line and the data line are crossed and arranged; A storage line parallel to the data line but intersecting and arranged at the edge of the pixel region corresponding to the data line applying a signal to the pixel region; And a thin film transistor provided at an intersection of the gate line and the data line, wherein the gate line includes a pair for receiving the same scan selection signal on one side and the other side of one pixel area, respectively. Grooves are provided on facing inner surfaces, and the pixel electrode is provided with protrusions disposed in the grooves at portions adjacent to the pair of gate lines, and the thin film transistors are provided on the protrusions of the pixel electrode. The pair of thin film transistors have a vertical structure having three channel regions, and the pixel electrodes are operated at the same time.

According to the present invention, since the gate line is formed in a double structure and two TFTs are provided for one pixel, even when damage occurs to the gate line and the TFT, the repair process can be easily performed. have.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 5 is a plan view illustrating a unit cell of a TFT array substrate according to an exemplary embodiment of the present invention.

As shown, a pair of gate lines 32a and 32b are spaced apart from each other, and each of the gate lines 32a and 32b is provided with recesses T1 and T2 in an inner portion facing the pixel region. . The data line 38 is provided to intersect and arrange the gate lines 32a and 32b. A pixel electrode 34 made of an ITO metal film is disposed in the pixel region defined by the pair of gate lines 32a and 32b and the data line 38, wherein the pixel electrode 34 is Protrusions 34a and 34b are provided in recesses T1 and T2 provided in the pair of gate lines 32a and 32b, respectively.

On the edge portion of the pixel electrode 34 corresponding to the data line 38, the storage line 40 is parallel to the data line 38 but intersects and arranges the pair of gate lines 32a and 32b. ) Is provided.

At the intersection of the pair of gate lines 32a and 32b and the data line 38, a pair of TFTs 50a and 50b for simultaneously operating a corresponding pixel electrode is provided. TFTs 50a and 50b are formed in recesses T1 and T2 of the gate lines 32a and 32b, respectively. Further, the TFTs 50a and 50b will be described later in detail, but have a vertical structure and are formed in the recesses T1 and T2 to have three channel regions A, B and C.

6A to 6D are plan views of respective processes for explaining a method of manufacturing a TFT array substrate having the above structure, which will be described below.

First, as shown in FIG. 6A, a pair of gate lines 32a having grooves T1 and T2 provided at inner portions of the transparent insulating substrate, for example, a glass substrate (not shown), facing the corresponding pixel region. 32b).

Then, as illustrated in FIG. 6B, the pixel electrode 34 is formed in the pixel region defined by the pair of gate lines 32a and 32b, and the pixel electrode 34 is the pair of gate lines. And protrusions 34a and 34b disposed in the recesses T1 and T2 provided in the pair of gate lines 32a and 32b, respectively.

Next, although not shown, a gate insulating film is coated on the entire surface of the glass substrate so as to cover the gate lines 32a and 32b and the pixel electrode 34, and an etching process is performed on the gate insulating film to form the pixel. The protrusions 34a and 34b of the electrode 34 are exposed.

Next, as shown in FIG. 6C, the first ohmic layer (not shown), the semiconductor layer (not shown), and the second ohmic layer 37b are disposed on the protrusions 34a and 34b of the exposed pixel electrode 34, respectively. ) To form a lamination pattern.

Then, as illustrated in FIG. 6D, the data line 38 intersecting and arranged with the pair of gate lines 32a and 32b is formed, and at the same time, the pixel electrode 34 spaced apart from the data line to the maximum. A storage line 40 is formed on an edge portion of the storage line 40 parallel to the data line 38 but intersected and arranged with the pair of gate lines 32a and 32b. In addition, when the data line 38 is formed, the signal electrode 38a drawn out from the data line 38 is formed, and the signal electrode 38a is disposed on the second ohmic layer 37b. Thus, a pair of TFTs 50a and 50b for simultaneously operating the corresponding pixel electrodes 34 in one pixel is formed.

FIG. 7 is a cross-sectional view of a vertical TFT formed by cutting along the line VIII-VIII of FIG. 5. As illustrated, the vertical TFT 50b includes a gate line 32b having a recess T2. The first ohmic layer 37a, the semiconductor layer 35, and the second ohmic layer 37b formed on the protrusion 34b of the pixel electrode disposed in the recess T2, and the protrusion 34b of the pixel electrode. A gate insulating film 33 for insulating a stacked pattern between the stacked pattern and the gate line 32b, and a signal electrode 38a of a data line formed on the second ohmic layer 37b and the gate insulating film 33 It includes. Unexplained reference numeral 31 is a glass substrate.

Here, the projection 34b of the pixel electrode performs a function as a direct signal electrode without being in contact with the signal electrode 38a of the data line, unlike the general TFT structure. The thickness of the gate line 32b is equal to, or thicker than, the sum of the thicknesses of the first and second ohmic layers 37a and 37b and the semiconductor layer 35, and the gate insulating layer 33 is formed of a semiconductor layer ( In 35, the channel regions B and C have a thickness enough to be induced.

FIG. 8 is a plan view illustrating a TFT array substrate according to an exemplary embodiment of the present invention. As illustrated, pixel regions arranged in a matrix form have a pair of gate lines 32a and 32b to which the same scan selection signal is input. And intersect and arrange with the pair of gate lines 32a and 32b, and are divided by adjacent data lines 40 to which different drive signals are input. Accordingly, two gate lines 32a and 32b are disposed between adjacent pixel regions, where one gate line 32a supplies a scan selection signal to a corresponding pixel and another gate line 32b. Supplies a scan selection signal to a neighboring pixel region.

Subsequently, the pixel electrode 34 is disposed in the pixel region defined by the pair of gate lines 32a and 32b and the data line 38, and the storage line 40 is arranged at the maximum of the corresponding data line 38. It is disposed parallel to the data line 38 on the edge portion of the pixel electrode 34 spaced apart from each other.

The vertical TFTs 50a and 50b having three channel regions are provided at the intersections of the pair of gate lines 32a and 32b and the data line 38, respectively. 50b operates the corresponding pixel electrode 34 simultaneously.

The TFT array substrate according to the embodiment of the present invention having the above structure has the following advantages.

First, since the TFT has three channel regions, high mobility can be ensured, and in particular, since the size thereof can be reduced, an improvement in aperture ratio can be obtained. In addition, since the gate line and the TFT are provided in duplicate, when a defect occurs in any one of the gate line and the TFT, the pixel can be driven through the remaining gate line and the TFT, so that the repair of the gate line and the TFT is performed. Can be done simply. In addition, since two gate lines disposed between neighboring pixel regions, and a data line and a storage line can be used as a black matrix, the image quality improvement of the TFT-LCD can be obtained.

As described above, the present invention can obtain a high opening ratio by forming the TFT in a vertical structure having three channel regions.

In addition, by forming the gate lines and the TFTs in duplicate, the repair process for the gate lines and the TFTs can be easily performed, thereby improving the production yield of the TFT array substrate.

In addition, the gate lines, data lines, and storage lines can be used as black matrices, thereby improving image quality and reducing cell spacing as much as possible, resulting in more cells. , High quality and large screen TFT-LCD can be realized.

Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.

Claims (3)

Transparent insulating substrates; Gate lines and data lines intersecting and arranged on the transparent insulating substrate; A pixel electrode disposed in each of pixel regions in a matrix form in which the gate line and the data line are crossed and arranged; A storage line parallel to the data line but intersecting and arranged at the edge of the pixel region corresponding to the data line applying a signal to the pixel region; A thin film transistor provided at an intersection of the gate line and the data line, The gate line has a pair for receiving the same scan selection signal on one side and the other side for one pixel area, and grooves are provided on the inner side facing the pixel area, respectively. The pixel electrode includes protrusions disposed in the grooves at portions adjacent to the pair of gate lines, And the thin film transistors are provided on the protrusions of the pixel electrodes, and the pair of thin film transistors have a vertical structure having three channel regions, and the pixel electrodes are operated simultaneously. The thin film transistor of claim 1, wherein the vertical thin film transistor includes: A gate line having a recess, a protrusion of a pixel electrode disposed in the recess of the gate line, a lamination pattern of a first ohmic layer, a semiconductor layer, and a second ohmic layer formed on the protrusion, and the lamination pattern and the gate line And a gate insulating film to insulate and a signal electrode of a data line disposed on the second ohmic layer. The thin film transistor array substrate of claim 2, wherein the gate line is equal to or thicker than a thickness of a stacked pattern of the first ohmic layer, the semiconductor layer, and the second ohmic layer.