CN116594234A - Array substrate, display panel and display device - Google Patents
Array substrate, display panel and display device Download PDFInfo
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- CN116594234A CN116594234A CN202310637203.0A CN202310637203A CN116594234A CN 116594234 A CN116594234 A CN 116594234A CN 202310637203 A CN202310637203 A CN 202310637203A CN 116594234 A CN116594234 A CN 116594234A
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Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136213—Storage capacitors associated with the pixel electrode
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
Abstract
The application discloses an array substrate, a display panel and a display device, wherein the array substrate comprises: a substrate and a plurality of pixel units located above the substrate. Each pixel unit comprises a thin film transistor and a pixel electrode; the pixel electrode is positioned at one side of the thin film transistor, which is away from the substrate; a passivation insulating layer is arranged between the pixel electrode and the thin film transistor, and the pixel electrode is electrically connected with the drain electrode of the thin film transistor through a via hole penetrating through the passivation insulating layer. The array substrate further comprises a common electrode wire, and the common electrode wire is positioned at one side of the drain electrode, which is away from the pixel electrode; a portion of the common electrode line overlapping the pixel electrode forms a storage capacitor; the orthographic projection of the via hole on the substrate and the orthographic projection of the common electrode wire on the substrate are not overlapped, so that the short circuit between the drain electrode and the common electrode wire can be avoided, and the probability of poor dotted line is reduced.
Description
Technical Field
The present application relates to the field of display technologies, and in particular, to an array substrate, a display panel, and a display device.
Background
The liquid crystal display (Liquid Crystal Display, abbreviated as LCD) panel includes an array substrate, a color film substrate, and a liquid crystal layer disposed between the array substrate and the color film substrate. The array substrate comprises a thin film transistor and a pixel electrode positioned above the thin film transistor; the thin film transistor includes a gate electrode, a source electrode, a drain electrode, and an active layer, wherein the drain electrode is separated from the pixel electrode by a passivation insulating layer, and the drain electrode is connected to the pixel electrode by a via hole in the passivation insulating layer. When displaying an image, an image signal voltage is input to the pixel electrode through the drain electrode, and an electric field for deflecting liquid crystal molecules in the liquid crystal layer is formed between the array substrate and the color film substrate, thereby displaying an image.
In an image display process, in order for the pixel electrode to maintain an image signal voltage for one frame period, a storage capacitor (Storage Capacitor, abbreviated as CS) needs to be formed in the array substrate to maintain the image signal voltage of the pixel electrode. At present, a scheme for forming a storage capacitor based on a common electrode line and a pixel electrode exists, in some schemes, in order to improve the storage capacitor, the common electrode line is arranged on one side of a drain electrode, which is away from the pixel electrode, and the orthographic projection of the drain electrode on an array substrate is positioned in the orthographic projection of the common electrode line on the array substrate, so that the occurrence rate of the problem of bad dotted line is high.
Disclosure of Invention
The application provides an array substrate, a display panel and a display device, which are used for reducing the occurrence probability of dotted line defects.
In a first aspect of the present application, there is provided an array substrate comprising:
a substrate base;
a plurality of pixel units located on the substrate; each pixel unit comprises a thin film transistor and a pixel electrode; the pixel electrode is positioned at one side of the thin film transistor, which is away from the substrate; a passivation insulating layer is arranged between the pixel electrode and the thin film transistor, and the pixel electrode is electrically connected with the drain electrode of the thin film transistor through a via hole penetrating through the passivation insulating layer;
a common electrode line at one side of the drain electrode facing away from the pixel electrode; a portion of the common electrode line overlapping the pixel electrode forms a storage capacitor; the orthographic projection of the via hole on the substrate base plate is not overlapped with the orthographic projection of the common electrode line on the substrate base plate.
In the array substrate provided by the application, the orthographic projection of the drain electrode on the substrate is not overlapped with the orthographic projection of the common electrode wire on the array substrate.
The array substrate provided by the application further comprises data lines and grid lines which are crossed transversely and longitudinally; the grid line is connected with the grid electrode, and the data line is connected with the source electrode;
the grid lines and the data lines are arranged in a surrounding mode to form a plurality of pixel areas which are arrayed, and the pixel electrodes are positioned in the pixel areas;
the common electrode line is positioned in each pixel area and extends along the direction parallel to the periphery of the pixel electrode; the orthographic projection of the common electrode line on the substrate is at least partially coincident with the orthographic projection of the pixel electrode on the substrate.
In the array substrate provided by the application, the orthographic projection of the data line on the substrate is not overlapped with the orthographic projection of the common electrode line on the substrate, and the orthographic projection of the grid line on the substrate is not overlapped with the orthographic projection of the common electrode line on the substrate.
In the array substrate provided by the application, the common electrode line comprises a first part extending along a direction parallel to the data line; the width of the first portion is greater than the width of the data line.
In the array substrate provided by the application, the width of the first part is 5.0-5.5 mu m; the width of the data line is 4.50 mu m-5.0 mu m; the width of the overlapping area of the orthographic projection of the pixel electrode on the substrate and the orthographic projection of the first portion on the substrate is 3.25 μm to 3.75 μm.
In the array substrate provided by the application, the common electrode wires positioned at two sides of the data wire are electrically connected through the connecting wires.
In the array substrate provided by the application, the distance between the orthographic projection of the via hole on the substrate and the orthographic projection of the common electrode wire on the substrate is larger than 5 mu m.
In the array substrate provided by the application, the common electrode wire and the grid electrode are arranged on the same layer and are mutually spaced from each other.
The second aspect of the present application also provides a display panel, including the array substrate, the opposite substrate, and the liquid crystal layer between the array substrate and the opposite substrate; the opposite substrate further includes a common electrode layer for forming a deflection electric field with the pixel electrode.
In a third aspect of the present application, there is also provided a display device comprising the display panel of any one of the above.
The application has the following beneficial effects:
the application provides an array substrate, a display panel and a display device, wherein the array substrate comprises a substrate and a plurality of pixel units positioned on the substrate. Each pixel unit comprises a thin film transistor and a pixel electrode; the pixel electrode is positioned at one side of the thin film transistor, which is away from the substrate; a passivation insulating layer is arranged between the pixel electrode and the thin film transistor, and the pixel electrode is electrically connected with the drain electrode of the thin film transistor through a via hole penetrating through the passivation insulating layer. The array substrate further comprises a common electrode wire, and the common electrode wire is positioned at one side of the drain electrode, which is away from the pixel electrode; a portion of the common electrode line overlapping the pixel electrode forms a storage capacitor; the orthographic projection of the via hole on the substrate is not overlapped with the orthographic projection of the common electrode wire on the substrate, so that the short circuit between the drain electrode and the common electrode wire can be avoided, and the probability of poor dotted line is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments of the present application will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a top view of an array substrate according to the related art;
FIG. 2 is a cross-sectional view of an array substrate according to the related art;
FIG. 3 is a top view of an array substrate according to an embodiment of the present application;
FIG. 4 is a cross-sectional view of an array substrate according to an embodiment of the present application;
FIG. 5 is a second cross-sectional view of an array substrate according to an embodiment of the present application;
FIG. 6 is a second top view of the array substrate according to the embodiment of the application;
FIG. 7 is a third cross-sectional view of an array substrate according to an embodiment of the present application;
FIG. 8 is a schematic diagram of a portion of an array substrate according to an embodiment of the present application;
FIG. 9 is a partial enlarged view of an embodiment of the present application;
fig. 10 is a signal crosstalk simulation diagram provided in an embodiment of the present application;
FIG. 11 is a third cross-sectional view of an array substrate according to an embodiment of the present application;
fig. 12 is a schematic cross-sectional structure of a display device according to an embodiment of the application.
The display device comprises a 1-substrate, 2-grid lines, 21-grid electrodes, 3-data lines, 31-source electrodes, 32-drain electrodes, K-openings, 4-active layers, 5-common electrode lines, 51-first parts, 52-second parts, 6-pixel electrodes, 7-passivation insulating layers, T-thin film transistors, S-pixel areas, H-through holes, 100-display panels, 110-array substrates, 120-opposite substrates, 130-liquid crystal layers and 200-backlight modules.
Detailed Description
In order that the above objects, features and advantages of the application will be readily understood, a further description of the application will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus a repetitive description thereof will be omitted. The words expressing the positions and directions described in the present application are described by taking the drawings as an example, but can be changed according to the needs, and all the changes are included in the protection scope of the present application. The drawings of the present application are merely schematic representations of relative positional relationships and are not intended to represent true proportions.
FIG. 1 is a top view of an array substrate according to the related art; fig. 2 is a cross-sectional view of an array substrate according to the related art.
The liquid crystal display (Liquid Crystal Display, abbreviated as LCD) panel includes an array substrate, a color film substrate, and a liquid crystal layer disposed between the array substrate and the color film substrate. As shown in fig. 1 and 2, the array substrate includes a thin film transistor T and a pixel electrode 6 located above the thin film transistor T. The thin film transistor includes a gate electrode 21, a source electrode 31, a drain electrode 32, and an active layer 4. Wherein the drain electrode 32 is separated from the pixel electrode 6 by a passivation insulating layer 7, and the drain electrode 32 is connected to the pixel electrode 6 by a via H penetrating the passivation insulating layer 7. In image display, an image signal voltage is input to the pixel electrode 6 through the drain electrode 32, and an electric field for deflecting liquid crystal molecules in the liquid crystal layer is formed between the array substrate and the color film substrate, thereby displaying an image.
In the image display process, in order for the pixel electrode 6 to hold the image signal voltage for one frame period, a storage capacitor (Storage Capacitor, abbreviated as CS) needs to be formed in the array substrate to hold the image signal voltage of the pixel electrode. Currently, there are schemes for forming a storage capacitance based on a common electrode line and a pixel electrode.
For example, as shown in fig. 1 and 2, in the related art, in order to increase the storage capacitance, a common electrode line 5 is disposed on a side of the drain electrode 32 facing away from the pixel electrode 6, and a portion of the common electrode line 5 overlapping the pixel electrode 6 forms the storage capacitance. In addition, since the drain electrode of the thin film transistor is made of a light-tight material, such as gold, silver, chromium or titanium, the common electrode line 5 is also disposed under the drain electrode 32, so as to further increase the storage capacitance without reducing the aperture ratio of the pixel. However, after the scheme is adopted, the occurrence rate of the problem of poor dotted line is high, so that dark points or dark lines appear on a display picture, and the display effect is affected.
The present application, based on a great number of experiments and analyses, found that the main reason for the occurrence of the defect of the dotted line in the above-mentioned scheme is that, when the common electrode line 5 is manufactured, a foreign matter (paint) is easily introduced into the film layer of the common electrode line 5, resulting in uneven surface of the common electrode line 5. At the position where the foreign matter exists, the surface of the common electrode line 5 protrudes to one side of the drain electrode 32, so that when the insulating layer between the common electrode line 5 and the drain electrode 32 is deposited and the drain electrode 32 is manufactured, the thickness of the insulating layer and the drain electrode 32 is thinner, and when the passivation insulating layer 7 is etched later to manufacture a via hole H for connecting the pixel electrode 6 and the drain electrode 32, if the via hole H just overlaps with the position where the foreign matter exists, the drain electrode 32 and the insulating layer are easily perforated, and finally after the pixel electrode 6 is deposited, the drain electrode 32 and the common electrode line 5 are shorted, resulting in poor dotted line. The occurrence rate of the defect of the dotted line in the related technology is about 3% -6%, which causes great economic loss.
In view of the above, the embodiments of the present application provide an array substrate, which can solve the above-mentioned problems.
FIG. 3 is a top view of an array substrate according to an embodiment of the present application; FIG. 4 is a cross-sectional view of an array substrate according to an embodiment of the present application; FIG. 5 is a second cross-sectional view of an array substrate according to an embodiment of the present application.
In an embodiment of the present application, as shown in fig. 3 to 5, an array substrate includes: a substrate 1, a plurality of pixel cells, and a common electrode line 5.
The substrate 1 is located at the bottom of the array substrate and is used for carrying each film layer on the array substrate. The shape of the substrate 1 is adapted to the shape of the array substrate, and may be square, rectangular, circular, or the like in practical implementation, which is not limited herein. The substrate 1 may be made of a transparent material, and specifically may be glass, resin, or the like, and is not limited thereto.
A plurality of pixel units are located on the substrate 1, each pixel unit including a thin film transistor T and a pixel electrode 6. The thin film transistor T serves as a drive switch, and an image signal voltage is input to the pixel electrode 6, and the pixel electrode 6 is used to form an electric field for deflecting liquid crystal molecules in the liquid crystal layer, thereby displaying an image.
The thin film transistor T is located between the pixel electrode 6 and the substrate 1, and includes a gate electrode, an active layer, a source electrode, and a drain electrode. As shown in fig. 4, the gate electrode 21 is located between the active layer 4 and the substrate 1, and the orthographic projection of the gate electrode 21 on the substrate 1 at least partially overlaps with the orthographic projection of the active layer 4 on the substrate. The source electrode 31 and the drain electrode 32 are located on both sides of the active layer 4, respectively, and are electrically connected to the active layer 4, and a conductive channel is formed between the source electrode 31 and the drain electrode 32 by applying a voltage to the gate electrode 21, so that the thin film transistor T can be turned on. In particular, as shown in fig. 4, the source electrode 31 may have a "U" structure, and the drain electrode 32 is partially located in a groove of the "U" structure, so that a channel length may be increased, a gate control capability may be improved, and the source electrode 31 may have other shapes, which is not limited herein.
A passivation insulating layer 7 is further provided between the pixel electrode 6 and the thin film transistor T. The passivation insulating layer 7 may serve as insulation and planarization. In particular, the passivation insulating layer 7 may be made of a material such as silicon oxide, silicon nitride, silicon oxynitride, or transparent resin, and is not limited thereto. As shown in fig. 4, the pixel electrode 6 and the drain electrode 32 of the thin film transistor T are electrically connected through a via hole H penetrating the passivation insulating layer 7.
The common electrode line 5 is located at a side of the drain electrode 32 facing away from the pixel electrode 6. There is at least a partial overlap region of the common electrode line 5 and the pixel electrode 6. The portion of the common electrode line 5 overlapping the pixel electrode 6 forms a storage capacitance.
In the embodiment of the present application, as shown in fig. 4, the orthographic projection of the via H on the substrate 1 does not overlap with the orthographic projection of the common electrode line 5 on the substrate. In specific implementation, as shown in fig. 4, an insulating layer is further disposed between the drain electrode 32 and the common electrode line 5, and the orthographic projection of the via hole H on the substrate 1 and the orthographic projection of the common electrode line 5 on the substrate are not overlapped, so that the insulating layer and the drain electrode 32 can be prevented from being thinner due to the existence of foreign matters in the common electrode line 5 directly under the via hole H, and the short circuit between the drain electrode 32 and the common electrode line 5 caused by perforation of the insulating layer and the drain electrode 32 can be avoided when the passivation insulating layer 7 is etched, thereby reducing the probability of bad dotted line.
In some embodiments, as shown in fig. 4, the spacing D between the orthographic projection of the via H on the substrate 1 and the orthographic projection of the common electrode line 5 on the substrate 1 is greater than 5 μm. In practical implementation, since the size of the foreign matter introduced during the fabrication of the common electrode line 5 is generally about 5 μm, the distance D between the orthographic projection of the via hole H on the substrate 1 and the orthographic projection of the common electrode line 5 on the substrate 1 is larger than 5 μm, and thus, the defect of the dotted line caused by the foreign matter introduced by the common electrode line 5 can be avoided.
In particular, as shown in fig. 5, in the process of etching the passivation insulating layer 7 to form the via hole H, since the side of the passivation insulating layer 7 away from the substrate 1 is etched first, the passivation insulating layer 7 is etched after being close to the side of the substrate 1, and the opening size of the finally formed via hole H is gradually reduced from the side away from the substrate 1 to the side close to the substrate 1, in this embodiment, the distance D between the front projection of the via hole H on the substrate 1 and the front projection of the common electrode line 5 on the substrate 1 may be specifically the distance between the front projection of the bottom of the via hole H on the substrate 1 and the front projection of the common electrode line 5 on the substrate 1.
In some embodiments, as shown in fig. 3-4, the orthographic projection of the drain electrode 32 on the substrate base plate 1 and the orthographic projection of the common electrode line 5 on the substrate base plate 1 have a partial overlap region. In the specific implementation, as shown in fig. 3 to 4, a common electrode line 5 is disposed below the drain electrode 32, an opening K is formed in the common electrode line 5, the orthographic projection of the via hole H on the substrate 1 is located within the orthographic projection of the opening K on the substrate 1, and in the area outside the opening K, the orthographic projection of the drain electrode 32 on the substrate 1 overlaps with the orthographic projection of the common electrode line 5 on the substrate 1, so that the size of the storage capacitor can be increased by using the overlapping area.
FIG. 6 is a second top view of the array substrate according to the embodiment of the application; FIG. 7 is a third cross-sectional view of an array substrate according to an embodiment of the present application; fig. 8 is a schematic partial view of an array substrate according to an embodiment of the present application.
In some embodiments, as shown in fig. 6 and fig. 7, the orthographic projection of the drain electrode 32 on the substrate 1 and the orthographic projection of the common electrode line 5 on the array substrate 1 are not overlapped, so that the influence of the foreign matters introduced during the manufacture of the common electrode line 5 on the thickness of the drain electrode 32 can be avoided to the greatest extent, and the problem of short circuit between the drain electrode 32 and the common electrode line 5 is avoided.
As shown in fig. 8, in a normal case, the length of the drain electrode 32 in the horizontal direction v is about 20 μm, and in a vertical direction h is about 25 μm, and when the common electrode line 5 is manufactured, an opening having a length of 20 μm to 25 μm in the horizontal direction v and a length of about 25 μm to 30 μm in the vertical direction h may be opened to the common electrode line 5 below the drain electrode 32. In practice, the size of the opening of the common electrode line 5 may be determined according to the actual size of the drain electrode 32, which is not limited herein.
In the embodiment of the present application, as shown in fig. 3 and 6, the array substrate further includes a data line 3 and a gate line 2 that cross horizontally and vertically. The gate line 2 is connected to the gate electrode 21 for applying a gate control voltage to the gate electrode 21 to turn on between the source electrode 31 and the drain electrode 32, and the data line 3 is connected to the source electrode 31 for inputting an image signal voltage to the thin film transistor T and inputting a pixel electrode through the drain electrode 32.
In particular, the gate line 2 and the gate electrode 21 may be formed in the same layer and simultaneously, and the data line 3 and the source electrode 31 may be formed in the same layer and simultaneously, which is not limited herein.
The gate lines 2 and the data lines 3 are surrounded by a plurality of pixel regions S arranged in an array, and the pixel electrodes 6 are located in each pixel region S. The common electrode line 5 is located in each pixel region and extends in a direction parallel to the periphery of the pixel electrode 6 to form a ring-shaped structure.
In some embodiments, as shown in fig. 3 and 6, the common electrode line 5 includes a first portion 51 extending in a direction parallel to the data line 3 and a second portion 52 perpendicular to the first portion 51, and around the periphery of the pixel electrode 6, an orthographic projection of an edge of the pixel electrode 6 on the substrate 1 is at least partially overlapped with an orthographic projection of the first portion 51 on the substrate 1 and an orthographic projection of the second portion 52 on the substrate 1. In practical implementation, the orthographic projection of the common electrode line 5 on the substrate 1 may fall completely into the orthographic projection of the pixel electrode 6 on the substrate 1, and a larger storage capacitance is provided between the common electrode line 5 and the pixel electrode 6. The orthographic projection of the common electrode line 5 on the substrate 1 may be partially located outside the orthographic projection of the pixel electrode 6 on the substrate 1, which is limited by the process accuracy and the aperture ratio, and is not limited herein.
In some embodiments, as shown in fig. 3 and 6, the orthographic projection of the data line 3 on the substrate 1 is not overlapped with the orthographic projection of the common electrode line 5 on the substrate 1 and the orthographic projection of the pixel electrode 6 on the substrate 1, and the orthographic projection of the gate line 2 on the substrate 1 is not overlapped with the orthographic projection of the common electrode line 5 on the substrate 1 and the orthographic projection of the pixel electrode 6 on the substrate 1. In specific implementation, it is necessary to ensure that a certain distance is kept between the data line 3 and the common electrode line 5 and the pixel electrode 6, and between the gate line 2 and the common electrode line 5 and the pixel electrode 6, so as to avoid disturbance to the storage capacitance between the common electrode line 5 and the pixel electrode 6 when the signal voltage is input to the gate line 2 and the data line 3, and avoid flicker.
FIG. 9 is a partial enlarged view of an embodiment of the present application; fig. 10 is a signal crosstalk simulation diagram according to an embodiment of the present application.
In the embodiment shown in fig. 6 to 7, since the orthographic projection of the drain electrode 32 on the substrate 1 and the orthographic projection of the common electrode line 5 on the array substrate 1 do not overlap, the overlapping area between the pixel electrode 6 and the common electrode 5 becomes smaller, and the storage capacitance formed between the pixel electrode 6 and the common electrode 5 becomes smaller. In some embodiments, the first portion 51 of the pixel electrode 6 and the common electrode 5 may be simultaneously flared toward a side close to the data line 3 to increase an area of an overlapping region between the orthographic projection of the pixel electrode 6 on the substrate 1 and the orthographic projection of the common electrode 5 on the substrate 1, compensating for a decrease in storage capacitance due to a decrease in the area of the common electrode line 5 under the drain electrode 32.
For example, as shown in fig. 9, in the related art, the width W of the first portion 51 of the common electrode line 5 is on both sides of the data line 3 1 Typically about 4.5 μm, the width W of the data line 3 2 Typically around 5.5 μm, the width of the overlapping area of the orthographic projection of the first portion 51 of the common electrode line 5 on the substrate base plate 1 and the orthographic projection of the data line 3 on the substrate base plate 1 is W, the value of W being dependent on the process accuracy. In the embodiment of the present application, the width of the first portion 51 of the common electrode line 5 may be expanded to 0.5 μm to 1 μm toward the data line 3 side, and the expanded width W of the first portion 51 of the common electrode line 5 11 The width of the overlapping region of the orthographic projection of the first portion 51 of the common electrode line 5 on the substrate 1 and the orthographic projection of the data line 3 on the substrate 1 becomes W' with an increase of 0.5 μm to 1 μm, which ranges from 3.25 μm to 3.75 μm, compared to W, thereby ensuring that the size of the storage capacitor satisfies the demand. In the embodiment of the application, the common electrode line 5 and the pixel electrode 6 are simultaneously outwards expanded towards the side close to the data line 3, so that the reduction of the pixel aperture opening ratio can be avoided while the storage capacitance is increased.
The common electrode line 5 and the pixel electrode 6 are expanded and simultaneously the data line 3 is contracted, as shown in fig. 9, the data line 3 is contracted by 0.5 μm to 1 μm correspondingly, and the width W of the data line 3 is contracted 22 4.5 μm to 5.0 μm to ensure a sufficient distance between the pixel electrode 6 and the data line 3 to avoid signal crosstalk. In practical implementation, after the common electrode line 5 and the pixel electrode 6 are expanded and the data line 3 is contracted, it is necessary to ensure that the distance between the orthographic projection of the pixel electrode 6 on the substrate 1 and the orthographic projection of the data line 3 on the substrate 1 is greater than 4.05 μm to avoid signal crosstalk. As shown in fig. 10, the abscissa represents the actual distance between the orthographic projection of the pixel electrode 6 on the substrate 1 and the orthographic projection of the data line 3 on the substrate 1The ordinate represents the value of (Cpd-Cpd ')/CST compared to the offset of the design distance, where Cpd represents the coupling capacitance generated when the pixel electrode 6 and the data line 3 are at the design distance, cpd' represents the coupling capacitance change caused by the distance deviation between the pixel electrode 6 and the data line 3 compared to the design distance, and CST represents the storage capacitance. The embodiment of the application simulates the signal crosstalk situation after the common electrode line 5 and the pixel electrode 6 are expanded by 1 mu m and the data line 3 is contracted by 1 mu m, wherein the coincidence ratio of the simulation curve (a dotted line in the figure) of the embodiment of the application and the standard sample curve (a solid line in the figure) obtained by simulating the signal crosstalk of a mass production product is higher, the error is in the range of 0.1 percent, the risk of the signal crosstalk is smaller, and the mass production requirement is met.
In the embodiment of the present application, as shown in fig. 9, after the data line 3 is contracted while the common electrode line 5 and the pixel electrode 6 are expanded, the width of the first portion 51 of the common electrode line 5 is larger than the width of the data line 3. Wherein the width direction of the first portion 51 and the width direction of the data line 3 are perpendicular to the extending direction of the first portion 51.
In some embodiments, the common electrode line 5 may be also inwardly expanded toward the inside of the pixel region S to increase the area of the overlapping region between the pixel electrode 6 and the common electrode 5, compensating for a decrease in storage capacitance due to a decrease in the area of the common electrode line 5 under the drain electrode 32. For example, in the related art, the width W of the common electrode line 5 1 Usually about 4.5 μm, the width of the data line 3 and the size of the pixel electrode 6 can be kept unchanged in the embodiment of the application, and the width W of the common electrode line 5 can be reduced 1 The width of the overlapping region of the common electrode line 5 and the data line 3 is increased by enlarging the pixel region S by 0.5 μm to 1 μm, thereby increasing the storage capacitance. The inner expansion mode can avoid changing the width of the data line 3 and the size of the pixel electrode 6, and ensures the process stability.
In forming a display panel, in order to prevent the metal wires in the array substrate from reflecting external light and affecting the display effect, the data lines 3, the gate lines 2, the common electrode lines 5, etc. in the array substrate are usually shielded by the black matrix in the opposite substrate. In the concrete implementation, whenWidth W of common electrode line 5 1 After expanding toward the inside of the pixel region S, it is correspondingly necessary to expand the area of the black matrix in the opposite substrate so that the orthographic projection of the black matrix on the array substrate covers the expanded common electrode lines 5, avoiding reflected light.
In some embodiments, as shown in fig. 3 and 6, the common electrode lines 5 located at both sides of the data line 3 are electrically connected through connection lines, so that a common voltage difference can be prevented from being generated between two adjacent pixel regions S at both sides of the data line 3, uniformity of the common voltage is improved, and flicker is prevented. In particular, the common electrode line 5 and the connection trace may be formed simultaneously by a patterning process, which is not limited herein.
In some embodiments, the common electrode lines 5 located at both sides of the data line 3 may not be connected, which is not limited herein.
In some embodiments, as shown in fig. 4 and 7, the common electrode line 5 and the gate electrode 2 are disposed in different film layers. In particular, as shown in fig. 4, the common electrode line 5 may be disposed between the film layer where the gate electrode 2 is located and the film layer where the drain electrode 32 is located, and the common electrode line 5 and the gate electrode 2, and the common electrode line 5 and the drain electrode 32 are separated by an insulating layer, respectively. The common electrode wires 5 and the grid electrodes 2 are arranged in different film layers, so that the distance between the common electrode wires 5 and the grid electrodes 2 can be increased, the risk of signal crosstalk is reduced, and the difficulty in circuit design of the film layer where the grid electrodes 2 are arranged can be reduced.
FIG. 11 is a third cross-sectional view of an array substrate according to an embodiment of the present application.
In some embodiments, as shown in fig. 11, the common electrode line 5 is disposed in the same layer as the gate electrode 2 and is spaced apart from the gate electrode 2. In specific implementation, the common electrode line 5 and the gate electrode 2 can be formed in the same film layer simultaneously through a patterning process, so as to reduce the thickness of the array substrate and simplify the manufacturing process.
According to the array substrate provided by the embodiment of the application, the orthographic projection of the drain electrode 32 on the substrate 1 is not overlapped with the orthographic projection of the common electrode wire 5 on the array substrate 1, and the common electrode wire 5 and the pixel electrode 6 are subjected to outward expansion processing, and the data wire 3 is subjected to inward contraction processing, so that the occurrence probability of poor dotted line can be reduced to 0%, the size of storage capacitance formed by the common electrode wire 5 and the pixel electrode 6 can be ensured, and signal crosstalk between the common electrode wire 5 and the data wire 3 can be avoided.
Fig. 12 is a schematic cross-sectional structure of a display device according to an embodiment of the application.
The embodiment of the application also provides a display panel.
The display panel provided by the embodiment of the application can be a liquid crystal display panel. Specifically, a Twisted Nematic (TN) liquid crystal display panel may be used. As shown in fig. 12, the liquid crystal display panel includes the array substrate 110, the opposite substrate 120, and the liquid crystal layer 130 disposed between the array substrate 110 and the opposite substrate 120 according to any of the above embodiments. The opposite substrate 120 further includes a common electrode layer for forming a deflection electric field with the pixel electrode in the array substrate 110 to drive the liquid crystal molecules in the liquid crystal layer 130 to deflect, thereby performing image display.
In specific implementation, the display panel may be another type of display panel, which is not limited herein.
The display panel provided by the embodiment of the application comprises the array substrate provided by any one of the embodiments, and has the same technical effects as the array substrate provided by any one of the embodiments when being implemented, and the description is omitted herein.
The embodiment of the application also provides a display device. The display device provided by the embodiment of the application comprises the display panel provided by any one of the embodiments.
Specifically, as shown in fig. 12, when the display panel is a liquid crystal display panel, the display device further includes a backlight module 200. The display panel 100 is located at the light emitting side of the backlight module 200, and is configured to receive light emitted from the backlight module 200 and modulate the incident light to display an image.
In specific implementation, the display device may be another display device, which is not limited herein. The display device provided by the embodiment of the present application includes the display panel provided by any one of the above embodiments, and has the same technical effects as the display panel provided by any one of the above embodiments when in implementation, and will not be described herein.
While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (11)
1. An array substrate, characterized by comprising:
a substrate base;
a plurality of pixel units located on the substrate; each pixel unit comprises a thin film transistor and a pixel electrode; the pixel electrode is positioned at one side of the thin film transistor, which is away from the substrate base plate; a passivation insulating layer is arranged between the pixel electrode and the thin film transistor, and the pixel electrode is electrically connected with the drain electrode of the thin film transistor through a via hole penetrating through the passivation insulating layer;
a common electrode line on a side of the drain electrode facing away from the pixel electrode; a portion of the common electrode line overlapping the pixel electrode forms a storage capacitor; the orthographic projection of the via hole on the substrate base plate is not overlapped with the orthographic projection of the common electrode wire on the substrate base plate.
2. The array substrate of claim 1, wherein an orthographic projection of the drain electrode on the substrate does not overlap with an orthographic projection of the common electrode line on the array substrate.
3. The array substrate of claim 2, further comprising data lines and gate lines crossing each other horizontally and vertically; the grid line is connected with the grid electrode, and the data line is connected with the source electrode;
the grid lines and the data lines are arranged in a surrounding mode to form a plurality of pixel areas which are arrayed, and the pixel electrodes are located in the pixel areas;
the common electrode lines are positioned in each pixel region and extend along the direction parallel to the periphery of the pixel electrodes; the orthographic projection of the common electrode line on the substrate is at least partially overlapped with the orthographic projection of the pixel electrode on the substrate.
4. The array substrate of claim 3, wherein the orthographic projection of the data lines on the substrate does not overlap with the orthographic projection of the common electrode lines on the substrate, and the orthographic projection of the gate lines on the substrate does not overlap with the orthographic projection of the common electrode lines on the substrate.
5. The array substrate of claim 4, wherein the common electrode line includes a first portion extending in a direction parallel to the data line; the width of the first portion is greater than the width of the data line.
6. The array substrate of claim 5, wherein the first portion has a width of 5.0 μm to 5.5 μm; the width of the data line is 4.50-5.0 mu m; the width of the overlapping area of the orthographic projection of the pixel electrode on the substrate and the orthographic projection of the first part on the substrate is 3.25-3.75 μm.
7. The array substrate of claim 3, wherein the common electrode lines located at both sides of the data line are electrically connected by connection lines.
8. The array substrate of any one of claims 1 to 7, wherein a spacing between an orthographic projection of the via on the substrate and an orthographic projection of the common electrode line on the substrate is greater than 5 μm.
9. The array substrate of any one of claims 1 to 7, wherein the common electrode line is disposed in the same layer as the gate electrode and is spaced apart from the gate electrode.
10. A display panel comprising the array substrate according to any one of claims 1 to 8, a counter substrate, and a liquid crystal layer between the array substrate and the counter substrate; the opposite substrate further includes a common electrode layer for forming a deflection electric field with the pixel electrode.
11. A display device comprising the display panel according to claim 9.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310637203.0A CN116594234A (en) | 2023-05-31 | 2023-05-31 | Array substrate, display panel and display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310637203.0A CN116594234A (en) | 2023-05-31 | 2023-05-31 | Array substrate, display panel and display device |
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| CN116594234A true CN116594234A (en) | 2023-08-15 |
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| CN202310637203.0A Pending CN116594234A (en) | 2023-05-31 | 2023-05-31 | Array substrate, display panel and display device |
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