KR20010019685A - Multi-chip package - Google Patents

Abstract

PURPOSE: A multi-chip package is provided to prevent a metal wire from being changed in the multi-chip package, by using a TAB lead instead of the metal wire regarding at least one of stacked semiconductor chips. CONSTITUTION: The first semiconductor chip has the first active surface(122) and the first rear surface(123). The semiconductor chip has the second active surface(132) and the second rear surface(133), located on the first semiconductor chip. At least the second semiconductor chip is adhered to a lead frame(117) which electrically connects the first and second semiconductor chips with an external apparatus. A TAB lead(142) is adhered to the first active surface of the first semiconductor chip, electrically connecting the first semiconductor and the lead frame. A unit for connection electrically connects the second semiconductor chip with the lead frame.

Description

Multi-chip package

The present invention relates to a multi-chip package, and more particularly, to a multi-chip package using Tape Automated Bonding (TAB) to reduce defects caused by a multi-chip packaging process.

Recently, in accordance with the development of the electronic industry and the needs of users, electronic components are required to be more compact and lighter. One of the technologies mainly applied to this is a multi-chip packaging technology in which a plurality of semiconductor chips are configured in one package. Multi-chip packages have been widely used for reducing and reducing the mounting area, especially in portable telephones that require miniaturization and light weight.

When a flash memory and a synchronous RAM (SRAM) chip, which performs memory functions, are configured into one thin small outline package (TSOP), the size and weight of each semiconductor chip package is higher than that of using two unit semiconductor chip packages. And compactness and weight reduction in the mounting area. In general, a method of configuring a plurality of semiconductor chips in one package includes a method of stacking semiconductor chips vertically and horizontally and parallelly arranging them.

In the former case, since the semiconductor chips are stacked up and down, the process is complicated and it is difficult to secure a stable process at a limited thickness. In the latter case, since the semiconductor chips are arranged on the same plane, the mounting area is reduced. It is difficult to obtain the advantages of miniaturization. Therefore, as a form applied to a package requiring miniaturization and light weight, many forms of stacking semiconductor chips up and down are used.

1 is a cross-sectional view showing a multi-chip package according to the prior art.

Referring to FIG. 1, the multi-chip package 10 includes a lead frame composed of a die pad 12, an inner lead 14, and an outer lead 16, and each of the active surfaces 22 and 32 are in contact with each other. The first and second semiconductor chips 20, 30 are bonded to the top and bottom surfaces of the die pad 12 by non-conductive adhesives 28, 38, as shown in the figure, facing in the opposite direction. The active surfaces 22 and 32 are surfaces of the semiconductor chips 20 and 30 on which circuit elements (not shown) including the bonding pads 24 and 34 are formed.

The bonding pads 24 and 34 of the first and second semiconductor chips 20 and 30 are electrically connected to the corresponding internal leads 14 by metal wires 26 and 36. The package body 18 is formed of a molding resin to protect the electrical connection portions including the semiconductor chips 20 and 30 from the outside. In the conventional multichip package 10, the active surfaces 22 and 32 of the semiconductor chips 20 and 30 are mounted in opposite directions with respect to the die pad 12.

Therefore, a die bonding process of adhering the semiconductor chips 20 and 30 to the die pad 12 and a wire bonding process of connecting the metal wires 26 and 36 are performed for each semiconductor chip 20 and 30. Should be carried out separately. Therefore, the first semiconductor chip 20 is adhered to the upper surface of the die pad 12, the metal wires 26 are connected to each other, and the lead frame is turned over to the second semiconductor chip 30 attached to the lower surface of the die pad 12. When wire bonding is performed, the metal wire 26 of the first semiconductor chip 20 may be deformed to cause defects.

As described above, the multi-chip package 10 having the structure in which the semiconductor chips 20 and 30 are attached to the upper and lower surfaces of the die pad 12 of the lead frame, respectively, has a metal line from above and below the lead frame. 26, 36), the electrical connection must be made, the process is complicated and the failure rate is high.

Therefore, an object of the present invention is to prevent the deformation of the metal wire generated in the wire bonding process.

Another object of the present invention is to simplify the process of stacking semiconductor chips, thereby reducing the manufacturing time and manufacturing cost of the multi-chip package.

1 is a cross-sectional view showing a multi-chip package according to the prior art,

2 is a cross-sectional view showing a multi-chip package according to a first embodiment of the present invention;

3 is a cross-sectional view showing a multi-chip package according to a second embodiment of the present invention;

4 is a cross-sectional view showing a multi-chip package according to a third embodiment of the present invention;

5 is a cross-sectional view illustrating a multichip package according to a fourth exemplary embodiment of the present invention.

<Description of Major Symbols in Drawing>

10, 100, 200, 300, 400; Multi-chip package

12, 312; Die pads 14, 114, 314; Inside lead

16, 116, 316; Outer leads 18, 118, 318; Package body

20, 30, 120, 130, 320, 330; Semiconductor chip

22, 32, 122, 132, 322, 332; Active cotton

24, 34, 124, 324; Bonding pads 26, 36, 126, 326; Metal wire

28, 38, 128, 328, 338; Adhesive 117, 317; Leadframe

123, 133, 323, 333; Rear 140, 340; Bump

142, 342; TAB lead

In order to achieve the above object, the present invention provides a semiconductor device comprising: (1) a first semiconductor chip having a first active surface and a first back surface, and (2) a first semiconductor chip positioned on the first semiconductor chip and having a second active surface and a second back surface. 2 semiconductor chips, (3) at least a second semiconductor chip, and a lead frame for electrically connecting the first semiconductor chip and the second semiconductor chip to an external device, and (4) bonding to the first active surface of the first semiconductor chip. And a TAB lead for electrically connecting the first semiconductor chip and the lead frame, and (5) connecting means for electrically connecting the second semiconductor chip and the lead frame.

In the present invention, in order to prevent the metal wire from being deformed at the time of wire bonding, the metal wire is removed by applying the TAB technique to at least one of the stacked semiconductor chips. The TAB tape is formed of a thin metal thin film on the insulating tape, whereby a TAB lead is formed, and a semiconductor chip is attached to one end of the TAB lead and electrically connected thereto. In general, bumps are formed on the bonding pads formed on the active surface of the semiconductor chip to easily bond with the TAB leads.

Hereinafter, a multi-chip package according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. Like numbers refer to like elements throughout.

2 is a cross-sectional view illustrating a multichip package according to a first embodiment of the present invention.

Referring to FIG. 2, the semiconductor chip 120 positioned above the stacked semiconductor chips 120 and 130 is bonded to the lead frame 117 in the form of a lead-on-chip (LOC). The semiconductor chip 130 positioned below is bonded to the TAB lead 142 of the TAB tape (not shown) by the TAB technology to form the multi chip package 100. The upper semiconductor chip 120 extends the inner lead 114 of the lead frame 117 over the active surface 122 to be bonded to the active surface 122.

Since the upper semiconductor chip 120 and the lower semiconductor chip 130 are bonded to the back surfaces 123 and 133, which are opposite surfaces of the active surfaces 122 and 132, by the non-conductive adhesive 128, the lower semiconductor chip 130 may be The active surface 132 is directed downwards. The upper semiconductor chip 120 is electrically connected to the bonding pad 124 and the inner lead 114 by the metal wire 126, and the lower semiconductor chip 130 is the corresponding inner lead by the TAB lead 142. Connected with 114.

The lower semiconductor chip 130 and the TAB lead 142 are preferably bonded by the bumps 140. When the electrical connection is completed between the semiconductor chips 120 and 130 and the internal lead 114, the package body 118 is formed of a molding resin to protect the semiconductor chips 120 and 130 and the electrical connection portion from the outside. The outer lead 116 protrudes out of the package body 118 to allow the multi chip package 100 to be connected to an external device (not shown).

3 is a cross-sectional view illustrating a multichip package according to a second exemplary embodiment of the present invention.

Referring to FIG. 3, the multichip package 200 is the same as the multichip package of FIG. 2 except for the semiconductor chip 130 below. In the lower semiconductor chip 130, the active surface 132 faces upward, similar to the upper semiconductor chip 120. Accordingly, the back surface 123 of the upper semiconductor chip 120 and the TAB lead 142 are bonded by the nonconductive adhesive 128.

4 is a cross-sectional view illustrating a multichip package according to a third exemplary embodiment of the present invention.

Referring to FIG. 4, the semiconductor chips 320 and 330 may include a general lead frame 317, that is, a die pad of a lead frame 317 including a die pad 312, an inner lead 314, and an outer lead 316. 312). The rear surface 323 of the semiconductor chip 320 positioned on the upper portion is bonded to the upper surface of the die pad 312, and the rear surface 333 of the lower semiconductor chip 330 is attached to the lower surface of the die pad 312. Accordingly, the active surface 322 of the upper semiconductor chip 320 faces upward, and the active surface 332 of the lower semiconductor chip 320 faces downward.

The bonding pad 324 of the upper semiconductor chip 320 is electrically connected to the inner lead 314 by the metal wire 326, and the lower semiconductor chip 330 is connected to the inner lead 314 by the TAB lead 342. Connected. The lower semiconductor chip 330 and the TAB lead 342 are preferably bonded by the bump 340. When the electrical connection is completed between the semiconductor chips 320 and 330 and the inner lead 314, the package body 318 is formed of a molding resin to protect the semiconductor chips 320 and 330 and the electrical connection portion from the outside.

The outer lead 316 protrudes out of the package body 318 to enable the multi chip package 300 to be connected to an external device (not shown). At least one of the adhesives 328, 338 that adheres the semiconductor chips 320, 330 to the die pad 312 should be nonconductive.

5 is a cross-sectional view illustrating a multichip package according to a fourth exemplary embodiment of the present invention.

Referring to FIG. 5, the multichip package 400 is the same as the multichip package of FIG. 3 except for the semiconductor chip 130 below. In the lower semiconductor chip 330, the active surface 332 faces upward, similar to the upper semiconductor chip 320. Therefore, the TAB lead 342 bonded to the lower semiconductor chip 330 is bonded to the lower surface of the die pad 312.

Although the present invention has been described with reference to specific embodiments, it is not limited to the above-described embodiments. In particular, two or more semiconductor chips may be included in one package body in terms of the number of semiconductor chips. In addition, the upper semiconductor chip and the inner lead may be connected by the TAB lead similarly to the lower semiconductor chip without using a metal wire.

Therefore, according to the present invention, the deformation of the metal wire generated in the multi-chip package can be prevented by using the TAB lead instead of the metal wire for at least one of the stacked semiconductor chips.

In addition, according to the present invention, the multi-chip package manufacturing process can be simplified by using the TAB technology.

Claims (6)

In a multi-chip package, (1) a first semiconductor chip having a first active surface and a first back surface, (2) a second semiconductor chip located above the first semiconductor chip and having a second active surface and a second back surface; (3) a lead frame to which at least the second semiconductor chip is bonded, and electrically connecting the first semiconductor chip and the second semiconductor chip to an external device; (4) a TAB lead attached to the first active surface of the first semiconductor chip to electrically connect the first semiconductor chip and the lead frame; And (5) connecting means for electrically connecting said second semiconductor chip and said leadframe. The multi-chip package of claim 1, wherein the multi-chip package has a LOC type in which an inner lead of the lead frame extends and adheres to the second active surface of the second semiconductor chip, wherein the first semiconductor chip has the first active surface. The second semiconductor chip faces upward and the second active surface faces upward, and a non-conductive adhesive is interposed between the first semiconductor chip and the second semiconductor chip so that the first back surface of the first semiconductor chip And wherein said second backside of said second semiconductor chip is adhered by said nonconductive adhesive. The first chip of claim 1, wherein the multi-chip package has a LOC type in which an inner lead of the lead frame extends and is bonded to the second active surface of the second semiconductor chip. And the TAB lead attached to the first semiconductor chip with the non-conductive adhesive interposed between the first semiconductor chip and the second semiconductor chip with the second active surface of the second semiconductor chip facing upward. And said second backside of said semiconductor chip is bonded by said nonconductive adhesive. The multi-chip package according to claim 1, wherein the connection means for electrically connecting the second semiconductor chip and the lead frame is a metal wire. The lead frame of claim 1, wherein the lead frame includes a die pad, and the second back surface of the second semiconductor chip is adhered to an upper surface of the die pad of the lead frame, and the lower surface of the lead pad is attached to the die pad. And the first rear surface of the first semiconductor chip is bonded. The lead frame of claim 1, wherein the lead frame includes a die pad, and the second back surface of the second semiconductor chip is adhered to an upper surface of the die pad of the lead frame, and the lower surface of the lead pad is attached to the die pad. Multi-chip package characterized in that the TAB lead is bonded.