KR20010019578A - Method for forming capacitor - Google Patents

Abstract

PURPOSE: A method for manufacturing a capacitor is provided to effectively form an opening which has a uniform width from an upper portion to a lower portion of the opening, by using a multilayered insulating layer instead of a single insulating layer when the opening for forming a storage electrode is formed. CONSTITUTION: The second insulating layer(210) is deposited on the first insulating layer(208) in which a contact plug(204) is formed. A multilayered insulating layer is deposited on the second insulating layer in an order of an etch rate of the insulating layers. The multilayered insulating layer is etched to form an opening(216) through a photolithography process.

Description

Capacitor Formation Method {METHOD FOR FORMING CAPACITOR}

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a capacitor.

The most widely used product in the semiconductor field, particularly in the memory field, is Dynamic Random Access Memory (DRAM). A DRAM has a cell composed of one transistor and one capacitor as one information unit. Thus, how to increase the capacity of the memory depends on how much of the manufacturing technology to integrate the cells. The technical challenge of high integration and high capacity of semiconductor memories is to reduce the size of transistors and capacitors as components and to reduce the isolation region between cells. The cell area of the initial DRAM, 16Kb DRAM, has a planar structure of 500µm ² , and the cell size of the recent 64Mb DRAM has been reduced to 1.3-2.0µm ² to one third. In contrast, the area of the capacitor, which is a constituent of the cell, is reduced by only one- ^third from 150µm ² for 16Kb DRAM to 4-6µm ² for 64Mb DRAM.

The reason why the area of the capacitor cannot be reduced in proportion to the shrinking of the cell is related to the characteristics of the capacitor. Due to problems such as soft errors and noise, there is a minimum required capacitance for storing information in DRAM. At least 25fF of capacitance is required for DRAM to store information. Capacitance is proportional to the dielectric constant of the dielectric between the electrodes and the electrode area. Therefore, no matter how small the cell area, there is a limit to reducing the area of the capacitor.

In order to achieve high capacity and high integration of memory, a technology for securing sufficient capacitance in a small area is required. As a method of increasing capacitance, there is a method of developing a material having a high dielectric constant and increasing an electrode surface area.

Commonly used dielectric materials are SiO ₂ (dielectric constant ε = 3.9) and Si ₃ N ₄ (ε = 7.0). High dielectric materials include TiO ₂ (ε = 70-80), Ta ₂ O ₅ (ε = 24-26), ZrO ₂ (ε = 15-20), SrTiO ₃ (ε = 200-300) and BST (ε = 300-500). However, the larger the dielectric constant, the larger the leakage current, so there are still problems in applying it to an actual process. However, attempts have recently been made using BST.

The most widely used method of increasing the surface area of an electrode is a stack structure, a cylinder structure of which is used a lot. However, a large step is formed as the stack height is increased to increase the surface area of the electrode. These steps make it difficult to proceed with subsequent processes. In addition, undesired problems occur during etching and deposition due to the high aspect ratio in forming the cylinder structure.

1 is a cross-sectional view showing a problem of a conventional cylindrical capacitor forming method.

Referring to FIG. 1, a general cylindrical capacitor forming method is illustrated. A silicon nitride film 106 as an etch stop film is deposited on the interlayer insulating film 102 on which the contact plug 104 is formed. An insulating film 108 is deposited on the silicon nitride film 106. An opening is formed by etching the insulating layer 108 to expose the contact plug 104 through a photolithography process. Subsequently, when the opening inner wall is deposited with a conductive film and the insulating film is removed, a storage node of the capacitor is formed.

However, when the opening is formed, as shown in FIG. 1, the width decreases toward the lower side. For this reason, the capacitance does not increase even if the height of the capacitor is increased to some extent. This phenomenon is remarkable when the height is about 1000 nm or more. Therefore, there is a possibility that the bottom width is narrow and the contact failure and the bottom electrode fall down.

The present invention has been proposed to solve the above-mentioned problems, and an object of the present invention is to provide a method for forming a capacitor, the width of which is kept constant during etching of an insulating film for forming a lower electrode of the capacitor.

1 is a cross-sectional view showing a problem of a conventional capacitor forming method.

2A and 2B are cross-sectional views illustrating a method of forming a capacitor according to an embodiment of the present invention.

3 is a cross-sectional view illustrating a method of forming a capacitor according to another embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

202, 302: insulating film 204, 304: contact plug

206 and 306 silicon nitride film 208 and 308 first insulating film

210, 310: second insulating film 212: third insulating film

214: fourth insulating film 216, 316: opening

According to the present invention for achieving the above object, the capacitor forming method deposits a second insulating film on the first insulating film formed with a contact plug. The insulating layer is deposited in multiple layers on the second insulating layer in order of increasing etch rate to form a multilayer insulating layer. The multilayer insulating film is etched through a photolithography process to form an opening. The opening inner wall is deposited by a conductive film. The multilayer insulating film is removed.

(Example)

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 2 and 3.

In the novel capacitor forming method of the present invention, since the insulating films having different etch rates are stacked in multiple layers in the insulating film deposition process for forming the lower electrode of the capacitor, a vertically straight shape is formed during the opening formation.

2A through 2B are cross-sectional views illustrating a method of forming a capacitor according to an embodiment of the present invention.

Referring to FIG. 2A, a contact plug 204 is formed in the interlayer insulating film 202. The interlayer insulating layer 202 may be formed of BPSG (Boron Phosphorus Silicte Glass), HDP (High Density Plasma) oxide film, USG (Undoped Silicate Glass), or the like. A silicon nitride film 206 is deposited on the contact plug 204 and the interlayer insulating film 202. The silicon nitride film 206 serves as an etch stopping layer.

The first insulating film 208, the second insulating film 210, the third insulating film 212, and the fourth insulating film 214 are sequentially stacked on the silicon nitride film 206 to form a multilayer insulating film 208-214. The first, second, third and fourth insulating layers 208, 210, 212, and 214 are formed of BPSG, USG, SiON, SiO ₂ , PSG, HDP oxide, or the like. The thickness of the fourth insulating layer 214 should be thicker than the sum of the thicknesses of the first, second and third insulating layers 208, 210, and 212. The reason is that the height of the multilayer insulating film is about 1000 nm, but in the case of the conventional single insulating film, the opening is formed while maintaining the vertical from the top to the bottom about 600 nm, and the width is narrowed down in the lower region so that the width is narrow. This is because only a part is replaced by a material having high etching rate. The multilayer insulating films 208-214 have the largest etch rate in the order of the fourth, third, second, and first insulating films 214, 212, 210, and 208.

Referring to FIG. 2B, a photoresist film (not shown) is deposited on the fourth insulating film 214. The photoresist film is patterned. The photoresist layer pattern is used as a mask, and the fourth, third, second, and first insulating layers 214, 212, 210, and 208 are anisotropic dry etched. The multilayer insulating films 208-214 are quickly etched in the vertical direction by the anisotropic dry etching. However, even in this case, the conventional problem remains as it is, and the lower width thereof is narrowly etched like the dotted line 218. Thus, an isotropic wet etching process is further performed. Since each of the insulating layers of the multilayer insulating layers 208-214 has different wet selectivity, the lower the lower the etching rate is, the better the etching becomes. Compensating for the vertical opening 216 is formed.

3 is a cross-sectional view showing an embodiment applicable to those skilled in the art through the spirit of the present invention.

A silicon nitride film 306 is deposited on the interlayer insulating film 302 on which the contact plug 304 is formed. A first insulating film 308 and a second insulating film 310 are deposited on the silicon nitride film 306. The first insulating layer 308 has a higher etching rate than the second insulating layer 310. The openings 312 may be formed by anisotropic dry etching of the second and first insulating layers 310 and 308 using an opening forming mask. Then, since the isotropic wet etching process is further performed, the first insulating layer 308 is further etched as shown in FIG. 3. Thus, the lower width of the opening 312 is sufficiently widened.

In the drawing, the first insulating film 308 is rather etched more than the second insulating film 310 to cause an under cut phenomenon. This undercut causes a breakdown voltage change but can be adjusted to a conventional level through the process of forming the lower electrode of the subsequent capacitor. In addition, the undercut increases the area of the opening 312 and is easily used to increase the area of the subsequent lower electrode.

According to the present invention, since the multilayer insulating film is used instead of the single insulating film when forming the capacitor lower electrode forming opening, the width of the opening can be etched from the top to the bottom of the opening.

Claims (3)

Depositing a second insulating film on the first insulating film on which the contact plug is formed: Depositing an insulating film in multiple layers on the second insulating film in an order of increasing etch rate; And forming an opening by etching the multilayer insulating film through a photolithography process. The method of claim 1, And wherein the multilayer insulating film has a larger thickness of the insulating film deposited on the uppermost layer than the thickness of the insulating film deposited on the remaining lower portion. The method of claim 1, The etching step may be performed by first performing dry etching to form an opening to expose the contact plug; And performing a wet etch after the opening is formed.