KR20010018841A - Mold flash intercepting structure for semiconductor package - Google Patents
Mold flash intercepting structure for semiconductor package Download PDFInfo
- Publication number
- KR20010018841A KR20010018841A KR1019990034956A KR19990034956A KR20010018841A KR 20010018841 A KR20010018841 A KR 20010018841A KR 1019990034956 A KR1019990034956 A KR 1019990034956A KR 19990034956 A KR19990034956 A KR 19990034956A KR 20010018841 A KR20010018841 A KR 20010018841A
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor package
- mold flash
- molding
- blocking
- intercepting
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
Abstract
Description
본 발명은 반도체 패키지의 몰드플래시 차단구조에 관한 것으로, 특히 몰딩시 플래시가 아웃리드에 발생되어 후공정에서 도금불량이 발생되는 것을 방지하도록 하는데 적합한 반도체 패키지의 몰드플래시 차단구조에 관한 것이다.The present invention relates to a mold flash blocking structure of a semiconductor package, and more particularly, to a mold flash blocking structure of a semiconductor package suitable for preventing a flash from being generated in an outlead during molding and preventing plating defects in a later process.
종래의 반도체 패키지가 도 1에 도시되어 있는 바, 이를 간단히 설명하면 다음과 같다.A conventional semiconductor package is shown in FIG. 1, which is briefly described as follows.
리드프레임(1)의 패들(2) 상면에 접착제(3)로 반도체 칩(4)이 고정부착되어 있고, 그 반도체 칩(4)의 주변에는 리드프레임(1)의 인너리드(5)가 나열설치되어 있으며, 상기 칩(4)의 상면에 형성된 칩패드(4a)들과 상기 인너리드(5)들은 각각 금속와이어(6)로 몰딩되어 있고, 상기 칩(4), 인너리드(5), 패들(2)의 일정부분을 감싸도록 몰딩부(7)가 형성되어 있으며, 그 몰딩부(7)의 외측으로 상기 인너리드(5)에 연결되는 아웃리드(8)들이 돌출형성되어 있다.The semiconductor chip 4 is fixedly attached to the upper surface of the paddle 2 of the lead frame 1 with an adhesive 3, and the inner lead 5 of the lead frame 1 is arranged around the semiconductor chip 4. The chip pads 4a and the inner leads 5 formed on the upper surface of the chip 4 are molded with metal wires 6, respectively, and the chips 4, inner leads 5, The molding part 7 is formed to surround a portion of the paddle 2, and the outleads 8 connected to the inner lead 5 are protruded to the outside of the molding part 7.
상기와 같이 구성되어 있는 종래 반도체 패키지는 패들(2)의 상면에 접착제(3)로 반도체 칩(4)을 고정부착하는 다이본딩을 실시하고, 그 칩(4)의 칩패드(4a)들과 인너리드(5)들을 금속와이어(6)로 와이어본딩을 실시 하며, 상기 칩(4), 인너리드(5), 패들(2)의 일정부분을 감싸도록 몰딩부(7)를 형성하는 몰딩공정을 실시하고, 그 몰딩부(7)의 외측으로 돌출형성된 아웃리드(8)들을 도금한 다음 트리밍, 포밍작업을 실시하여 패키지를 완성한다.The conventional semiconductor package configured as described above is die-bonded to fix the semiconductor chip 4 with the adhesive 3 on the upper surface of the paddle 2, and the chip pads 4a of the chip 4 A molding process of wire bonding the inner leads 5 to the metal wires 6 and forming a molding part 7 to cover a predetermined portion of the chip 4, the inner lead 5, and the paddle 2. Then, the outleads 8 protruding outward from the molding part 7 are plated, and then trimming and forming are performed to complete the package.
그러나, 상기와 같이 구성되어 있는 종래의 반도체 패키지는 도 2와 같이 몰딩시 아웃리드(8)에 몰드 플래시(9)가 흘러나와서 후공정인 도금공정시 몰드 플래시(9)가 발생된 아웃리드(8) 부분은 도금이되지 못하여 도금불량이 발생되는 문제점이 있었다.However, in the conventional semiconductor package having the above-described structure, as shown in FIG. 2, the mold flash 9 flows out to the outlead 8 during molding so that the mold flash 9 is generated during the post-plating process. 8) There was a problem in that the plating is bad because the portion is not plated.
상기와 같은 문제점을 감안하여 안출한 본 발명의 목적은 몰딩시 몰드 플래시가 아웃리드에 흘러나오는 것을 차단하여 후공정인 도금공정에서 도금불량이 발생되는 것을 방지하도록 하는데 적합한 반도체 패키지의 몰드플래시 차단구조를 제공함에 있다.An object of the present invention devised in view of the above problems is to block the mold flash from flowing out of the mold during molding to prevent the mold flash block structure of the semiconductor package suitable for preventing the occurrence of plating defects in the plating process, which is a post-process In providing.
도 1은 종래 반도체 패키지의 구조를 보이 종단면도.1 is a longitudinal sectional view showing a structure of a conventional semiconductor package.
도 2는 종래 패키지의 아웃리드에 몰드플래시가 발생된 상태를 보인 정면도.2 is a front view showing a state in which a mold flash is generated in the outread of the conventional package.
도 3은 본 발명 몰드플래시 차단구조가 형성된 반도체 패키지의 구조를 보인 사시도.3 is a perspective view showing a structure of a semiconductor package in which the mold flash blocking structure of the present invention is formed.
도 4는 도 3의 A-A'를 절취하여 보인 단면도.4 is a cross-sectional view taken along the line AA ′ of FIG. 3;
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
11c : 아웃리드 16 : 몰딩부11c: Out lead 16: Molding part
20 : 차단홈20: blocking groove
상기와 같은 본 발명의 목적을 달성하기 위하여 몰딩부의 외측으로 아웃리드들이 구비되어 있는 반도체 패키지에 있어서, 상기 아웃리드의 소정부분에 몰딩시 몰딩수지가 흘러나오는 것을 차단하기 위한 차단부를 형성하여서 구성되는 것을 특징으로 하는 반도체 패키지의 몰드플래시 차단구조가 제공된다.In order to achieve the object of the present invention as described above, in the semiconductor package is provided with the outer lead to the outside of the molding portion, formed by forming a blocking portion for blocking the flow of the molding resin during molding in the predetermined portion of the outlead A mold flash blocking structure of a semiconductor package is provided.
이하, 상기와 같이 구성되는 본 발명 반도체 패키지의 몰드플래시 차단구조를 첨부된 도면의 실시예를 참고하여 보다 상세히 설명하면 다음과 같다.Hereinafter, the mold flash blocking structure of the semiconductor package according to the present invention will be described in detail with reference to the accompanying drawings.
도 3은 본 발명 몰드플래시 차단구조가 형성된 반도체 패키지의 구조를 보인 사시도이고, 도 4는 도 3의 A-A'를 절취하여 보인 단면도로서, 도시된 바와 같이, 본 발명 몰드 플래시 차단구조가 형성된 반도체 패키지는 리드프레임(11)의 패들(11a) 상면에 반도체 칩(13)이 접착제(14)로 고정부착되어 있고, 그 반도체 칩(13)의 주변에는 리드프레임(11)의 인너리드(11b)들이 나열설치되어 있으며, 상기 반도체 칩(13)의 칩패드(13a)들과 인너리드(11b)들은 각각 금속와이어(15)들로 연결되어 있고, 상기 칩(13), 패들(11a), 인너리드(11b), 금속와이어(15)의 일정부분을 감싸도록 에폭시 수지로 몰딩부(16)가 형성되어 있으며, 상기 몰딩부(16)의 외측으로는 리드프레임(11)의 인너리드(11b)들에 각각 연결되도록 아웃리드(11c)들이 돌출형성되어 있다.3 is a perspective view illustrating a structure of a semiconductor package in which a mold flash blocking structure of the present invention is formed, and FIG. 4 is a cross-sectional view taken along line AA ′ of FIG. 3. As illustrated, the mold flash blocking structure of the present invention is formed. In the semiconductor package, the semiconductor chip 13 is fixedly attached to the upper surface of the paddle 11a of the lead frame 11 with an adhesive 14, and the inner lead 11b of the lead frame 11 is around the semiconductor chip 13. ), The chip pads 13a and the inner lead 11b of the semiconductor chip 13 are connected to the metal wires 15, respectively, and the chip 13, the paddle 11a, The molding part 16 is formed of an epoxy resin so as to surround a portion of the inner lead 11b and the metal wire 15, and the inner lead 11b of the lead frame 11 is formed outside the molding part 16. The outleads 11c are protruded so as to be connected to the respective ones.
그리고, 상기 아웃리드(11c)와 상기 몰딩부(16)의 경계부에는 몰딩시 수지물이 아웃리드(11c)의 상면으로 흘러나오지 않도록 차단하기 위한 일정깊이의 차단홈(20)이 형성되어 있다.In addition, at the boundary between the outlead 11c and the molding part 16, a blocking groove 20 having a predetermined depth is formed to block the resin material from flowing out to the upper surface of the outlead 11c during molding.
상기와 같은 본 발명의 몰드플래시 차단구조를 갖는 반도체 패키지는 리드프레임(11)의 패들(11a) 상면에 접착제(14)를 이용하여 반도체 칩(13)을 고정부착하고, 그 칩(13)의 칩패드(13a)들과 리드프레임(11)의 인너리드(11b)들을 각각 금속와이어(15)들을 와이어본딩하며, 상기 칩(13), 패들(11a), 금속와이어(15), 인너리드(11b)의 일정부분을 감싸도록 에폭시로 몰딩하게 되는데, 이와 같이 몰딩이 진행될때에 아웃리드(11c)의 상면에 형성된 차단홈(20)에 의하여 몰딩수지가 아웃리드(11c)의 상면으로 흘러나오는 것이 차단된다.In the semiconductor package having the mold flash blocking structure of the present invention as described above, the semiconductor chip 13 is fixedly attached to the upper surface of the paddle 11a of the lead frame 11 by using an adhesive 14, and the chip 13 of the chip 13 Inner leads 11b of the chip pads 13a and the lead frame 11 are wire-bonded to the metal wires 15, respectively, and the chip 13, the paddle 11a, the metal wire 15, and the inner lead ( Molding with epoxy to cover a portion of 11b), the molding resin flows out to the upper surface of the outlead (11c) by the blocking groove 20 formed on the upper surface of the outlead (11c) when the molding proceeds in this way Is blocked.
이상에서 상세히 설명한 바와 같이, 본 발명 반도체 패키지의 몰드플래시 차단구조는 몰딩부의 외측으로 돌출형성되는 아웃리드들의 상면에 몰딩시 수지물이 아웃리드의 상면을 흘러나오는 것을 차단하기 위한 차단홈을 형성하고, 몰딩시 수지물이 아웃리드로 흘러나오는 것을 차단하여, 몰딩공정에서 발생된 몰드플래시에 의하여 후공정인 도금공정에서 도금불량이 발생되는 것을 방지하는 효과가 있다.As described above in detail, the mold flash blocking structure of the semiconductor package of the present invention forms a blocking groove for blocking resin flow out of the upper surface of the outlead when molding on the upper surface of the outlead protruding outward from the molding part. In the molding, the resin material is prevented from flowing out to the outlead, thereby preventing plating defects from occurring in the plating process, which is a post process, by the mold flash generated in the molding process.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990034956A KR20010018841A (en) | 1999-08-23 | 1999-08-23 | Mold flash intercepting structure for semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990034956A KR20010018841A (en) | 1999-08-23 | 1999-08-23 | Mold flash intercepting structure for semiconductor package |
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| Publication Number | Publication Date |
|---|---|
| KR20010018841A true KR20010018841A (en) | 2001-03-15 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990034956A KR20010018841A (en) | 1999-08-23 | 1999-08-23 | Mold flash intercepting structure for semiconductor package |
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| KR (1) | KR20010018841A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010105891A (en) * | 2000-05-19 | 2001-11-29 | 마이클 디. 오브라이언 | Leadframe for semiconductor package |
-
1999
- 1999-08-23 KR KR1019990034956A patent/KR20010018841A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010105891A (en) * | 2000-05-19 | 2001-11-29 | 마이클 디. 오브라이언 | Leadframe for semiconductor package |
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