KR20010016901A - System for driving of an LCD - Google Patents

Abstract

PURPOSE: A system of driving LCD(Liquid Crystal Display) is provided to reduce the harmful effects of electronic waves and noises and thus improve reliability of the display synchronizing the frequency of a horizontal clock signal from the controller with the frequency of data put into a drive IC through de-multiplying. CONSTITUTION: In a system of driving LCD(Liquid Crystal Display), color data and control signals go into a controller(110) and a DC voltage goes into a power supply(120). The power supply(120) provides a source of constant voltage for the controller(110), a gradiation generator(130) and a gate voltage generator(140). The controller(110) sends a source drive part(200) electrically connected to an LCD panel(160) various signals and data to determine grey tone of each pixel. The gradiation generator(130) supplies the source drive part(200) with a gradiation voltage and the gate voltage generator(140) sends a voltage to the gate drive part(150) generating a turn-on/turn-off voltage. The gate and source drive parts(150,200) generate and send a gate signal and a source signal respectively to the LCD panel(160). The LCD panel(160) generates liquid crystal capacitance(Cls) and storage capacitance(Cs) at the drain with the source and drain signals.

Description

System for driving of an LCD

The present invention relates to a drive system for a liquid crystal display device, and more particularly, to divide the frequency of the horizontal clock signal output from the controller at least once to have the same frequency as the data input to the drive IC. It is about.

Liquid crystal display device, a kind of flat panel display device, uses the electrical characteristics of liquid crystal whose light transmittance changes according to the voltage applied to each pixel. It is lighter, thinner, capable of low-voltage driving, and consumes less power than other display devices. It is widely used as a monitor of a desktop computer as well as a computer.

A liquid crystal display device having such characteristics includes an LCD panel displaying an image by means of image signals and light, a printed circuit board transmitting image signals necessary for displaying an image to the LCD panel, a backlight assembly that guides light toward the LCD panel, and their members. And other fixtures for fixing them.

Among these members, the LCD panel and the printed circuit board are electrically connected to a plurality of source and gate drive ICs, and various components such as a controller are mounted on the printed circuit board.

Here, when the source signal generated by the source drive IC and the gate signal generated by the gate drive IC are applied to each pixel of the LCD panel, the gate signal is transmitted through a thin film transistor through a gate line formed in the LCD panel. Is applied to the gate electrode of " TFT ", thereby turning the TFT on or off.

On the other hand, the source signal flowing along the data lines formed in the LCD panel is applied to the pixel electrode only when the TFT is turned on by the gate signal to change the arrangement state of the liquid crystal existing between the pixel electrode and the counter electrode, thereby preventing the transmitted light. Adjust the amount.

As described above, the internal structure of the source drive IC for generating the source signal along with the process of generating the source signal applied to the pixel electrode to change the arrangement of the liquid crystal will be described as follows.

The source drive IC is composed of a shift resist, a digital-to-analog converter, and a buffer. The shift resist is a horizontal clock signal (H_CLK) and a shift signal (STH) divided into two parts of a master clock signal, 6-bit RGB data, and a load signal (TP). Is authorized.

In other words, when a shift signal is input, the shift register receives RGB data simultaneously, reads and shifts each data at the rising point of the horizontal clock signal, and continuously stores the data, and carries it when the data is filled in the first source drive IC. The carry out signal is transmitted to the next source drive IC to repeat the above-described operation.

When the data is filled in the plurality of source drive ICs through this process, the data stored in the shift resist is output to the digital / analog converter by the load signal, and the digital / analog converter converts the data into an analog voltage corresponding to the coating value. To the buffer.

The buffer regulates the output of the analog voltage output from the digital / analog converter and then applies a source signal to the LCD panel.

Here, the frequency of the RGB data is 16.25 MHz, and the frequency of the horizontal clock signal is 32.5 MHz, which is twice the RGB data.

As the high frequency horizontal clock signal is input to the source drive IC and driven at a high frequency, a large amount of electromagnetic waves (EMI) are generated to interfere with the source signal transmitted to the LCD panel, thereby degrading image quality. Since it is emitted to the outside of the liquid crystal display device to cause a malfunction of other devices, there is a problem that the reliability is lowered.

In addition, noise is generated because the horizontal clock signal is not secured enough to set-up time for stabilizing the waveform of the data before latching the data and hold time for maintaining the waveform of the data for a certain period of time after the latching of the data. There was this.

Therefore, an object of the present invention is to divide the frequency of the horizontal clock signal output from the controller to match the frequency of the data input to the drive IC, thereby minimizing the damage of electromagnetic waves and noise to improve the reliability of the product.

Other objects of the present invention will become more apparent from the following detailed description and the accompanying drawings.

1 is a block diagram for explaining the driving of a liquid crystal display device according to the present invention;

2 is a detailed block diagram of a gate drive IC according to the present invention.

3 is a detailed block diagram of a source drive IC according to the present invention;

4 is a logic circuit part according to a first embodiment of the present invention.

Fig. 5 is a timing chart of signals input or output to the logic circuit section of the first embodiment.

6 is a logic circuit part according to a second embodiment of the present invention.

Fig. 7 is a timing chart of signals input to or output from the logic circuit portion of the second embodiment.

8 is a logic circuit part according to a third embodiment of the present invention.

Fig. 9 is a timing chart of signals input or output to the logic circuit section of the third embodiment.

In order to achieve the above object, the present invention generates a horizontal clock signal having a frequency equal to the data in the source drive IC and a horizontal clock signal having a phase difference of 180 ° from the horizontal clock signal to latch data. Adjusts the output of the gradation voltage output from the digital / analog converter and the digital / analog converter, which selects the gradation voltage by encoding the data input from the shift resist and the shift resist that continuously stores and shifts the data output from After that, a buffer is applied to the LCD panel.

For example, the logic circuit unit divides the horizontal clock signal for division into two, and generates a horizontal clock signal identical to the data, and a horizontal clock signal in which the levels of the horizontal clock signal and the horizontal clock signal are inverted. And a data latch unit for inputting and latching data, and an output selecting unit for selecting data output from the data latch unit and outputting the data toward the shift resist.

Hereinafter, a driving system of a liquid crystal display according to the present invention will be described with reference to FIGS. 1 to 8.

In the driving system of the liquid crystal display 100 shown in FIG. 1, predetermined color data and control signals are input to the controller 110, and DC power is provided to the power supply unit 120. When DC power is applied to the power supply unit 120, the power supply unit 120 supplies a constant voltage necessary for the operation of the controller 110, the gray scale generator 130, and the gate voltage generator 140.

Here, the controller 110 outputs various control signals and data for determining the gray level for each pixel to the source drive part 200 electrically connected to the LCD panel 160, and also controls the gate drive part 150. Configured to output signals.

In addition, the gray voltage generator 140 is configured to supply a gray voltage to the source drive part 200, and the gate voltage generator 140 supplies a voltage for generating turn-on / turn-off voltage to the gate drive part 150. Supply.

In addition, the gate and source drive parts 150 and 200 electrically connected to the LCD panel 160 generate a source signal and a gate signal and apply the generated source signal to the LCD panel.

In addition, the LCD panel 160 is formed by crossing the gate line 162 and the data lines 164 with each other, and TFTs 166 are formed at these intersections, respectively. A source signal is applied to the source electrode through the data lines 164, and a liquid crystal capacitor Clc and a storage capacitor Cs are formed on the drain electrode side.

On the other hand, a plurality of gate drive ICs 151 for generating a gate signal are electrically connected to the gate drive part, and each of the gate drive ICs 151 is level shifted with the shift resist 152 as shown in FIG. 2. 154 and an amplifier 155.

The shift signal STV and the vertical clock signal V_CLK are input to the shift resist 152, and the shift resist 152 has a plurality of outputs sequentially in the longitudinal direction, and thereafter, the carry out signals carry different shift resists. Is input as a signal.

The level shift 154 receives the turn-on voltage Von and the turn-off voltage Voff from the gate voltage generator 140, and turns on the level of the signal output from the shift resist 152 to the level shift 154. Or it is converted to the turn-off voltage level and output to the amplifier 156.

In addition, the amplifier 156 amplifies the signal output from the level shift 154 to a predetermined gain value and outputs the signal to the LCD panel 160 as a gate signal. In this case, the output of the amplifier 156 is determined by the output enable signal OE.

In addition, a plurality of source drive ICs 201 for outputting a source signal are electrically connected to the source drive part 200. According to the present invention, the logic circuits 210, 310, and 410 and the shift resister 270 are formed inside each source drive IC. , Digital / analog converter 280 and buffer 290 are formed.

Here, the logic circuits 210, 310, and 410 receive the horizontal clock signal H_CLK, the shift signal STH, and the 6-bit RGB data in which the 65 MHz mast clock signal is divided into two or four. A horizontal clock signal having the same frequency and another horizontal clock signal having the inverted level of the horizontal clock signal are generated to accurately register the data and transfer the data to the shift resist 270.

That is, at the time of rising the horizontal clock signal and another horizontal clock signal whose level is inverted, each data is latched and transferred to the shift register 270.

In addition, the shift resist 270 shifts the data output from the logic circuits 210, 310, and 410 and continuously stores the data, and then carries out the data when the first source drive IC 201 is filled. out) is transmitted to the next source drive IC to repeat the above-described operation.

When the data is completely filled in the plurality of source drive ICs through this process, the load signal TP is input to the shift resist 270 so that the stored resist is simultaneously output to the digital / analog converter 280. .

The digital / analog converter 280 converts the data into an analog voltage corresponding to an encoding value and outputs the data toward the buffer 290.

The buffer 290 adjusts the output of the analog voltage output from the digital / analog converter 280 and then applies a source signal to the LCD panel 160.

Hereinafter, the configuration and operation of the logic circuit unit 210, 310, 410 of the present invention will be described in more detail with reference to FIGS.

The logic circuit 210 according to the first embodiment includes a horizontal clock signal CLK of 16.25 MHz transmitted from the controller 110 and another horizontal clock signal inverting the signal. Is generated, the horizontal clock signals CLK, ) To fetch and output the data correctly.

The logic circuit unit 210 is electrically connected to the buffer 242 and the buffer 242 to delay the predetermined signal while outputting the horizontal clock signal CLK input from the controller 110 as it is and output from the buffer 242. A first D flip-flop having a clock input terminal for inputting the horizontal clock signal CLK, a data input terminal D, and a data output terminal Q and outputting the input data value as it is; ), The inverter 252 for inverting the level of the horizontal clock signal CLK transmitted from the controller 110, and the horizontal clock signal inverted in the inverter 252 electrically connected to the inverter 252 ( ) Is a clock input terminal, a data input terminal (D) and a data output terminal (Q) is provided with the second D flip-flop 255 and the output terminals of the first and second D flip-flops (245, 255) And an output selector 260 that is electrically connected to and selects and outputs data signals transmitted from the first and second D flip-flops 245 and 255.

Here, the output selector 260 is a horizontal clock signal (CLK) and the inverted horizontal clock signal ( After inputting these two horizontal clock signals (CLK, ) To select only one of the four data input terminals D0, D1, D2, and D3 to output data input from the first and second D flip-flops 245 and 255. to be.

That is, the clock signal input terminal S0 electrically connected to the output side of the buffer 242 and the clock signal input terminal S1 are electrically connected to the output side of the inverter 252 so that the clock signal input terminal S1 has a low level "0" level clock signal CLK, ) Is input, the input terminal of D0 is selected to output the signal, and the signal of "0" level is input to S0, and the signal of "1" level is input to S1, the input terminal of D1 is input. On the contrary, if the signal of level "1" is input to S0 and the signal of level "0" is input to S1, D2 is selected. Finally, if the signal of high level "1" is input to both S0 and S1, D3 is input. Is selected.

Here, the horizontal clock signal CLK and the horizontal clock signal inverted ( ) Is input, so when the signals input to S0 and S1 are combined, they become "1,0" or "0,1", so that only the input terminals of D1 and D2 can be selected.

Accordingly, the data output terminal Q of the first D flip-flop 245 is electrically connected to the input terminal of D1, and the data output terminal Q of the second D flip-flop 255 is connected to the data input terminal of D2. Electrically connected.

The operation of the logic circuit according to the first embodiment of the present invention will be described with reference to the timing chart shown in FIG.

First, when the clear signal CLR is applied to the first and second D flip-flops 245 and 255 to initialize the first and second D flip-flops 245 and 255 to the "0" level, the controller 110 divides 16.25. The horizontal clock signal CLK of MHz is input to the buffer 242 and the inverter 252 of the logic circuit 210, respectively.

The buffer 242 outputs the horizontal clock signal CLK shown in FIG. 5A as it is, and transmits the same to the clock input terminal of the first D flip-flop 245 and the S1 terminal of the multiplexer 260, respectively, and the inverter 252. ) Inverts the level of the horizontal clock signal CLK shown in FIG. 5A and then inverts the horizontal clock signal C as shown in FIG. 5B. ) Is transferred to the clock input terminal of the second D flip-flop 255 and the S1 terminal of the multiplexer 260, respectively.

Here, the reason why the buffer 242 is formed at the front end of the first D flip-flop 245 is because the horizontal clock signal CLK transmitted from the controller 210 is inverted after passing through the inverter 252. By delaying the horizontal clock signal CLK input to the flip-flop 245, the horizontal clock signal CLK is inverted from the horizontal clock signal CLK ( ) To match the motivation.

Meanwhile, when the horizontal clock signal CLK transmitted from the controller 110 is applied to the buffer 242 and the inverter 252, the 6-bit RGB data shown in FIG. 5C is the first and second D flip-flops 245 and 255. Is input to the data input terminal (D).

As described above, the first and second D flip-flops 245 and 255 include data, a horizontal clock signal CLK, and an inverted horizontal clock signal ( ) Is input to the S0 and S1 terminals of the multiplexer 260, and the horizontal clock signal CLK and the inverted horizontal clock signal ( ) Is input, first, the second D flip-flop 255 is the inverted horizontal clock signal ( In accordance with the rising point of the < RTI ID = 0.0 >),< / RTI > the " 1 " level signal of the data shown in FIG. 5C is latched and then transmitted to the multiplexer 260.

Here, the inverted horizontal clock signal ( ) Is lined with a signal of "1" level, the horizontal clock signal CLK is polled as a signal having a "O" level, so the horizontal clock signal CLK of level "0" is input to S0 of the multiplexer 260. S1 has a horizontal clock signal ("1" level) ), The multiplexer 260 selects the input terminal of D2 among the four input terminals. Therefore, the "1" level signal input from the second D flip-flop 255 is output through the output terminal of the multiplexer 260 and stored in the shift register 270.

And, the inverted horizontal clock signal ( ) Is raised to the "1" level and then polled to the "0" level, the horizontal clock signal CLK rises to the "1" level. Therefore, the second D flip-flop 255 does not register data and the first D flip. Only the flop 245 latches the " 0 " level signal of the data shown in FIG. 5C at the rising time of the horizontal clock signal CLK, and then transfers the signal to the multiplexer 260. FIG.

At this time, the horizontal clock signal CLK of level "1" is input to S0 of the multiplexer 260 and the horizontal clock signal of level "0" is input to S1. Since the multiplexer 260 selects the data input terminal of D1 connected to the output terminal of the first D flip-flop 245 among the four input terminals, the multiplexer 260 inputs " The 0 " level data signal is output through the output terminal of the multiplexer 260 and stored in the shift resist 270.

If the above process is repeatedly repeated, the multiplexer 260 outputs a data signal as shown in FIG. 5D and sequentially stores the data in the shift resist 270.

Thereafter, as described above, when all the source drive ICs 201 are filled with data, the data is input to the digital / analog converter 280, and the digital / analog converter 280 encodes the data to transmit the data line 164. The gray voltages to be output are selected, and the gray voltages selected as a result of encoding a specific voltage among the gray voltages applied by the gray generator 130 are passed through the buffer 290 to each data line of the LCD panel 160. 164 is applied.

Meanwhile, the logic circuit 310 according to the second embodiment delays the phase of the horizontal clock signal CLK and the horizontal clock signal CLK by dividing the horizontal clock signal transmitted from the controller 110 by 180 degrees. By generating the signal DCLK, the data is correctly digitized and output as the horizontal clock signals CLK and DCLK having the same frequency as the data.

As shown in FIG. 6, the logic circuit 310 includes a clock divider 311 which divides the horizontal clock signal CLK0 for two divisions largely transmitted from the controller 110, and a horizontal clock signal CLK divided by two. Clock signal delay unit 320 for delaying the phase of the signal 180 °, the data latch unit 340 and the data latch for inputting the horizontal clock signal CLK and the horizontal clock signal DCLK having the phase 180 ° delayed to latch data. And an output selector 360 that selects data output from the tooth 340 and outputs the data to the shift resist 270.

Here, the clock divider 311 may include one D flip-flop 315 and one inverter that inverts the level of data output from the D flip-flop 315 and inputs it to the input terminal of the D flip-flop 315. 312, the clock signal delay unit 320 is electrically connected to the output terminal of the D flip-flop 315, and 2 x n inverters 322 for delaying the phase of the horizontal clock signal CLK by 180 degrees. It consists of

In addition, the data latch unit 340 is electrically connected to an output terminal of the D flip-flop 315 and receives the horizontal clock signal CLK outputted therein to latch the data and the first D flip-flop 345 and a clock signal. A second D flip-flop 355 electrically connected to the delay unit 320 and receiving the horizontal clock signal DCLK having a phase delayed 180 degrees from the horizontal clock signal CLK to latch data.

The output selector 360 is electrically connected to the clock signal delay unit 320 and receives a clock signal input terminal H and a first clock signal DCLK having a phase delayed 180 degrees from the horizontal clock signal CLK. The first data input terminal D1 electrically connected to the data output terminal Q of the D flip-flop 345 and the second data input terminal electrically connected to the data output terminal of the second D flip-flop 355 ( D2), the first and second input terminals D1 and D2 are selected according to the level of the horizontal clock signal DCLK input to the clock signal input terminal H to output the input data values as they are.

The operation of the logic circuit according to the second embodiment of the present invention will be described with reference to the timing chart shown in FIG.

First, when a mast clock of 65 MHz is divided by two at the controller 110 and the frequency divider horizontal clock signal CLK0 having a frequency of 32.5 MHz is input to the D flip-flop 315 as shown in FIG. The flop 315 latches and outputs data only at the rising point of the frequency division clock signal CLK0.

For example, when the D flip-flop 315 is in the initial state and a signal of "0" level is input, the "0" level is horizontal as shown in FIG. 7B through the data output terminal of the D flip-flop 315. The clock signal CLK is output as it is.

Here, as shown in FIGS. 7A and 7B, when the frequency divider horizontal clock signal CLK0 is risen twice, the D flip-flop 315 latches and outputs one data, so that the D flip-flop 315 is output. The frequency of the horizontal clock signal CLK is 16.25 MHz, which is 1/2 of the frequency of the horizontal clock signal CLK0 for division.

Through this process, the horizontal clock signal CLK output from the D flip-flop 315 is applied to the inverter 312, the first D flip-flop 345, and the clock signal delay unit 320, respectively. The horizontal clock signal CLK inputted at the NX is inputted to the input terminal D of the D flip-flop 315 after the level is inverted, for example, the signal of the "0" level is inverted to the signal of the "1" level. And used as a source to generate a horizontal clock signal CLK waveform as shown in FIG. 7B.

That is, when the level of the horizontal clock signal CLK output from the D flip-flop 315 is continuously inverted by the inverter 312 and input to the D flip-flop 315, the horizontal clock signal divided at 16.25 MHz is shown in FIG. 7B. The waveform of (CLK) can be obtained.

When the horizontal clock signal CLK continuously generated through the above-described process is applied to the first D flip-flop 345, the 6-bit RGB data input to the first D flip-flop 345 is latched to output the output selector ( 360), and as shown in FIG. 7B, when the horizontal clock signal CLK is initially input to the "0" level, data cannot be latched.

Accordingly, the phase of the horizontal clock signal CLK shown in FIG. 7B is delayed by 180 ° by the clock signal delay unit 320 and is at a level opposite to the horizontal clock signal CLK input to the first D flip-flop 345. Data is latched and output from the second D flip-flop 355 to which the horizontal clock signal DCLK is input.

In this case, when the horizontal clock signal CLK passes through the inverter 322 of the clock signal delay unit 320, the horizontal clock signal CLK is delayed by a predetermined time and passes through all 2 × n inverters 322. Therefore, the horizontal clock signal DCLK is generated such that the level of the horizontal clock signal CLK is inverted.

The horizontal clock signal DCLK generated as described above is input to the output selector 360 as well as the second D flip-flop 355.

On the other hand, when the high level signal used to latch the data, that is, the horizontal clock signal DCLK of the " 1 " level, is input to the output selector 360, the output selector 360 is the second of the two input terminals. The second data input terminal D2 electrically connected to the data output terminal Q of the D flip-flop 355 is selected and outputted to the shift resist 270.

When the horizontal clock signal DCLK input to the second D flip-flop 355 is raised to the "1" level and then polled to the "0" level, the horizontal clock signal input to the first D flip-flop 345. Since the CLK rises to the " 1 " level, data is not digitized in the second D flip-flop 355, and only shown in FIG. 7D in accordance with the rising time of the horizontal clock signal CLK only in the first D flip-flop 345. The "0" level signal of the acquired data is latched and then output to the output selector 360.

In this case, since the low level horizontal clock signal DCLK, that is, the signal having the "0" level, is input to the output selector, the output selector Q of the first D flip-flop 345 among the two input terminals. ) And first data input terminal (D1) electrically connected to the) to output the data to the shift resist (270).

If the above-described process is repeated at a high speed, the data selector outputs a signal as shown in FIG. 7E and is sequentially stored in the shift resist 270.

Thereafter, as described above, when all the source drive ICs 201 are filled with data, the data is input to the digital / analog converter 280, and the digital / analog converter 280 encodes the data to transmit the data line 164. The gray voltages to be output are selected, and the gray voltages selected as a result of encoding a specific voltage among the gray voltages applied by the gray generator 130 are passed through the buffer 290 to each data line of the LCD panel 160. 164 is applied.

Finally, the logic circuit unit 410 according to the third embodiment divides the horizontal clock signal CLK0 for dividing transmitted by the controller 110 into two and the horizontal clock signal CLK and the horizontal clock signal whose level is inverted. Is generated, the horizontal clock signal CLK, ) And register the data correctly.

As shown in FIG. 8, the logic circuit unit 410 divides the clock divider 411 which divides the horizontal clock signal CLK0 of 32.5 MHz largely transmitted from the controller 110 into two, and the horizontal clock signal divided into two. A data latch unit 420 for latching data and outputting the data to a predetermined place according to CLK, and an output selecting unit 460 for selecting data output from the data latch unit 420 and outputting the data to the shift resist 270. do.

Here, the clock divider 411 includes one D flip-flop 415 and one inverter that inverts the level of data output from the D flip-flop 415 and inputs it to the input terminal of the D flip-flop 415. 412).

In addition, the data latch unit 440 outputs the horizontal clock signal CLK input from the clock divider 411 as it is and delays the horizontal clock signal CLK by a predetermined signal. A first D flip-flop 445 and a clock input terminal electrically connected to the horizontal clock signal CLK output from the buffer 442, and a data input terminal D and a data output terminal Q are provided. An inverter 452 for inverting the level of the horizontal clock signal CLK transmitted from the division unit 411, a horizontal clock signal electrically connected to the inverter 452 and inverted in the inverter 452 ( The second D flip-flop 455 is provided with a clock input terminal, a data input terminal D, and a data output terminal Q.

The output selector is composed of three buffers 462, 464, 465 and one inverter 468. The first buffer 462 is electrically connected to the data output terminal Q of the first D flip-flop 445 to form a third buffer. The data applied from the first D flip-flop 445 is output only when the output of the 468 is high level, and the second buffer 464 is electrically connected to the output terminal of the second D flip-flop 455. The data applied by the second D flip-flop 455 is output only when the output of the inverter 468 is high level.

In addition, the input terminal of the third buffer 466 is connected to the output terminal of the inverter 452 and the output terminal is connected to the second buffer 464 to drive the second buffer 464, and the input terminal of the inverter 468 is an inverter ( It is connected to the output terminal of 452 and the output terminal is electrically connected to the first buffer 462 to drive the first buffer 462.

The operation of the logic circuit according to the third embodiment of the present invention will be described with reference to the timing chart shown in FIG.

First, when a mast clock of 65 MHz is divided in two by the controller 110 and the frequency divider horizontal clock signal CLK0 having a frequency of 32.5 MHz is input to the D flip-flop 415 as shown in FIG. The flop 415 latches and outputs data only at the rising time of the frequency division clock signal CLK0.

For example, when a signal of level "0" is input when the D flip-flop 415 is in an initial state, the level "0" level is horizontal as shown in FIG. 9B through the data output terminal of the D flip-flop 415. The clock signal CLK is output as it is. Since the frequency-divided horizontal clock signal CLK0 having a waveform rises twice as shown in Figs. 9A and 9B, the D flip-flop 415 is output. ), The frequency of the horizontal clock signal CLK outputted from the reference signal becomes 16.25 MHz, which is 1/2 of the frequency of the horizontal clock signal CLK0 for division.

Through this process, the horizontal clock signal CLK divided by two is output from the D flip-flop 415 and applied to the buffer 442 and the inverter 452 of the inverter 412, the data latch unit 440, respectively.

Here, when the level of the horizontal clock signal CLK input to the inverter 412 is, for example, a "0" level, the inverter 412 inverts the signal of the "1" level and then inputs the D flip-flop 415 again. It is input to the terminal D and used as a source to generate a horizontal clock signal CLK waveform as shown in FIG. 9B.

That is, when the level of the horizontal clock signal CLK output from the D flip-flop 415 is continuously inverted by the inverter 412 and inputted to the D flip-flop 415, the horizontal clock signal divided at 16.25 MHz as shown in FIG. 9B. The waveform of (CLK) can be obtained.

Further, when the horizontal clock signal CLK shown in FIG. 9B is input to the buffer 442, the horizontal clock signal CLK transmitted from the clock divider 411 passes through the inverter 452. By delaying the horizontal clock signal CLK by a delayed time, the horizontal clock signal CLK input to the first D flip-flop 445 and the horizontal clock signal input to the second D flip-flop 455 ( ) To match the motive.

The inverter 452 inverts the level of the input horizontal clock signal CLK and then inverts the horizontal clock signal (see FIG. 9C). ) Is transferred to the clock input terminal H of the second D flip-flop 455 and the input terminal of the inverter 468 and the third buffer 466 of the output selector 460.

Meanwhile, when the horizontal clock signal CLK transmitted from the clock divider 411 is applied to the buffer 442 and the inverter 452 of the data latch unit 440, the 6-bit RGB data shown in FIG. The data input terminal D of the first and second D flip-flops 445 and 455 is input.

In this manner, data, the horizontal clock signal CLK, and the inverted horizontal clock signal (C) are transmitted to the first and second D flip-flops 445 and 455. ) Is input, the inverted horizontal clock signal (as shown in Fig. 9c) ) Is operated before the horizontal clock signal CLK, so the second D flip-flop 455 operates first, and the second D flip-flop 455 is the inverted horizontal clock signal CLK. The value "1" of the data shown in FIG. 9D is latched according to the rising point of time) and transferred to the input terminal of the second buffer 464.

At this time, the inverted horizontal clock signal shown in Fig. 9c ( When the signal of the "1" level used for regulating the data among the terminals is input to the inverter 468 of the output selector 460, the signal of the inverted door "0" level is output to the first buffer 462. As a result, the first buffer 462 may not output data applied from the first D flip-flop 445.

However, the inverted horizontal clock signal ( Is applied to the third buffer 466 of the output selector 460, the same signal " 1 " Since the second buffer 464 is applied to the second buffer 464, the second buffer 464 outputs the data applied from the second D flip-flop 455 and transfers the data to the shift resist 270.

On the other hand, the inverted horizontal clock signal ( When the clock is raised and then polled, the horizontal clock signal CLK rises, so that the second D flip-flop 455 does not latch data, but at the time of the rising of the horizontal clock signal CLK in the first D flip-flop 445. In accordance with this, the "0" value of the data shown in FIG. 9D is latched and then transferred to the first buffer 462.

At this time, the inverted horizontal clock signal ( ) When the signal of level "0" is input to the inverter 468 of the output selector 460, the level is inverted so that the signal of level "1" is output, so that the first buffer 462 is the first D flip-flop ( The data applied at 445 is output and stored in the shift resist 270.

However, the horizontal clock signal having the "0" level ( Is applied to the third buffer 466 of the output selector 460, the same signal " 0 " is output and applied to the second buffer 464. Therefore, in the second buffer 464, the second D flip-flop 455 is applied. ) Is not outputted data.

If the above-described process is repeated at a high speed, the output selector outputs a signal as shown in Fig. 9E, and is sequentially stored in the shift resist.

Thereafter, as described above, when all the source drive ICs 201 are filled with data, the data is input to the digital / analog converter 280, and the digital / analog converter 280 encodes the data to transmit the data line 164. The gray voltages to be output are selected, and the gray voltages selected as a result of encoding a specific voltage among the gray voltages applied by the gray generator 130 are passed through the buffer 290 to each data line of the LCD panel 160. 164 is applied.

When the logic circuits described in the first, second and third embodiments are formed at the input terminals of the respective source drive ICs, the frequency of the horizontal clock signal which latches the RGB data is reduced by 1/2 compared to the conventional method, which is equivalent to 16.25 MHz as the RGB data. As a result, the driving circuit can be made excellent in terms of electromagnetic characteristics and timing tuning compared with the prior art.

That is, when data is latched using a 16.25MHz horizontal clock signal and a horizontal clock signal whose phase is delayed by 180 ° using an inverter or a delay unit, it is as if the 16.25MHz horizontal clock signal is rising and falling. It has the same effect as latching the data.

In addition, when using a 16.25MHz horizontal clock signal and another horizontal clock signal whose phase is 180 ° out of phase, the data set-up time and hold time are sufficiently secured and the output waveform of the data is stabilized. Less occurrence of

For example, in a XGA-class (1024 × 768) liquid crystal display, if the data holding time is 30ms, the horizontal clock signal and the rising time of the horizontal clock time with a 180 ° delay are coincident with the center of the data. Since the set-up time and the hold time of the data are about 15 ms, sufficient set-up time and hold time can be secured to stabilize the output waveform.

As described above, according to the present invention, a logic circuit portion for generating a horizontal clock signal having the same frequency as RGB data and another horizontal clock signal having a phase difference of 180 ° from the horizontal clock signal is formed at the input terminal of the source drive IC. Therefore, the horizontal clock signal and the horizontal clock signal delayed by 180 ° in phase can precisely latch the RGB data, thereby minimizing the damage of electromagnetic waves caused by the high frequency of the horizontal clock signal.

In addition, when the data is latched using the horizontal clock signal having the same frequency as the RGB data and the horizontal clock signal delayed in phase of 180 °, the data set-up time and hold time are sufficiently secured to suppress the generation of noise. It has an effect.

Claims (15)

A power supply unit for supplying a voltage required for each unit, a controller for outputting data and control signals to implement a predetermined screen, a gradation generator for generating a plurality of gradation voltages using the voltage applied from the power supply unit, and the power supply A gate voltage generator for outputting a gate turn-on / turn-off voltage using a voltage applied from a supply unit, and a source drive IC for inputting some signals included in the data and the control signal and the gray level voltage to output a source signal For example, gate drive ICs for outputting a gate signal by applying the other signal included in the control signals and the gate turn on / off voltage and an LCD for displaying a predetermined screen when the source signal and the gate signal are applied. In a driving system of a liquid crystal display device comprising a panel, Each of the source drive ICs A logic circuit unit generating a horizontal clock signal having a phase different from a horizontal clock signal having the same frequency as the data and the horizontal clock signal by 180 ° to latch the data; A shift register which continuously inputs and outputs data output from the logic circuit unit and continuously stores the shift register; A digital / analog converter for encoding the data input from the shift resist to select a gray scale voltage; And And a buffer configured to apply an output to the LCD panel after controlling the output of the control voltage output from the digital / analog converter. The logic circuit of claim 1, wherein the logic circuit unit A data input terminal into which the data is input, a clock input terminal to which a horizontal clock signal having a frequency equal to the data frequency is input by being divided by the controller several times, and an output terminal to output data latched by the horizontal clock signal; First D flip-flop; An inverter for inverting the level of the horizontal clock signal at the same frequency as the data; A clock input terminal electrically connected to the inverter to input a horizontal clock signal inverted by the inverter, a data input terminal to which data is input, and an output terminal to output data latched by the inverted horizontal clock signal; 2 D flip-flop; And An output electrically connected to the output terminals of the first and second D flip-flops to select and output only one of the data output from the first and second D flip-flops to the shift resist; A drive system for a liquid crystal display device, characterized by comprising a selection unit. 3. The horizontal clock of claim 2, wherein the horizontal clock signal is inputted to the first D flip-flop for a time that the horizontal clock signal passes through the inverter to the second D flip-flop. 3. And a buffer for delaying the signal. The method of claim 3, wherein the output selector A first clock signal input terminal electrically connected to an output terminal of the buffer to receive the horizontal clock signal; A second clock signal input terminal electrically connected to an output terminal of the inverter and receiving the inverted horizontal clock signal; And Input terminals D0 to D3, whose two terminals are electrically connected to the output terminals of the first and second D flip-flops, and whose output is selected according to a combination of signals input to the first and second clock signal input terminals. Driving system of the liquid crystal display device characterized in that the multiplexer consisting of. The output terminal of the first D flip-flop is selected when a low level signal is input to the first clock signal input terminal and a high level signal is input to the second clock signal input terminal. Electrically connected to the input terminal of the output D1, The output terminal of the second D flip-flop is an input terminal of D2 for outputting data selected when a high level signal is input to the first clock signal input terminal and a low level signal is input to the second clock signal input terminal. And an electrical connection with the liquid crystal display device. The logic circuit of claim 1, wherein the logic circuit unit A clock divider which divides the horizontal clock signal for division divided by the controller into two and generates the same horizontal clock signal as the data; A clock signal delay unit for delaying a phase of the horizontal clock signal by 180 degrees; A data latch unit which latches data by inputting the horizontal clock signal and the horizontal clock signal whose phase is 180 DEG; And And an output selector configured to select data output from the data latch and output the data toward the shift resist. The clock divider of claim 6, wherein the clock divider comprises: A D flip-flop comprising an input terminal for inputting a predetermined signal, a clock input terminal for inputting the horizontal clock signal for division, and an output terminal for outputting the horizontal clock signal obtained by dividing the division clock signal; A drive system of the liquid crystal display device comprising an inverter for inverting the level of the horizontal clock signal output from the D flip-flop and inputting it to an input terminal of the D flip-flop; 7. The liquid crystal display of claim 6, wherein the clock signal delay unit is electrically connected to an output terminal of the D flip-flop and configured by 2 x n inverters for delaying a phase of the horizontal clock signal by 180 degrees. Drive system. The method of claim 6, wherein the data latch unit A data input terminal to which the data is input, a clock input terminal electrically connected to an output terminal of the D flip-flop, and a clock input terminal to which the horizontal clock signal is input, and an output terminal to output data latched by the horizontal clock signal; 1 D flip-flop; A clock input terminal electrically connected to the clock signal delay unit to receive a horizontal clock signal delayed by 180 °, a data input terminal to which the data is input, and data latched by a horizontal clock signal delayed by 180 ° And a second D flip-flop having an output terminal for outputting the digital signal. The method of claim 6, wherein the output selector A clock signal input terminal electrically connected to the clock signal delay unit to receive a horizontal clock signal having a phase delay of 180 °; A first data input terminal electrically connected to an output terminal of the first D flip-flop and selected when a low level signal is input to the clock signal input terminal to output data; And And a second data input terminal electrically connected to a data output terminal of the second D flip-flop and selected and outputted when a high level signal is input to the clock signal input terminal. Drive system. The logic circuit of claim 1, wherein the logic circuit unit A clock divider which divides the horizontal clock signal for division divided by the controller into two and generates the same horizontal clock signal as the data; A data latch unit for inputting the horizontal clock signal and the horizontal clock signal having the inverted level of the horizontal clock signal to latch data; And And an output selector configured to select data output from the data latch and output the data toward the shift resist. The method of claim 11, wherein the clock divider A D flip-flop comprising an input terminal for inputting a predetermined signal, a clock input terminal for inputting the horizontal clock signal for division, and an output terminal for outputting the horizontal clock signal obtained by dividing the division clock signal; A drive system of the liquid crystal display device comprising an inverter for inverting the level of the horizontal clock signal output from the D flip-flop and inputting it to an input terminal of the D flip-flop; The method of claim 11, wherein the data latch unit A data input terminal to which the data is input, a clock input terminal electrically connected to an output terminal of the D flip-flop, and a clock input terminal to which the horizontal clock signal is input, and an output terminal to output data latched by the horizontal clock signal; 1 D flip-flop; An inverter for inverting the level of the horizontal clock signal at the same frequency as the data; A clock input terminal electrically connected to the inverter to input a horizontal clock signal inverted by the inverter, a data input terminal to which data is input, and an output terminal to output data latched by the inverted horizontal clock signal; A drive system for a liquid crystal display device, characterized in that it comprises a 2D flip-flop. 14. The horizontal clock of claim 13, wherein the horizontal clock signal is inputted to the first D flip-flop for a time inputted to the clock input terminal of the first D flip-flop through the inverter to the second D flip-flop. And a buffer for delaying the signal. 12. The apparatus of claim 11, wherein the data selector A first buffer electrically connected to an output terminal of the first D flip-flop and outputting data input from the first D flip-flop to the shift resist only when a high level signal is input; A second buffer electrically connected to an output terminal of the second D flip-flop and outputting data input from the second D flip-flop to the shift register only when a high level signal is input; A third buffer having an input terminal electrically connected to an output side of the inverter of the data latch unit and an output terminal electrically connected to a second buffer to drive the second buffer; And And an input terminal is electrically connected to an output side of the inverter of the data latch unit, and an output terminal is electrically connected to a first buffer to drive the first buffer.