KR20000010310A - Gray scale voltage generator with pulse width modulation method - Google Patents

Abstract

PURPOSE: A gray scale voltage generator is provided to simplify component of a device and to improve response speed of a device using pulse width modulation. CONSTITUTION: The gray scale voltage generator comprises a controller, a pulse generator, a shift register, a pulse selection unit, a data latch unit, a driver. The controller takes a control signal, a clock, a gray scale level data and generates data synchronized at the clock by the control signal. The pulse generator generates macro pulses and micro pulses. The macro pulse roughly defines a width of driving pulse. The micro pulse exactly adjusts the width of driving pulse. The shift register takes the gray scale data from the controller and transforms to parallel data to generates parallel gray scale data by each column. The pulse selection unit takes macro pulses and micro pulses from the pulse generator and takes parallel gray scale data form the shift register. The pulse selection unit selects one of pulse in macro pulses and selects one of pulse in micro pulses according to the parallel gray scale data. The pulse selection unit multiplies selected the macro pulse and the micro pulse and generates a gray scale pulse. The data latch unit takes the gray scale pulse from the pulse selection unit and saves the pulse in response to the control signal and generates a pulse. The driving takes gray scale pulse from the data latch and transforms level of pulse and drives a pixel.

Description

Pulse width modulation type gradation voltage generator

The present invention relates to a driving circuit of a liquid crystal display device, and more particularly, to a gray scale voltage generating circuit in a driving circuit of a liquid crystal display device.

With the development of manufacturing technology and driving technology of STN (Super Twisted Nematic) liquid crystal panel, it is now possible to display moving images in color by liquid crystal panel. Currently, the response speed of STN liquid crystal panel is close to 50ms, which is the response speed of TFT liquid crystal panel using TN (Twisted Nematic) liquid crystal. In order to improve the response speed of the STN liquid crystal panel, it is required to generate grayscale voltage at high speed and drive each pixel.

In general, a liquid crystal display generates a gray scale voltage by a frame rate control (FRC) method or a pulse width modulation (PWM) method.

The FRC type gray voltage generator adjusts the intensity of the on voltage applied to a pixel by periodically applying on / off on a frame basis to adjust an effective voltage (RMS voltage) applied to the pixel. For example, in order to generate four gray voltages of full on, half on, half off, and full off, three frames are combined on and off in each frame. That is, when the full on voltage is to be applied, the on voltage is continuously applied to the pixel for three frame periods, and when the full off voltage is to be applied, the off voltage is continuously applied to the pixel for three frame periods. In addition, when the half-on voltage is to be applied, the on voltage is applied to the pixel only in two frames among the three frames, and when the half-off voltage is to be applied, the on voltage is applied to only one frame among the three frames.

In the FRC type gray scale voltage generator, the larger the number of gray scales, the more frames must be included in one cycle. As a result, a pixel having a low gray level has a long period of voltage applied to the pixel, so that the frame response characteristic is deteriorated, so that it takes a long time to display a desired gray level (or color), and an afterimage remains in a moving image. There is a problem.

The PWM system generates a gray level by adjusting an application time of an on voltage applied to a pixel within one frame period. The time during which the on voltage can be applied to the pixel during one frame period is set to 1 / (number of liquid crystal panel columns), and during this time, the pulse width of the on voltage applied to the pixel is changed in proportion to the gray level.

However, in the conventional PWM system for generating a gradation voltage, a pulse width modulated signal as many as the number of gradations is generated, and one of these is selected and outputted, so that the pulse width modulated signal generation circuit becomes complicated in proportion to the number of gradations. There was this.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and it is a technical object of the present invention to provide a gradation voltage generator capable of generating a large number of gradation pulse width modulation signals while employing only a small number of pulse width modulation signal generation circuits.

1 is a graph showing a relationship between an effective voltage and a transmittance of a liquid crystal in a liquid crystal panel.

2 is a block diagram of a preferred embodiment of a gradation voltage generating device according to the present invention.

3 is a waveform diagram illustrating pulses generated by the pulse generator of FIG. 2.

4 is a circuit diagram of the pulse generator of FIG. 2.

FIG. 5 is a circuit diagram illustrating one of the pulse selection circuits in the pulse selector of FIG. 2.

In order to achieve the above technical problem, the present invention provides a pulse width modulation method gradation voltage generator of a liquid crystal panel displaying a gray level by adjusting the width of a driving pulse applied to a pixel. The control unit receives data representing the gray level for each pixel together with the control signal and the clock, and outputs the data in synchronization with the clock under the control of the control signal. The pulse generator generates macro pulses for roughly determining the width of the driving pulse and micro pulses for precisely adjusting the width of the driving pulse. The shift register receives grayscale data from the control unit, converts the grayscale data into parallel data, and outputs parallel grayscale data for each column. A pulse selector receives the macro pulses and micro pulses from the pulse generator and receives parallel grayscale data from the shift register, selects one of the macro pulses and the micro pulses, respectively, according to the parallel grayscale data, By multiplying the selected pulses, one gray scale pulse is generated and output. The data latch unit receives the gradation pulse from the pulse selector, temporarily stores the output signal in response to a control signal from the control unit, and outputs the result. The drive unit drives a few pixels that receive the gray scale pulse from the data latch unit and convert the level.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1 is a graph showing a general relationship between an effective voltage and a transmittance of a liquid crystal in a liquid crystal panel. As shown, the greater the effective voltage applied to the liquid crystal panel, the higher the transmittance of the liquid crystal. Therefore, since the effective voltage increases when a signal having a long pulse width is applied, the transmittance of the liquid crystal increases accordingly.

In the present invention, instead of separately generating different pulse signals for all the effective voltages separated by the vertical dotted line in FIG. 1, the voltage groups 1, 2, 3, 4). In addition to generating the micro pulses in addition to the macro pulses and multiplying the macro pulse by the micro pulses, the pulse width is adjusted for fine adjustment of the effective voltage in each of the voltage groups 1, 2, 3, and 4. .

2 is a block diagram of a preferred embodiment of a gradation voltage generating device according to the present invention. In general, in order to drive the liquid crystal panel, a vertical line driving signal and a horizontal line driving signal of the pixel matrix should be generated. The gray voltage generator of FIG. 2 generates a vertical line driving signal.

The gray scale voltage generator of FIG. 2 includes a controller 10, a pulse generator 12, a shift register 14, a pulse selector 16, a data latcher 18, a level shifter 20, and a driver 22. It includes.

The control unit 10 receives data indicating the gray level for each pixel together with the control signal and the clock CLK, and supplies the data to the shift register 14 in synchronization with the clock CLK under the control of the control signal. In this embodiment, it is assumed that the gray level of each gray level of each pixel is 16 and therefore the data is represented by 4 bits for each pixel.

The pulse generator 12 generates macro pulses pw1-pw4 and micro pulses sub1-sub4 in synchronization with a clock. 3 is a waveform diagram illustrating macro pulses pw1-pw4 and micro pulses sub1-sub4 generated in the pulse generator 12. The macro pulses pw1-pw4 and the micro pulses sub1-sub4 are repeatedly generated at a period of 16 clocks. The macro pulses pw1-pw4 are used to select the voltage groups 1, 2, 3, 4 of FIG. 1, and the micro pulses sub1-sub4 are used to select the macro pulses pw1-sub within each voltage group. It is multiplied by pw4) and used to adjust the detail width of the macro pulses pw1-pw4. Therefore, according to the present invention, only eight pulses can be generated to generate 16 pulse widths.

The shift register 14 receives gradation data from the control unit 10, shifts the received data, converts the received data into parallel data, and outputs 4-bit parallel gradation data for each column.

The pulse selector 16 receives the macro pulses pw1-pw4 and the micro pulses sub1-sub4 from the pulse generator 12, and receives 4-bit parallel gradation data for each column from the shift register 14. It is. The pulse selector 16 selects one pulse from among the macro pulses pw1-pw4 and the micro pulses sub1-sub4 in response to 4 bits of parallel grayscale data for each column, and selects the selected pulses. By multiplying, one gradation pulse is generated and output.

The data latch unit 18 receives the gradation pulses for each column from the pulse selector 16, temporarily stores them in response to a control signal from the control unit 10, and outputs them. The level shifter 20 receives the gray level pulse from the data latch unit 18, converts the voltage level of the gray level pulse to a higher level, and then outputs the level converted gray level signal. The driver 22 receives the gray level signal from the level shifter 20 and selects an on / off voltage of the pixel according to the gray level signal to drive the pixel.

4 is a circuit diagram of the pulse generator 12 of FIG. 2.

Eight di-D flip-flops D1-D8 are connected in a ring shape. The clock CLK is applied to the clock input terminals of the D flip-flops D1-D8 and the tee flip-flop T1. A reset signal is reset to the reset input terminal R of the D flip-flops D1-D4 and the tee flip-flop T1, and to the set input terminal S of the D flip-flops D5-D8. Is applied. On the other hand, the output of the D flip-flop D8 is applied to one input terminal of the AND gate 32 and the AND gate 34, and the output signal of the T flip-flop T1 is applied to the other input terminal.

When the reset signal resets from 'high' to 'low', the D flip flops D1-D4 and the T flip flop T1 are reset and the D flip flops D5-D8 are set. Accordingly, the D flip-flop D8 outputs 'high' and the T flip-flop T1 outputs 'low'.

Then, when the clock CLK is applied, the T flip-flop T1 toggles 'high' and this signal is output as a macro pulse pw2. At this time, the AND gate 32 and the AND gate 34 outputs a 'high' signal as macro pulses pw1 and pw3, respectively. Thereafter, the states of the macro pulses pw1 to pw3 change in units of four clocks as shown in FIG. 3.

Meanwhile, the twelve D flip-flops D9-D20, the D flip-flops D20 and D21, and the AND gates 36 and 38 generate micro pulses sub1-sub3. Twelve D flip-flops D9-D20 are connected in series. The clock CLK is applied to the clock input terminals of the D flip-flops D9 to D20. In addition, a reset signal reset is applied to the set input terminal S of the D flip-flops D9 to D19 and the reset input terminal R of the D flip-flop D20. The D flip-flop D21 receives and latches the output of the D flip-flop D20. The D flip-flop D22 receives and latches the output of the D flip-flop D21. The AND gate 36 accepts the outputs of the D flip-flops D20 and D21 to perform an AND operation, and the AND gate 38 outputs the AND gate 36 and the D flip-flop D22. Accept and perform an AND operation. The outputs of the AND gate 38, the AND gate 38, and the D flip-flop D20 are output as micro pulses sub1 to sub3, respectively.

In this embodiment, since the macro pulse pw4 and the micro pulse sub4 always have a 'high' level, the pulse selector 16 instead of the pulse generator 12 generates and supplies these pulses. The power supply voltage (VDD) level is used as a surrogate signal for.

FIG. 5 is a circuit diagram illustrating one of the pulse selection circuits in the pulse selector of FIG. 2. The pulse select circuit of FIG. 5 includes a first select circuit 42, a second select circuit 44, and an inverted AND gate 46.

The first selection circuit 42 selects one of the macro pulses pw1-pw4 in response to the upper two bits D2 and D3 of the 4-bit parallel grayscale data D0-D3. The macro pulse pw1 is selected when the parallel gradation data D2 and D3 are '00', and the macro pulse pw2 is selected when the parallel gradation data D2 and D3 is '01'. When the parallel grayscale data D2 and D3 are '10', the macro pulse pw3 is selected. When the parallel grayscale data D2 and D3 is '11', the macro pulse pw4, that is, the power supply voltage ( VDD) level is selected.

The second selection circuit 44 selects one of the micro pulses sub1-sub4 in response to the upper two bits D0, D1 of the 4-bit parallel grayscale data D0-D3. When the parallel grayscale data D0 and D1 are '00', the micro pulse sub1 is selected, and when the parallel grayscale data D0 and D1 are '01', the micro pulse sub2 is selected. Further, when the parallel grayscale data D0 and D1 are '10', the micro pulse sub3 is selected. When the parallel grayscale data D0 and D1 are '11', the micro pulse sub4, that is, the power supply voltage ( VDD) level is selected.

The inverse AND gate 46 performs an inverse AND operation on the macro pulse selected by the first selection circuit 42 and the micro pulse selected by the second selection circuit 44, and outputs the result of the operation as a gradation pulse. do. Meanwhile, in another embodiment of the present invention, an AND gate or other gate may be used instead of the inverted AND gate according to the waveforms of the macro pulses pw1 to pw4 and the micro pulses sub1 to sub4.

As described above, according to the gradation voltage generating device of the present invention, a large number of pulse width modulation signals can be generated by generating a small number of pulse width modulation signals and combining them. Therefore, there is an effect that the configuration of the gradation voltage generator can be simplified and a large number of gray levels can be displayed. In addition, since a simple logic circuit is used to select the pulse width modulated signal, the response speed of the device is maintained fast.

Claims (1)

In the pulse width modulation method gradation voltage generator of a liquid crystal panel which displays a gray level by adjusting a width of a driving pulse applied to a pixel, A control unit which receives data representing gray levels for each pixel together with a control signal and a clock, and outputs the data in synchronization with a clock under the control of the control signal; A pulse generator for generating macro pulses for roughly determining the width of the driving pulse and micro pulses for precisely adjusting the width of the driving pulse; A shift register which receives grayscale data from the control unit, converts the grayscale data into parallel data, and outputs parallel grayscale data for each column; Receive the macro pulses and the micro pulses from the pulse generator and receive the parallel grayscale data from the shift register, select one of the macro pulses and the micro pulses according to the parallel grayscale data, and select the selected pulses A pulse selector for generating and outputting one gradation pulse by multiplying; A data latch unit which receives the gray scale pulses from the pulse selector, temporarily stores and outputs them in response to a control signal from the controller; And a driving unit which receives a gray level pulse from the data latching unit and drives several pixels whose levels are converted.