KR101016731B1 - Liquid crystal display using spread spectrum and driving method thereof - Google Patents

Abstract

The present invention relates to a liquid crystal display device and a driving method thereof capable of reducing electromagnetic interference by using a spread spectrum.

A liquid crystal display device according to the present invention comprises: a liquid crystal panel having a pixel matrix; A memory for storing a plurality of frequency spreading information; A timing controller for generating a plurality of control signals having a pulse width determined according to the plurality of frequency spreading information; And a liquid crystal panel driver for driving the liquid crystal panel using control signals from a timing controller.

Description

Liquid crystal display using a spread spectrum and its driving method {LIQUID CRYSTAL DISPLAY USING SPREAD SPECTRUM AND DRIVING METHOD THEREOF}             

1 illustrates a conventional liquid crystal display device.

2A and 2B are waveform diagrams of input and output signals of the timing controller shown in FIG.

3 is a diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

4 is an input / output signal waveform diagram of the timing controller shown in FIG. 3;

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

2, 12: liquid crystal panel 4, 14: gate driver

6, 16: data driver 8, 18: timing controller

10: spread spectrum IC 20: memory

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof capable of reducing electromagnetic interference by using a spread spectrum.

The liquid crystal display displays an image by adjusting the light transmittance of the liquid crystal having dielectric anisotropy using an electric field. To this end, the liquid crystal display includes a liquid crystal panel having a pixel matrix and a driver for driving the liquid crystal panel.

Specifically, the liquid crystal display includes a liquid crystal panel 2 having a pixel matrix, a gate driver 4 for driving gate lines GL1 to GLm of the liquid crystal panel 2, as shown in FIG. A data driver 6 for driving the data lines DL1 to DLn of the liquid crystal panel 2, and a timing controller 8 for controlling the driving timing of the gate driver 4 and the data driver 6. do.

The liquid crystal panel 2 includes a pixel matrix composed of pixels formed at respective regions defined by intersections of the gate lines GL1 to GLm and the data lines DL1 to DLn. Each of the pixels includes a liquid crystal cell Clc for adjusting light transmittance according to a pixel signal, and thin film transistors TFT for driving the liquid crystal cell Clc.

The thin film transistor TFT is turned on when the scan signal from the gate line GL, that is, the gate high voltage VGH is supplied, and supplies the pixel signal from the data line DL to the liquid crystal cell Clc. The thin film transistor TFT is turned off when the gate low voltage VGL is supplied from the gate line GL to maintain the pixel signal charged in the liquid crystal cell Clc.

The liquid crystal cell Clc is equivalently represented by a capacitor, and includes a common electrode facing each other with a liquid crystal interposed therebetween and a pixel electrode connected to the thin film transistor TFT. In addition, the liquid crystal cell Clc further includes a storage capacitor (not shown) so that the charged pixel signal is stably maintained until the next pixel signal is charged. The liquid crystal cell Clc realizes gray by adjusting light transmittance by varying an arrangement state of liquid crystals having dielectric anisotropy according to pixel signals charged through the thin film transistor TFT.

The gate driver 4 shifts a gate start pulse (hereinafter, referred to as a GSP) from the timing controller 8 according to a gate shift clock (hereinafter, referred to as a GSC). Scan pulses having a gate high voltage (hereinafter referred to as VGH) are sequentially supplied to GL1 to GLm). The gate driver 4 supplies the gate low voltage (hereinafter referred to as VGL) in the remaining periods when VGH is not supplied to the gate lines GL1 to GLn. In addition, the gate driver 4 controls the pulse width of the scan pulse according to a gate output enable signal (hereinafter referred to as a GOE) signal from the timing controller 8.

The data driver 6 generates a sampling signal by shifting the source start pulse (hereinafter referred to as SSP) from the timing controller 8 according to the source shift clock (hereinafter referred to as SSC). do. The data driver 6 latches the pixel data RGB according to the SSC according to the sampling signal and then lines by line in response to a source output enable signal (SOE). Supply. Subsequently, the data driver 6 converts the gamma voltage from a gamma voltage part (not shown) into pixel signals RGB supplied in line units to analog pixel signals and supplies them to the data lines DL1 through DLn. Here, the data driver 6 determines the polarity of the pixel signal in response to the polarity control (hereinafter referred to as POL) signal from the timing controller 8 when converting the pixel data into the pixel signal. The data driver 6 determines a period in which the pixel signal is supplied to the data lines DL1 to DLn in response to the SOE.

The timing controller 8 generates GSP, GSC, GOE signals, etc. for controlling the gate driver 4, and generates SSP, SSC, SOE, POL signals, etc., for controlling the data driver 6. In this case, the timing controller 8 may include a data enable (Data Enable) signal indicating a valid data section input from the outside, a horizontal sync signal (hereinafter referred to as Hsync), and a vertical sync signal (hereinafter referred to as Control signals such as GSP, GSC, GOE, SSP, SSC, SOE, POL, etc. using a dot clock (hereinafter referred to as DCLK) that determines the transmission timing of pixel data RGB. Will be created. In particular, the timing controller 8 spreads the spread spectrum to reduce electromagnetic interference (hereinafter referred to as EMI) between various control signals and pixel data signals transmitted to the gate driver 4 and the data driver 6. According to the Spread Spectrum method, control signals such as the GSP, GSC, GOE, SSP, SSC, SOE, and POL are generated using DCLK (hereinafter, SDLCK) spread in a specific frequency range. Accordingly, the frequency of the control signals generated by the timing controller 8 is not kept constant, but has a form of shaking within a specific frequency range along the SDCLK. As a result, EMI between the control signals is caused by the shaking frequency. The offset and reduction effect can be obtained.

For this frequency spreading, the liquid crystal display shown in FIG. 1 further includes a spread spectrum IC 10 for frequency spreading the DCLK input from the outside to the timing controller 8. The spread spectrum IC 10 frequency modulates the input DCLK and adjusts the oscillation frequency using a phase-locked loop (hereinafter referred to as a PLL) circuit according to the modulated frequency, as shown in FIGS. 2A and 2B. As shown in the figure, the output of SDCLK varies with a certain period within a specific frequency range.

FIG. 2A shows the case where the frequency spreading period of the SDCLK is larger than the period of Hsync. The pulse width is shown as an example. Here, the first and second control signals CS1 and CS2 correspond to any one of the GSP, GOE, SSP, and SOE signals.

However, such a liquid crystal display device has a problem in that the cost is increased because a spread spectrum IC 10 must be additionally provided to frequency spread the DCLK input from the outside to the timing controller 8 for frequency spreading.

Accordingly, it is an object of the present invention to provide a liquid crystal display device and a driving method thereof capable of reducing electromagnetic interference by using a spread spectrum.

In order to achieve the above objects, a liquid crystal display according to an embodiment of the present invention includes a liquid crystal panel having a pixel matrix; A memory for storing a plurality of frequency spreading information; A timing controller for generating a plurality of control signals having a pulse width determined according to the plurality of frequency spreading information; And a liquid crystal panel driver for driving the liquid crystal panel using control signals from the timing controller.

In the liquid crystal display, the frequency spread information indicates a rising time and a polling time of the control signals.

The rising time and the falling time of the control signals are determined by counting an input clock signal supplied from the liquid crystal display to the timing controller.

In the LCD, the control signals have different rising time points and different polling time points for each frame.

The control signals in the liquid crystal display include a gate start pulse, a gate shift clock, and a gate enable signal that are required by the liquid crystal panel driver to drive the gate lines of the liquid crystal panel. It includes the source start pulse, source shift clock, source enable signal, and polarity control signal needed for driving.

A method of driving a liquid crystal display according to an embodiment of the present invention includes storing a plurality of frequency spreading information for a control signal in a memory; Generating a plurality of control signals having a pulse width determined according to the plurality of frequency spreading information; Driving the liquid crystal panel using the control signals.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 3 and 4.

3 illustrates a liquid crystal display according to an exemplary embodiment of the present invention.

The liquid crystal display shown in FIG. 3 includes a liquid crystal panel 12 having a pixel matrix, a gate driver 14 for driving gate lines GL1 to GLm of the liquid crystal panel 12, and a liquid crystal panel 12. A data driver 16 for driving the data lines DL1 to DLn of the memory, a memory 20 storing a change range of control signals for driving the gate driver 14 and the data driver 16, and a memory ( And a timing controller 18 for controlling the driving timing of the gate driver 14 and the data driver 16 by using the change range of the control signals stored in the controller 20.

The liquid crystal panel 12 includes a pixel matrix composed of pixels formed at regions defined by intersections of the gate lines GL1 to GLm and the data lines DL1 to DLn. Each of the pixels includes a liquid crystal cell Clc for adjusting light transmittance according to a pixel signal, and thin film transistors TFT for driving the liquid crystal cell Clc.                     

The thin film transistor TFT is turned on when the scan signal from the gate line GL, that is, the gate high voltage VGH is supplied, and supplies the pixel signal from the data line DL to the liquid crystal cell Clc. The thin film transistor TFT is turned off when the gate low voltage VGL is supplied from the gate line GL to maintain the pixel signal charged in the liquid crystal cell Clc.

The liquid crystal cell Clc is equivalently represented by a capacitor and includes a common electrode facing each other with a liquid crystal interposed therebetween and a pixel electrode connected to the thin film transistor TFT. In addition, the liquid crystal cell Clc further includes a storage capacitor (not shown) so that the charged pixel signal is stably maintained until the next pixel signal is charged. The liquid crystal cell Clc realizes gray by adjusting light transmittance by varying an arrangement state of liquid crystals having dielectric anisotropy according to pixel signals charged through the thin film transistor TFT.

The gate driver 14 shifts the GSP from the timing controller 18 according to the GSC to sequentially supply the scan pulses having VGH to the gate lines GL1 to GLm. The gate driver 14 supplies the VGL in the remaining period in which the VGH is not supplied to the gate lines GL1 through GLn. The gate driver 14 also controls the pulse width of the scan pulse in accordance with the GOE signal from the timing controller 18.

The data driver 16 shifts the SSP from the timing controller 18 in accordance with the SSC to generate a sampling signal. The data driver 16 latches the pixel data RGB input according to the SSC according to the sampling signal and supplies the line data in response to the SOE signal. Subsequently, the data driver 16 converts the gamma voltage from a gamma voltage part (not shown) into the analog pixel signal by supplying the pixel data RGB supplied on a line basis to the data lines DL1 to DLn. Here, the data driver 16 determines the polarity of the pixel signal in response to the POL from the timing controller 18 when converting the pixel data RGB into the pixel signal. The data driver 16 determines a period in which the pixel signal is supplied to the data lines DL1 to DLn in response to the SOE signal.

The memory 20 stores a change range (spreading information) of control signals for driving the gate driver 14 and the data driver 16. The memory 20 is an electric erasable programmable ROM (EEPROM), in which spread information CSS of control signals as shown in Table 1 is stored.

address Justice 01 CS_R-1 2Clk 02 CS_F-1 8Clk 03 CS_R-2 4Clk 04 CS_F-2 12Clk .
.
. .
.
. .
.
.

Referring to Table 1, the rising time CS_R-1 of the control signal CS supplied during the first frame is stored in the first address 01, and the second address 02 is supplied during the first frame. The polling time point CS_F-1 of the control signal CS is stored. At this time, the rising time CS_R-1 of the control signal CS supplied during the first frame is a time point at which the i th dot clock DCLKi is supplied (i is a natural number greater than 1) as shown in FIG. 4. to be. Here, it is assumed that the i-th dot clock DCLKi is a time point at which the second dot clock DCLK2 is supplied. That is, as shown in Table 1, the rising time CS_R-1 of the control signal CS stored in the first address 01 is a time point at which the second dot clock DCLK2 is supplied. The polling time CS_F-1 of the control signal CS supplied during the first frame is a time point at which the j th (j is a natural number larger than i) th dot clock DCLKi is supplied as shown in FIG. 4. . Here, it is assumed that the j-th dot clock DCLKj is a time point at which the 8th dot clock DCLK8 is supplied. That is, as shown in Table 1, the polling time CS_F-1 of the control signal CS stored in the second address 02 is a time point at which the eighth dot clock DCLK8 is supplied. Accordingly, the control signal CS supplied during the first frame has a frequency corresponding to j − i dot clocks (eg, 8 − 2 = 6 dot clocks).

The third address 03 stores the rising time CS_R-2 of the control signal CS supplied during the second frame, and the fourth address 04 stores the rising time CS_R-2 of the control signal CS supplied during the second frame. Polling time point CS_F-2 is stored. At this time, the rising time CS_R-2 of the control signal CS supplied during the second frame is a time point when the p-th (p is a natural number greater than 1) th dot clock DCLKp as shown in FIG. 4. to be. Here, it is assumed that the p-th dot clock DCLKp is a time point at which the fourth dot clock DCLK4 is supplied. That is, as shown in Table 1, the rising time CS_R-2 of the control signal CS stored in the third address 03 is a time point at which the fourth dot clock DCLK4 is supplied. The polling time point CS_F-2 of the control signal CS supplied during the second frame is a time point at which the r-th dot clock DCLKr (r is a natural number larger than p) is supplied as shown in FIG. 4. . Here, it is assumed that the r-th dot clock DCLKr is a time point at which the 12th dot clock DCLK12 is supplied. That is, as shown in Table 1, the polling time CS_F-2 of the control signal CS stored in the fourth address 04 is a time point at which the 12th dot clock DCLK12 is supplied. Accordingly, the control signal CS supplied during the second frame has a frequency corresponding to r − p dot clocks (eg, 12 − 4 = 8 dot clocks).

In this way, the memory 20 stores the variation range CSS of the rising time and the falling time of the control signals CS supplied for each frame, that is, spreading information. The spreading information CSS of the rising time and the falling time of the control signal CS is set differently from frame to frame and stored in the memory 20. Here, the control signal CS corresponds to any one of the GSP, GOE, SSP, SOE signal and the like. On the other hand, the spreading information CSS of the rising time and polling time of the control signals CS stored in the memory 20 is read from the memory 20 and the timing controller 18 so that the information is read every frame using I ² C communication. Write communication program between).

The timing controller 18 generates GSP, GSC, GOE signals, etc. for controlling the gate driver 14, and generates SSP, SSC, SOE, POL signals, etc., for controlling the data driver 16. In this case, the timing controller 18 uses the DE signal, the Hsync, the Vsync, and the spread information CSS of the control signals CS stored in the memory 20 for the valid data section input from the outside. It generates control signals CS such as GOE, SSP, SSC, SOE, and POL signals. Here, the control signals CS have different frequencies from frame to frame by the spread information CSS of the control signals CS stored in the memory 20, so that the control signals CS generated by the timing controller 18 are generated. The frequencies of the waves do not remain constant and have a swinging shape. As a result, EMI between the control signals transmitted from the timing controller 18 is canceled by the shaking frequency, thereby reducing the effect.

As described above, in the liquid crystal display according to the present invention, since the control signals have different frequencies from each other by using a memory in which spread information of the control signals are stored, the frequencies of the control signals generated by the timing controller are not kept constant, but are shaken. Will have As a result, EMI between control signals transmitted from the timing controller is canceled by the shaking frequency, thereby reducing the effect.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (10)

A liquid crystal panel having a pixel matrix; A memory for storing a plurality of frequency spreading information; A timing controller for generating a plurality of control signals having a pulse width determined according to the plurality of frequency spreading information; And a liquid crystal panel driver for driving the liquid crystal panel by using control signals from the timing controller. The method of claim 1, And the frequency spread information indicates a rising time and a falling time of the control signals. The method of claim 2, And a rising time and a falling time of the control signals are determined by counting an input clock signal supplied to the timing controller. The method of claim 3, wherein And the control signals have different rising time points and different polling time points for each frame. The method of claim 1, The control signals, The liquid crystal panel driver includes a gate start pulse, a gate shift clock, and a gate enable signal required to drive the gate lines of the liquid crystal panel, and a source start pulse required to drive the data lines of the liquid crystal panel. And a source shift clock, a source enable signal, and a polarity control signal. Storing a plurality of frequency spreading information for the control signal in a memory; Generating a plurality of control signals having a pulse width determined according to the plurality of frequency spreading information; And driving a liquid crystal panel using the control signals. The method of claim 6, The frequency spreading information indicates a rising time and a falling time of the control signals. The method of claim 7, wherein The rising time and the falling time of the control signals are determined by counting an input clock signal. The method of claim 8, And the control signals have different rising time points and different polling time points for each frame. The method of claim 6, The control signals, A liquid crystal panel driver comprising a gate start pulse, a gate shift clock, and a gate enable signal required to drive gate lines of the liquid crystal panel, a source start pulse required to drive data lines of the liquid crystal panel; A driving method of a liquid crystal display device comprising a source shift clock, a source enable signal, and a polarity control signal.

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