KR20010010858A - method of fabricating semiconductor package - Google Patents

method of fabricating semiconductor package Download PDF

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Publication number
KR20010010858A
KR20010010858A KR1019990029970A KR19990029970A KR20010010858A KR 20010010858 A KR20010010858 A KR 20010010858A KR 1019990029970 A KR1019990029970 A KR 1019990029970A KR 19990029970 A KR19990029970 A KR 19990029970A KR 20010010858 A KR20010010858 A KR 20010010858A
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KR
South Korea
Prior art keywords
metal wire
insulating
semiconductor chip
wire
semiconductor package
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KR1019990029970A
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Korean (ko)
Inventor
고재원
이재승
Original Assignee
이수남
주식회사 칩팩코리아
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Priority to KR1019990029970A priority Critical patent/KR20010010858A/en
Publication of KR20010010858A publication Critical patent/KR20010010858A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PURPOSE: A method for manufacturing a semiconductor package is to prevent each metal wire from being shorted even when a wire sweeping is generated in a molding process. CONSTITUTION: A semiconductor package fabrication method comprises the steps of: adhering a semiconductor chip(10) to an electric connection carrier(40); electrically connecting the electric connection carrier with a bonding pad(11) of the semiconductor chip by a metal wire(20); jetting an insulation material(30) to the resultant structure, and then isolating the metal wire by an insulating coating layer; and molding the resultant structure by a sealant so that only the outer connection terminal of the electric connection carrier is exposed. The insulation material is a high molecule insulating hardener resin. The high molecule insulating hardener resin is a high molecule silicon or polyamide. The electric connection carrier is a lead frame.

Description

반도체 패키지의 제조 방법{method of fabricating semiconductor package}Method of fabricating semiconductor package

본 발명은 반도체 패키지의 제조 방법에 관한 것으로서, 보다 구체적으로는 반도체 칩의 본딩 패드가 금속 와이어에 의해 리드 프레임에 전기적으로 연결된 반도체 패키지를 제조하는 방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor package, and more particularly, to a method of manufacturing a semiconductor package in which the bonding pads of the semiconductor chip are electrically connected to the lead frame by metal wires.

패키지의 한 예로서, 가장 범용으로 사용되고 있는 에스오제이(SOJ:Small Outline J-lead) 타입이 있고, 특수한 경우에 사용하는 지프(ZIP: Zigzag Inline Package) 타입이 있으며, 또 규격화되고 있는 메모리 카드(memory card)에 적합하도록 구성된 티에스오피(TSOP: Thin Small Outline Package) 타입 등이 있다.An example of a package is a small outline J-lead (SOJ) type that is most commonly used, and a Zigzag Inline Package (ZIP) type that is used in a special case. There is a Thin Small Outline Package (TSOP) type that is configured to be suitable for a memory card.

이러한 패키지 제조 방법을 개략적으로 설명하면 다음과 같다.The manufacturing method of such a package is briefly described as follows.

먼저, 웨이퍼를 스크라이빙 라인을 따라 절단하는 소잉(sawing) 공정을 진행하여 개개의 반도체 칩으로 분리한 다음, 리드 프레임의 인너 리드를 각 반도체 칩에 부착하는 다이 어태치 공정을 진행한다.First, a sawing process of cutting a wafer along a scribing line is performed to separate the semiconductor chips into individual semiconductor chips, and then a die attach process of attaching the inner lead of the lead frame to each semiconductor chip is performed.

이후 일정 온도에서 일정시간 동안 큐어링(curing)을 실시한 후, 반도체 칩의 패드와 리드 프레임의 인너 리드를 금속 와이어로 상호 연결시켜 전기적으로 연결시키는 와이어 본딩 공정을 수행한다.After curing at a predetermined temperature for a predetermined time, a wire bonding process is performed in which the pads of the semiconductor chip and the inner lead of the lead frame are interconnected with metal wires to be electrically connected to each other.

와이어 본딩이 끝나면, 봉지제를 사용하여 반도체 칩을 몰딩하는 몰딩 공정을 수행한다. 이와 같이 반도체 칩을 몰딩해야만, 외부의 열적, 기계적 충격으로 부터 반도체 칩을 보호할 수가 있는 것이다.After the wire bonding is finished, a molding process of molding a semiconductor chip using an encapsulant is performed. Only by molding the semiconductor chip in this way, can the semiconductor chip be protected from external thermal and mechanical shocks.

상기와 같은 몰딩 공정이 완료된 후에는 아우터 리드을 도금하는 플래팅 공정, 아우터 리드를 지지하고 있는 댐바를 절단하는 트림 공정, 및 기판에 실장이 용이하도록 아우터 리드를 소정 형태로 절곡 형성하는 포밍 공정을 진행하여, 패키지를 제조한다.After the molding process is completed, a plating process for plating the outer lead, a trimming process for cutting the dam bar supporting the outer lead, and a forming process for bending the outer lead into a predetermined shape to facilitate mounting on the substrate are performed. To prepare the package.

한편, 최근에는 아우터 리드 포밍 공정 대신에, 리드 프레임 자체에 볼 랜드를 형성하고, 이 볼 랜드가 봉지제에서 노출되도록 한 후, 솔더 볼을 각 볼 랜드에 마운트하는 방법이 주류를 이루고 있다.On the other hand, in recent years, instead of the outer lead forming step, a ball land is formed in the lead frame itself, and the ball land is exposed in the encapsulant, and then a solder ball is mounted on each ball land.

그러나, 상기된 종래의 방법에서 와이어 본딩 후 몰딩 공정을 실시하는데, 이 몰딩 공정중에 다음과 같은 문제점이 발생된다. 몰딩 공정은 와이어 본딩이 완료된 반도체 칩과 리드 프레임을 몰드 다이에 안치시키고, 몰드 다이의 게이트를 통해서 봉지제를 플로우시키는 것으로 진행된다.However, in the conventional method described above, a molding process is performed after wire bonding, and the following problems occur during the molding process. The molding process proceeds by placing the semiconductor chip and lead frame in which the wire bonding is completed in the mold die, and flowing the encapsulant through the gate of the mold die.

그런데, 금속 와이어는 연성이 우수한 재질인 관계로, 봉지제 플로우시 금속 와이어가 한쪽으로 쏠리는 와이어 스위핑(wire sweeping) 현상이 발생되어, 각 금속 와이어가 쇼트되는 심각한 문제점이 발생되었다. 특히, 반도체 칩의 크기가 줄어들어 본딩 패드간의 피치가 미세해짐에 따라 쇼트 현상은 더욱 심각한 문제점으로 대두되고 있는 실정이다.However, since the metal wire is a material having excellent ductility, a wire sweeping phenomenon occurs in which the metal wire is oriented to one side when the encapsulant flows, and a serious problem occurs in that each metal wire is shorted. In particular, as the size of the semiconductor chip is reduced and the pitch between the bonding pads becomes fine, the short phenomenon is a more serious problem.

이를 방지하기 위해서는, 봉지제의 플로우 속도를 적정하게 제어해야 하는데, 플로우 속도를 너무 낮추면 봉지제내에 보이드가 형성되고 특히 공정 시간이 증가하게 되는 다른 문제점이 유발된다.In order to prevent this, it is necessary to properly control the flow rate of the encapsulant. If the flow rate is too low, another problem occurs that voids are formed in the encapsulant, and in particular, the process time increases.

따라서, 본 발명은 종래의 제조 방법으로 인한 문제점을 해소하기 위해 안출된 것으로서, 몰딩 공정전에 각 금속 와이어가 절연되도록 하여, 몰딩 공정시 와이어 스위핑 현상이 발생되어도 각 금속 와이어가 쇼트되는 것을 방지할 수 있는 반도체 패키지의 제조 방법을 제공하는데 목적이 있다.Therefore, the present invention has been made to solve the problems caused by the conventional manufacturing method, so that each metal wire is insulated before the molding process, it is possible to prevent the short circuit of each metal wire even if a wire sweep phenomenon occurs during the molding process. An object of the present invention is to provide a method of manufacturing a semiconductor package.

도 1은 본 발명에 따른 패키지 제조 방법을 설명하기 위한 도면.1 is a view for explaining a package manufacturing method according to the present invention.

- 도면의 주요 부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawing-

10 ; 반도체 칩 11 ; 본딩 패드10; Semiconductor chip 11; Bonding pads

20 ; 금속 와이어 30 ; 절연물20; Metal wire 30; Insulation

40 ; 리드 프레임40; Lead frame

상기와 같은 목적을 달성하기 위하여, 본 발명에 따른 제조 방법은 다음과 같다.In order to achieve the above object, the manufacturing method according to the present invention is as follows.

먼저, 반도체 칩을 리드 프레임상에 접착하고, 금속 와이어로 반도체 칩과 리드 프레임을 전기적으로 연결시킨다. 그런 다음, 전체 결과물에 절연물을 분사한다. 그러면, 금속 와이어가 절연 피복층으로 둘러싸이게 된다. 이어서, 전체 결과물을 몰드 다이에 반입한 후, 몰드 다이내로 봉지제를 플로우시켜 몰딩한다. 이때, 각 금속 와이어는 절연 피복층에 의해 절연된 상태이므로, 와이어 스위핑 현상이 발생되어도 각 금속 와이어는 쇼트되지 않는다. 마지막으로, 봉지제에서 노출된 리드 프레임 부분에 솔더 볼을 마운트한다.First, the semiconductor chip is bonded onto the lead frame, and the semiconductor chip and the lead frame are electrically connected with a metal wire. Then insulate the entire product. The metal wire is then surrounded by an insulating coating layer. Subsequently, the entire resultant is brought into the mold die, and then the encapsulant is flowed into the mold die to be molded. At this time, since each metal wire is insulated by the insulating coating layer, even if a wire sweeping phenomenon occurs, each metal wire is not shorted. Finally, solder balls are mounted on the exposed lead frame portions of the encapsulant.

상기된 본 발명의 구성에 의하면, 금속 와이어에 절연물을 분사하여 절연 피복층으로 금속 와이어를 절연시키게 되므로써, 몰딩 공정중에 와이어 스위핑 현상에 의해서도 금속 와이어가 쇼트되는 현상이 방지된다.According to the above-described configuration of the present invention, the insulation is sprayed onto the metal wire to insulate the metal wire with the insulating coating layer, thereby preventing the metal wire from being shorted by the wire sweeping phenomenon during the molding process.

이하, 본 발명의 바람직한 실시예를 첨부도면에 의거하여 설명한다.Best Mode for Carrying Out the Invention Preferred embodiments of the present invention will now be described based on the accompanying drawings.

도 1은 본 발명에 따른 반도체 패키지 제조 방법을 설명하기 위한 도면이다.1 is a view for explaining a method of manufacturing a semiconductor package according to the present invention.

도 1을 참조로 하여, 반도체 칩(10)을 리드 프레임(40)상에 접착한다. 그런 다음, 반도체 칩(10)의 본딩 패드(11)와 리드 프레임(40)의 인너 리드를 금속 와이어(20)로 전기적으로 연결시킨다.Referring to FIG. 1, the semiconductor chip 10 is bonded onto the lead frame 40. Then, the bonding pad 11 of the semiconductor chip 10 and the inner lead of the lead frame 40 are electrically connected with the metal wire 20.

이어서, 본 발명에서 제시되는 공정이 실시된다. 즉, 몰딩 공정 전에, 절연물(30)을 전체 결과물 상부에 분사한다. 그러면, 전체 결과물의 상부, 즉 반도체 칩(10)의 표면과 금속 와이어(20)에 절연물(30)이 일정 두께로 코팅된다. 따라서, 금속 와이어(20)는 절연 피복층으로 둘러싸이게 된다. 또한, 반도체 칩(10)의 본딩 패드(11)에도 절연물(30)이 코팅된다. 도 1에서 타원형으로 도시한 부분이 절연물(30)이 분사되는 영역이다. 절연물(30)로는 고분자 실리콘이나 폴리이미드와 같은 고분자 절연성 경화 수지를 사용할 수 있다. 이러한 절연물(30)은 2∼3분이 경화하면 고형화된다.Subsequently, the process proposed in the present invention is carried out. That is, before the molding process, the insulator 30 is sprayed on the entire resultant. Then, the insulating material 30 is coated to a predetermined thickness on top of the entire result, that is, the surface of the semiconductor chip 10 and the metal wire 20. Thus, the metal wire 20 is surrounded by an insulating coating layer. In addition, the insulator 30 is also coated on the bonding pad 11 of the semiconductor chip 10. The oval in FIG. 1 is a region in which the insulator 30 is sprayed. As the insulator 30, a polymer insulating cured resin such as polymer silicone or polyimide may be used. The insulator 30 is solidified after 2-3 minutes curing.

그런 다음, 전체 결과물을 몰드 다이에 위치시킨 후, 몰드 다이의 게이트를 통해서 봉지제를 몰드 다이 내부로 플로우시킨다. 봉지제는 리드 프레임(40)의 아우터 리드 또는 리드 프레임(40)의 밑면에 형성된 볼 랜드, 즉 외부 접속 단자만이 노출되도록, 전체 결과물을 몰딩하게 된다. 이러한 몰딩 공정시, 플로우되는 봉지제에 의해 금속 와이어(20)들이 한 쪽으로 쏠리는 와이어 스위핑 현상이 발생되어도, 각 금속 와이어(20)는 절연 피복층으로 둘러싸여 있으므로, 쇼트 현상은 절대로 발생되지 않는다. 따라서, 봉지제의 플로우 속도 제어 마진이 확보된다.Then, after placing the entire result on the mold die, the encapsulant flows into the mold die through the gate of the mold die. The encapsulant molds the entire product so that only the ball lands formed on the bottom surface of the lead frame 40 or the outer lead of the lead frame 40, that is, the external connection terminals, are exposed. In this molding process, even if a wire sweeping phenomenon in which the metal wires 20 are pulled to one side by the encapsulant flowing is generated, each metal wire 20 is surrounded by an insulating coating layer, so a short phenomenon never occurs. Thus, the flow rate control margin of the encapsulant is secured.

마지막으로, 봉지제에서 노출된 리드 프레임(40)의 아우터 리드를 기판에 실장 가능하도록 포밍하거나 또는 리드 프레임(40)의 볼 랜드에 솔더 볼을 마운트한다.Lastly, the outer lead of the lead frame 40 exposed by the encapsulant is formed to be mountable on the substrate or the solder balls are mounted on the ball lands of the lead frame 40.

한편, 본 실시예에서는 금속 와이어(20)를 매개로 반도체 칩(10)의 본딩 패드(11)에 연결되는 전기적 연결 매개체로서 리드 프레임(40)을 예시하였다. 그러나, 본 발명에 따른 제조 방법이 리드 프레임(40)이 사용되는 패키지로만 국한되는 것은 물론 아니다. 다른 예로 금속 패턴이 절연층 사이에 형성된 패턴 필름이 사용되는 패키지에도 본 발명에 따른 방법이 적용될 수 있음은 물론이다.Meanwhile, in the present exemplary embodiment, the lead frame 40 is illustrated as an electrical connection medium connected to the bonding pad 11 of the semiconductor chip 10 through the metal wire 20. However, the manufacturing method according to the present invention is not limited to only the package in which the lead frame 40 is used. As another example, the method according to the present invention may be applied to a package in which a pattern film having a metal pattern formed between insulating layers is used.

이상에서 설명한 바와 같이 본 발명에 의하면, 몰딩 공정 전에 절연물을 분사하여, 금속 와이어이 절연 피복층으로 둘러싸이도록 하므로써, 몰딩 공정시 와이어 스위핑 현상이 발생되어도 각 금속 와이어가 쇼트되지 않게 된다.As described above, according to the present invention, the insulating material is sprayed before the molding process so that the metal wire is surrounded by the insulating coating layer, so that the metal wire is not shorted even if a wire sweeping phenomenon occurs during the molding process.

이상에서는 본 발명에 의한 패키지 제조 방법을 실시하기 위한 바람직한 실시예에 대하여 도시하고 또한 설명하였으나, 본 발명은 상기한 실시예에 한정되지 않고, 이하 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진자라면 누구든지 다양한 변경 실시가 가능할 것이다.In the above has been shown and described with respect to a preferred embodiment for carrying out a method of manufacturing a package according to the present invention, the present invention is not limited to the above embodiment, without departing from the gist of the invention claimed in the claims below Various modifications can be made by those skilled in the art to which the present invention pertains.

Claims (7)

금속 와이어를 이용한 와이어 본딩 공정을 포함하는 반도체 패키지의 제조 방법에 있어서,In the manufacturing method of the semiconductor package containing the wire bonding process using a metal wire, 상기 와이어 본딩 공정 후, 상기 금속 와이어를 절연 피복층으로 둘러싸는 공정을 실시하는 것을 특징으로 하는 반도체 패키지의 제조 방법.And a step of enclosing the metal wire with an insulating coating layer after the wire bonding step. 제 1 항에 있어서, 상기 절연물은 고분자 절연성 경화 수지인 것을 특징으로 하는 반도체 패키지의 제조 방법.The method of claim 1, wherein the insulator is a polymer insulating cured resin. 제 2 항에 있어서, 상기 고분자 절연성 경화 수지는 고분자 실리콘 또는 폴리이드인 것을 특징으로 하는 반도체 패키지의 제조 방법.The method of claim 2, wherein the polymer insulating curable resin is polymer silicone or polyide. 반도체 칩을 전기적 연결 매개체에 접착하는 단계;Adhering a semiconductor chip to an electrical connection medium; 상기 반도체 칩의 본딩 패드와 전기적 연결 매개체를 금속 와이어로 전기적으로 연결하는 단계;Electrically connecting a bonding pad of the semiconductor chip and an electrical connection medium with a metal wire; 상기 결과물 전체에 상부로부터 절연물을 분사하여, 상기 각 금속 와이어를 절연 피복층으로 절연시키는 단계; 및Insulating each of the metal wires with an insulating coating layer by spraying an insulator from the top on the whole resultant; And 상기 전기적 연결 매개체의 외부 접속 단자만이 노출되도록 전체 결과물을 봉지제로 몰딩하는 단계를 포함하는 것을 특징으로 하는 반도체 패키지의 제조 방법.Molding the entire product into the encapsulant such that only the external connection terminals of the electrical connection medium are exposed. 제 4 항에 있어서, 상기 절연물은 고분자 절연성 경화 수지인 것을 특징으로 하는 반도체 패키지의 제조 방법.The method of claim 4, wherein the insulator is a polymer insulating curable resin. 제 5 항에 있어서, 상기 고분자 절연성 경화 수지는 고분자 실리콘 또는 폴리이미드인 것을 특징으로 하는 반도체 패키지의 제조 방법.The method of manufacturing a semiconductor package according to claim 5, wherein the polymer insulating curable resin is polymer silicone or polyimide. 제 4 항에 있어서, 상기 전기적 연결 매개체는 리드 프레임인 것을 특징으로 하는 반도체 패키지의 제조 방법.The method of claim 4, wherein the electrical connection medium is a lead frame.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007129830A1 (en) * 2006-05-04 2007-11-15 Hanwha Chemical Corporation Semiconductor package having polymer coated copper wire and method for manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007129830A1 (en) * 2006-05-04 2007-11-15 Hanwha Chemical Corporation Semiconductor package having polymer coated copper wire and method for manufacturing the same

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