KR20010008441A - Method for forming contact of semiconductor device - Google Patents
Method for forming contact of semiconductor device Download PDFInfo
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- KR20010008441A KR20010008441A KR1019980062555A KR19980062555A KR20010008441A KR 20010008441 A KR20010008441 A KR 20010008441A KR 1019980062555 A KR1019980062555 A KR 1019980062555A KR 19980062555 A KR19980062555 A KR 19980062555A KR 20010008441 A KR20010008441 A KR 20010008441A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체장치의 콘택 형성방법에 있어서, 보다 상세하게는 콘택을 통해 다층 금속배선을 연결할 경우 장벽금속층과 매립금속과의 계면에서 발생되는 화합물에 의해 매립금속의 유효면적이 축소되어 전체적인 저항이 증가되는 것을 방지하기 위해 계면에서의 반응을 억제하도록 하여 전체적인 저항을 줄일 수 있도록 한 반도체장치의 콘택 형성방법에 관한 것이다.In the method of forming a contact of a semiconductor device, more particularly, when the multilayer metal wiring is connected through the contact, the effective area of the buried metal is reduced by the compound generated at the interface between the barrier metal layer and the buried metal, thereby reducing the overall resistance. The present invention relates to a method for forming a contact in a semiconductor device in which the overall resistance can be reduced by suppressing the reaction at the interface to prevent the increase.
최근에는 반도체 디자인 룰이 점점 미세화됨에 따라 반도체 소자를 다층배선 형태로 제조하고 있어 다층 금속배선간을 연결하기 위한 콘택이 매우 중요한 위치를 차지하게 되었다.In recent years, as semiconductor design rules become more and more sophisticated, semiconductor devices are manufactured in the form of multilayer interconnections, and contacts for interconnecting multilayer metal interconnections have become very important.
즉, 콘택을 통해 금속배선간의 신호전달이 이루어지기 때문에 접촉상태와 접촉저항에 따라 신호의 전달특성이 좌우되기 때문에 소자의 특성향상에 중요한 요인이된다.That is, since the signal transmission between the metal wiring is made through the contact, the signal transmission characteristic depends on the contact state and the contact resistance, which is an important factor in improving the characteristics of the device.
도 1내지 도 2는 종래 방법에 의한 반도체장치의 콘택 형성방법을 설명하기 위한 단면도들이다.1 to 2 are cross-sectional views illustrating a method for forming a contact of a semiconductor device by a conventional method.
도 1은 제 1금속층(10)위로 절연층(20)을 형성한 후 상부에 콘택홀(25)을 형성하기 위한 식각마스크로 감광막 패턴을 형성한 후 제 1금속층(10)이 노출되도록 절연층(20)을 식각하여 콘택홀(25)을 형성한다. 그런다음 전면에 장벽금속층으로 Ti층(32)을 증착하여 이후 매립되는 금속이 절연층(20)으로 확산되는 것을 방지하도록 한다.FIG. 1 illustrates that after forming the insulating layer 20 on the first metal layer 10 and forming a photoresist pattern as an etch mask for forming the contact hole 25 thereon, the insulating layer is exposed so that the first metal layer 10 is exposed. 20 is etched to form contact holes 25. Then, the Ti layer 32 is deposited as a barrier metal layer on the front surface to prevent the metal buried thereafter from being diffused into the insulating layer 20.
그런다음, 도 2와 같이 제 2금속층(40)을 알루미늄으로 고온에서 물리적 기상 증착 방법에 의해 콘택홀(25)을 매립하게 되면 Ti층(32)이 알루미늄과 반응하여 계면에 높은 저항을 갖는 TiAl3층(34)이 형성된다.Then, as shown in FIG. 2, when the contact hole 25 is buried in the second metal layer 40 with aluminum at a high temperature by physical vapor deposition, the Ti layer 32 reacts with aluminum to have a high resistance at the interface. Layer 34 is formed.
위와 같이 고온에서 제 2금속층(30)인 알루미늄을 증착하게 됨에 따라 콘택홀(25)의 계면에 증착된 Ti층(32)과 반응하여 높은 저항물질인 TiAl3층(34)을 형성하게 됨으로써 제 2금속층(40)의 유효면적을 줄여 반도체 소자의 금속배선에서 전체적인 저항 증가를 초래하며 과도하게 형성된 TiAl3층(34)은 반도체 소자의 전자이동(electro-migration) 특성을 저하시키게 된다는 문제점이 있다.As the aluminum is deposited as the second metal layer 30 at a high temperature as described above, the TiAl 3 layer 34, which is a high resistance material, is formed by reacting with the Ti layer 32 deposited at the interface of the contact hole 25. Reducing the effective area of the metal layer 40 causes an increase in overall resistance in the metal wiring of the semiconductor device, and excessively formed TiAl 3 layer 34 has a problem in that the electro-migration characteristics of the semiconductor device are degraded.
본 발명은 상기와 같은 문제점을 해결하기 위해 창작된 것으로서, 본 발명의 목적은 콘택홀을 형성한 후 장벽금속층을 증착할 때 Si가 함유시켜 매립금속과의 반응을 억제함으로써 얇고 균일한 장벽금속층을 형성하도록 함으로써 매립금속의 유효면적을 넓혀줌으로써 전체적인 저항을 줄일 수 있도록 한 반도체장치의 콘택 형성방법을 제공함에 있다.The present invention has been made to solve the above problems, and an object of the present invention is to form a thin and uniform barrier metal layer by suppressing the reaction with the buried metal by containing Si when depositing the barrier metal layer after forming the contact hole. The present invention provides a method for forming a contact in a semiconductor device in which the overall resistance can be reduced by increasing the effective area of the buried metal.
도 1내지 도 2는 종래 방법에 의한 반도체장치의 콘택 형성방법을 설명하기 위한 단면도들이다.1 to 2 are cross-sectional views illustrating a method for forming a contact of a semiconductor device by a conventional method.
도 3내지 도 4는 본 발명에 의한 반도체장치의 콘택 형성방법을 설명하기 위한 단면도들이다.3 to 4 are cross-sectional views illustrating a method for forming a contact of a semiconductor device according to the present invention.
- 도면의 주요부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawings-
10 : 제 1금속층 20 : 절연층10: first metal layer 20: insulating layer
25 : 콘택홀 32 : Ti층25 contact hole 32 Ti layer
34, 38 : TiAl3층 36 : Ti-Si층34, 38 TiAl 3 layer 36 Ti-Si layer
40 : 제 2금속층40: second metal layer
상기와 같은 목적을 실현하기 위한 본 발명은 제 1금속층 위로 절연층을 형성한 후 콘택홀을 형성하는 단계와, 콘택홀 전면에 Si가 함유된 장벽금속층을 형성하는 단계와, 장벽금속층을 형성한후 제 2금속층으로 콘택홀을 매립하는 단계를 포함하여 이루어진 것을 특징으로 한다.The present invention for achieving the above object is to form a contact hole after forming an insulating layer on the first metal layer, forming a barrier metal layer containing Si on the contact hole front surface, and forming a barrier metal layer And then burying a contact hole in the second metal layer.
위에서 Si가 함유된 장벽금속층은 Ti에 Si가 0.5∼10% 정도 함유된 Ti-Si 합금으로 상온 이하에서 증착하며, 증착전 웨이퍼의 온도를 충분히 냉각시킨 상태에서 증착하는 것을 특징으로 한다.The barrier metal layer containing Si is deposited at a temperature below room temperature with a Ti-Si alloy containing about 0.5 to 10% of Si in Ti, and is deposited while the temperature of the wafer is sufficiently cooled before deposition.
그리고 제 2금속층은 알루미늄으로 증착후 열을 가해 콘택내로 이동하도록 하는 것을 특징으로 한다And the second metal layer is characterized in that to move into the contact by applying heat after deposition of aluminum.
위와 같이 이루어진 본 발명의 작용을 설명하면 다음과 같다.Referring to the operation of the present invention made as described above are as follows.
콘택홀을 형성한 후 매립금속인 제 2금속층의 전자이동을 막기 위해 콘택홀 전면에 증착되는 장벽금속층을 Si가 함유된 Ti-Si합금으로 형성함으로써 제 2금속층인 알루미늄과의 반응을 억제하여 TiAl3층의 생성을 억제하여 제 2금속층의 유효면적을 늘려 전체적인 저항을 줄일 수 있게 된다.After forming the contact hole, a barrier metal layer deposited on the entire surface of the contact hole to prevent electron migration of the buried metal second metal layer is formed of a Ti-Si alloy containing Si, thereby suppressing the reaction with aluminum as the second metal layer, thereby preventing TiAl3. By suppressing the formation of the layer, the effective area of the second metal layer can be increased to reduce the overall resistance.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다. 또한 본 실시예는 본 발명의 권리범위를 한정하는 것은 아니고, 단지 예시로 제시된 것이며 종래 구성과 동일한 부분은 동일한 부호 및 명칭을 사용한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.
도 3내지 도 4는 본 발명에 의한 반도체장치의 콘택 형성방법을 설명하기 위한 단면도들이다.3 to 4 are cross-sectional views illustrating a method for forming a contact of a semiconductor device according to the present invention.
도 3은 제 1금속층(10)위로 절연층(20)을 형성한 후 상부에 콘택홀(25)을 형성하기 위한 식각마스크로 감광막 패턴을 형성한 후 제 1금속층(10)이 노출되도록 절연층(20)을 식각하여 콘택홀(25)을 형성한다. 그런다음 전면에 장벽금속층으로 Ti-Si층(36)을 증착하여 이후 매립되는 금속이 절연층(20)으로 확산되는 것을 방지하도록 한다.FIG. 3 shows that the first metal layer 10 is exposed after forming the photoresist pattern as an etching mask for forming the contact hole 25 thereon after forming the insulating layer 20 on the first metal layer 10. 20 is etched to form contact holes 25. Then, the Ti-Si layer 36 is deposited as a barrier metal layer on the front surface to prevent the metal embedded thereafter from being diffused into the insulating layer 20.
이때, Ti-Si층(36)은 Ti에 0.5∼10% 까지 Si가 함유된 Ti-Si합금을 타겟으로 상온 이나 냉각장치를 이용하여 0℃ 이하의 온도에서 물리적 기상 증착 방식에 의해 200∼1500Å 정도로 증착한다.At this time, the Ti-Si layer 36 is targeted to a Ti-Si alloy containing 0.5 to 10% Si in Ti by physical vapor deposition at a temperature of 0 ° C. or below by using a room temperature or a cooling device. Deposit to the extent.
그런다음, 도 2와 같이 제 2금속층(40)을 알루미늄을 콘택홀(25) 전면에 3000∼10000Å 두께로 증착하여 콘택홀(25)을 매립한다.Next, as shown in FIG. 2, the second metal layer 40 is deposited to have a thickness of 3000 to 10000 mm over the entire surface of the contact hole 25 to fill the contact hole 25.
이때 제 2금속층(40)인 알루미늄을 증착시키는 방법으로 여러 가지가 있다.In this case, there are various methods of depositing aluminum, which is the second metal layer 40.
첫째, 먼저 알루미늄을 증착한 후 불활성 기체를 사용하여 웨이퍼에 열을 공급하여 웨이퍼를 승온시켜 열에너지에 의해 알루미늄이 콘택홀(25) 내부로 이동하도록 하여 증착한다.First, aluminum is first deposited, and then heat is supplied to the wafer using an inert gas to heat up the wafer so that aluminum is moved into the contact hole 25 by thermal energy.
둘째, 일차적으로 낮은 파워로 알루미늄을 증착하고, 이차적으로 높은 파워로 알루미늄을 증착한 후, 히터의 복사열에 의해 알루미늄이 콘택홀내로 흘러들어가 완전히 매립되도록 히터의 온도를 450℃∼600℃로 유지하여 증착한다.Second, after depositing aluminum at low power, and secondly depositing aluminum at high power, the temperature of the heater is maintained at 450 ° C to 600 ° C so that aluminum flows into the contact hole by the radiant heat of the heater and is completely embedded. Deposit.
셋째, 일차적으로 높은 파워로 알루미늄을 증착하고, 불활성 기체에 의해 400℃∼500℃의 히터 열을 공급하여 웨이퍼를 승온시킨 다음 이차적으로 낮은 파워로 알루미늄을 증착한다.Third, aluminum is first deposited at a high power, and the wafer is heated by supplying a heater heat of 400 ° C to 500 ° C with an inert gas, and then aluminum is deposited at a second low power.
위와 같이 여러 가지 방법으로 콘택홀(25)을 형성할 때 알루미늄이 콘택홀 (25)내부로 완전히 매립되도록 고온공정을 수행하게 되는때 이때 장벽금속층의 Ti-Si층(36)과 반응을 일으켜 도 4와 같이 TiAl3층(38)이 형성된다.When the contact hole 25 is formed in various ways as described above, when a high temperature process is performed such that aluminum is completely embedded in the contact hole 25, the reaction may be caused by the Ti-Si layer 36 of the barrier metal layer. TiAl 3 layer 38 is formed as shown in FIG.
그러나, 이때 형성된 TiAl3층(38)은 도 2의 TiAl3층(34)과 비교할 때 두께와 균일도에서 차이가 남을 알 수 있다. 즉, 장벽금속층에 함유된 Si로 인해 반응이 억제되어 얇게 균일하게 형성됨을 알 수 있다.However, it can be seen that the TiAl 3 layer 38 formed at this time has a difference in thickness and uniformity compared to the TiAl 3 layer 34 of FIG. 2. That is, it can be seen that due to Si contained in the barrier metal layer, the reaction is suppressed and is formed thinly and uniformly.
상기한 바와 같이 본 발명은 콘택홀을 형성한 후 전자이동을 방지하기 위한 장벽금속층과 콘택홀에 매립되는 매립금속과의 반응을 억제하기 위해 장벽금속층을 Si가 함유된 물질을 사용하여 매립금속과의 반응을 억제함으로써 균일하고 얇은 화합물이 형성되도록 하여 금속층의 유효면적을 증대시킬 수 있으며, 전체적인 저항을 줄일 수 있어 소자의 특성을 향상시킬 수 있다는 이점이 있다.As described above, the present invention provides a barrier metal layer using a material containing Si to suppress the reaction between the barrier metal layer and the buried metal buried in the contact hole after forming the contact hole. By suppressing the reaction of the metal layer to form a uniform and thin compound can increase the effective area of the metal layer, there is an advantage that the overall resistance can be reduced to improve the characteristics of the device.
Claims (5)
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| KR1019980062555A KR20010008441A (en) | 1998-12-30 | 1998-12-30 | Method for forming contact of semiconductor device |
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| KR1019980062555A KR20010008441A (en) | 1998-12-30 | 1998-12-30 | Method for forming contact of semiconductor device |
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| JPH10261597A (en) * | 1997-03-19 | 1998-09-29 | Fujitsu Ltd | Semiconductor device and its manufacture |
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1998
- 1998-12-30 KR KR1019980062555A patent/KR20010008441A/en not_active Application Discontinuation
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| JPH04343417A (en) * | 1991-05-21 | 1992-11-30 | Sharp Corp | Semiconductor device and its manufacture |
| US5770520A (en) * | 1996-12-05 | 1998-06-23 | Lsi Logic Corporation | Method of making a barrier layer for via or contact opening of integrated circuit structure |
| EP0866499A2 (en) * | 1997-03-18 | 1998-09-23 | Applied Materials, Inc. | Silicon-doped titanium wetting layer for aluminum plug |
| JPH10261597A (en) * | 1997-03-19 | 1998-09-29 | Fujitsu Ltd | Semiconductor device and its manufacture |
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