KR20010005155A - Fabricating method for semiconductor device - Google Patents
Fabricating method for semiconductor device Download PDFInfo
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- KR20010005155A KR20010005155A KR1019990025953A KR19990025953A KR20010005155A KR 20010005155 A KR20010005155 A KR 20010005155A KR 1019990025953 A KR1019990025953 A KR 1019990025953A KR 19990025953 A KR19990025953 A KR 19990025953A KR 20010005155 A KR20010005155 A KR 20010005155A
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- film
- etching
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- insulating film
- layer
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- 238000000034 method Methods 0.000 title claims abstract description 57
- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 238000005530 etching Methods 0.000 claims abstract description 47
- 238000002955 isolation Methods 0.000 claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 125000006850 spacer group Chemical group 0.000 claims abstract description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 8
- 150000004767 nitrides Chemical class 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 239000010408 film Substances 0.000 description 77
- 239000010410 layer Substances 0.000 description 77
- 229920002120 photoresistant polymer Polymers 0.000 description 13
- 239000005360 phosphosilicate glass Substances 0.000 description 6
- 238000009413 insulation Methods 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로서, 특히 소자분리막 형성후 소자분리마스크로 사용한 절연막 패턴을 제거하지 않고 그대로 사용하여 별도의 마스크공정없이 랜딩콘택플러그를 형성하는 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of fabricating a semiconductor device in which a landing contact plug is formed without using an additional mask process without removing the insulating film pattern used as the device isolation mask after forming the device isolation film. .
최근의 반도체장치의 고집적화 추세는 미세 패턴 형성 기술의 발전에 큰 영향을 받고 있으며, 반도체장치의 제조공정 중에서 식각 또는 이온주입 공정 등의 마스크로 매우 폭 넓게 사용되는 감광막 패턴의 미세화가 필수 요건이다.The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, is essential in the manufacturing process of semiconductor devices.
상기 감광막 패턴의 분해능(R) 은 축소노광장치의 광원의 파장(λ) 및 공정 변수(k)에 비례하고, 노광 장치의 렌즈 구경(numerical aperture : NA, 개구수)에 반비례한다.The resolution R of the photoresist pattern is proportional to the wavelength λ of the light source of the reduction exposure apparatus and the process variable k, and inversely proportional to the numerical aperture NA of the exposure apparatus.
[ R = k*λ/NA, R = 해상도, λ = 광원의 파장, NA = 개구수][R = k * λ / NA, R = resolution, λ = wavelength of light source, NA = numerical aperture]
여기서, 상기 축소노광장치의 광분해능을 향상시키기 위하여 광원의 파장을 감소시키게 되며, 예를 들어 파장이 436 및 365nm인 G-라인 및 i-라인 축소노광장치는 공정 분해능이 각각 약 0.7, 0.5㎛ 정도가 한계이고, 0.5㎛이하의 미세 패턴을 형성하기 위해 파장이 작은 원자외선(deep ultra violet : DUV), 예를 들어 파장이 248㎚인 KrF 레이저나 193㎚인 ArF 레이저를 광원으로 사용하는 노광장치를 이용하거나, 공정상의 방법으로는 노광마스크(photo mask)를 위상 반전 마스크(phase shift mask)를 사용하는 방법과, 이미지 콘트라스트를 향상시킬 수 있는 별도의 박막을 웨이퍼 상에 형성하는 씨.이.엘.(contrast enhancement layer, 이하 CEL이라 함)방법이나 두 층의 감광막 사이에 SOG 등의 중간층을 개재시킨 삼층레지스트(tri layer resist, TLR) 방법 또는 감광막의 상측에 선택적으로 실리콘을 주입시키는 실리레이션 방법 등이 개발되어 분해능 한계치를 낮추고 있다.Here, the wavelength of the light source is reduced in order to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of about 0.7 and 0.5 µm, respectively. Exposure is limited using a deep ultra violet (DUV) light, for example, a KrF laser having a wavelength of 248 nm or an ArF laser having a wavelength of 193 nm as a light source to form a fine pattern of 0.5 µm or less. As an apparatus or process method, a photo mask is used as a phase shift mask, and a separate thin film is formed on the wafer to improve image contrast. L. (contrast enhancement layer, CEL) method, tri-layer resist (TLR) method in which an intermediate layer such as SOG is interposed between two layers of photoresist, or selectively on top of the photoresist. Silicate methods for injecting cones have been developed to lower the resolution limit.
또한, 상하의 도전배선을 연결하는 콘택홀은 소자가 고집적화되어감에 따라 자체의 크기와 주변배선과의 간격이 감소되고, 콘택홀의 지름과 깊이의 비인 에스펙트비(aspect ratio)가 증가하기 때문에 다층의 도전배선을 구비하는 고집적 반도체소자에서는 콘택을 형성하기 위하여 제조 공정에서의 마스크들간의 정확하고 엄격한 정렬이 요구되어 공정여유도가 감소되는 문제점이 있다.In addition, the contact holes connecting the upper and lower conductive wirings have a multi-layered structure due to the high integration of devices, and the gap between the size of the contact holes and the peripheral wirings is reduced and the aspect ratio, which is the ratio of the diameter and depth of the contact holes, is increased. In the highly integrated semiconductor device having the conductive wiring of, a precise and strict alignment between the masks in the manufacturing process is required to form a contact, thereby reducing the process margin.
상기와 같이 소자의 고집적화에 따른 문제점을 해결하기 위하여 도전배선을 서로 연결시키고, 공정여유도를 증가시키기 위하여 비트라인과 저장전극 콘택을 형성하는 경우 랜딩콘택플러그를 사용하게 된다. 상기 랜딩콘택플러그는 게이트전극을 형성한 다음 비트라인 콘택과 저장전극 콘택으로 예정되는 부분을 노출시키는 콘택홀이 구비된 층간절연막을 형성한 후, 전면에 다결정실리콘층을 형성한 다음, 화학적 기계적 연마(chemical mechanical polishing, 이하 CMP 라 함)공정으로 제거하여 비트라인 콘택과 저장전극 콘택으로 예정되는 부분과 접속되는 랜딩콘택플러그를 형성한다.In order to solve the problems caused by the high integration of the device as described above, the landing contact plug is used when the conductive lines are connected to each other and the bit line and the storage electrode contact are formed to increase the process margin. The landing contact plug forms a gate electrode, and then forms an interlayer insulating film having a contact hole exposing a portion intended as a bit line contact and a storage electrode contact, and then forms a polysilicon layer on the front surface, followed by chemical mechanical polishing It is removed by a chemical mechanical polishing (hereinafter referred to as CMP) process to form a landing contact plug that is connected to a portion intended as a bit line contact and a storage electrode contact.
그러나, 상기와 같이 종래기술에 따른 반도체소자의 제조방법은, 반도체소자가 고집적화되어 감에 따라 게이트 전극 형성 후 랜딩콘택플러그의 형성시 상기 게이트 전극과 랜딩콘택플러그가 쇼트되는 것을 방지하기 어렵고, 소자분리공정을 위하여 반도체기판을 식각하여 트랜치를 형성한 후 절연막을 형성한 다음 상기 절연막을 CMP공정으로 제거하여 소자분리막을 형성하고, 게이트전극을 형성한 다음 후속공정으로 층간절연막을 형성하고 CMP공정으로 평탄화공정을 실시하는 등의 복잡한 공정을 실시해야 하는 문제점이 있다.However, as described above, in the method of manufacturing a semiconductor device according to the related art, it is difficult to prevent the gate electrode and the landing contact plug from shorting when the landing contact plug is formed after the formation of the gate electrode as the semiconductor device is highly integrated. To form a trench by etching a semiconductor substrate for a separation process, an insulating film is formed, and then the insulating film is removed by a CMP process to form a device isolation film, a gate electrode is formed, and an interlayer insulating film is formed by a subsequent process by a CMP process. There is a problem that a complex process such as a planarization process should be performed.
본 발명은 상기한 종래기술의 문제점들을 해결하기 위하여, 반도체기판 상부에 소자분리마스크로 사용되는 절연막 패턴을 소자분리막 형성후에도 제거하지 않고, 상기 절연막 패턴에 게이트전극으로 예정되는 부분을 노출시키는 홈을 형성한 다음, 게이트전극을 형성하고 상기 절연막 패턴을 제거하여 랜딩콘택플러그가 형성될 오픈영역을 형성하여 별도의 콘택마스크를 형성하지 않고도 랜딩콘택플러그를 형성하고 그에 의해 단순한 공정을 진행할 수 있는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, a groove for exposing a portion intended as a gate electrode is exposed to the insulating layer pattern without removing the insulating layer pattern used as the device isolation mask on the semiconductor substrate even after forming the isolation layer. After forming, the gate electrode is formed and the insulating layer pattern is removed to form an open region in which the landing contact plug is to be formed, thereby forming a landing contact plug without a separate contact mask, thereby allowing a simple process to be performed. Its purpose is to provide a method of manufacturing.
도 1 은 본 발명에 따른 반도체소자의 제조방법에 의한 레이아웃도.1 is a layout diagram of a method of manufacturing a semiconductor device according to the present invention;
도 2 내지 도 13 은 본 발명의 제1실시예에 따른 반도체소자의 제조방법을 도시한 단면도.2 to 13 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.
도 14 내지 도 18 은 본 발명의 제2실시예에 따른 반도체소자의 제조방법을 도시한 단면도.14 to 18 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.
〈도면의 주요부분에 대한 부호 설명〉<Explanation of symbols on main parts of the drawing>
11, 100 : 반도체기판 13, 110 : 버퍼층11, 100: semiconductor substrate 13, 110: buffer layer
15, 120 : 제1절연막 17 : 제1감광막 패턴15, 120: first insulating film 17: first photosensitive film pattern
19 : 트렌치 21, 130 : 제2절연막19: trench 21, 130: second insulating film
23 : 제2감광막 패턴 25, 131, 132 : 소자분리막23: second photosensitive film pattern 25, 131, 132: device isolation film
27, 140 : 게이트절연막 29, 150 : 도전층27, 140: gate insulating film 29, 150: conductive layer
31, 160 : 마스크절연막 패턴 33, 170 : 제3절연막 스페이서31 and 160: mask insulating film pattern 33 and 170: third insulating film spacer
35, 180 : 랜딩콘택플러그35, 180: Landing contact plug
이상의 목적을 달성하기 위하여 본 발명에 따른 반도체소자의 제조방법은,In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention,
반도체기판 상부에 소자분리영역으로 예정되는 부분을 노출시키는 절연막 패턴을 형성하고, 상기 절연막 패턴을 식각마스크로 상기 반도체기판을 식각하여 트렌치를 형성하는 공정과,Forming an insulating layer pattern over the semiconductor substrate to expose a predetermined portion as a device isolation region, and forming a trench by etching the semiconductor substrate using the insulating layer pattern as an etching mask;
상기 트렌치를 매립하는 소자분리막을 형성하는 공정과,Forming a device isolation film to fill the trench;
게이트전극으로 예정되는 부분을 노출시키는 게이트전극 마스크를 식각마스크로 상기 절연막 패턴을 식각하여 틈을 형성하는 공정과,Etching the insulating film pattern with an etching mask using a gate electrode mask that exposes a predetermined portion of the gate electrode, and forming a gap;
상기 틈의 소정두께를 매립하는 게이트절연막과 게이트전극을 형성하는 공정과,Forming a gate insulating film and a gate electrode to fill a predetermined thickness of the gap;
전체표면 상부에 상기 절연막 패턴과 식각선택비를 갖는 마스크절연막을 형성하는 공정과,Forming a mask insulating film having an etching selectivity with the insulating film pattern on the entire surface;
상기 마스크절연막을 식각하여 상기 틈을 완전히 매립하는 마스크절연막 패턴을 형성하는 공정과,Etching the mask insulating film to form a mask insulating film pattern that completely fills the gaps;
상기 절연막 패턴을 제거하여 상기 소자분리막과 게이트절연막/게이트전극/마스크절연막 패턴의 적층구조를 돌출시키는 공정과,Removing the insulating layer pattern to protrude the stacked structure of the device isolation layer and the gate insulating layer / gate electrode / mask insulating layer pattern;
상기 소자분리막과 적층구조의 측벽에 절연막 스페이서를 형성하는 공정과,Forming an insulating film spacer on sidewalls of the device isolation film and the stacked structure;
전체표면 상부에 랜딩콘택플러그용 도전층을 형성한 다음, 식각하여 랜딩콘택플러그를 형성하는 공정을 포함하는 것을 특징으로 한다.And forming a landing contact plug by etching the conductive contact layer for the landing contact plug on the entire surface.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1 은 본 발명에 따른 반도체소자의 제조방법에 의한 레이아웃도이고, 도 2 내지 도 13 은 본 발명의 제1실시예에 따른 반도체소자의 제조방법을 도시한 단면도로서, 도 2 내지 도 6 은 도 1 의 x축 및 y축의 단면에 따른 공정순서를 도시하고, 도 7 내지 도 13 은 도 1 의 x축 및 y'축의 단면에 따른 공정순서도를 도시한다. 상기 도 1 에서 A 영역은 활성영역, B영역은 소자분리영역, C영역은 게이트전극을 나타낸다.1 is a layout diagram illustrating a method of manufacturing a semiconductor device in accordance with the present invention, and FIGS. 2 to 13 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention. FIG. 1 shows the process sequence along the cross section of the x-axis and the y-axis, and FIGS. 7 to 13 show the process flow chart along the cross-section of the x-axis and the y 'axis of FIG. In FIG. 1, region A represents an active region, region B represents an isolation region, and region C represents a gate electrode.
먼저, 반도체기판(11) 상부에 버퍼층(13)과 제1절연막(15)의 적층구조를 형성하고, 상기 제1절연막(15) 상부에 소자분리영역으로 예정되는 부부분을 노출시키는 제1감광막 패턴(17)을 형성한다. 이때, 상기 버퍼층(13)은 LP-TEOS(low pressure tetra ethyl ortho silicate glass), PE-TEOS(plasma enhanced tetra ethyl ortho silicate glass), 고온산화막(high temperature oxide, HTO), 고밀도플라즈마산화막(high density plasma oxide, HDP) 등의 화학기상증착산화막(chemical vapor deposition oxide, 이하 CVD 산화막 이라 함) 또는 열산화막(thermal oxide) 또는 다결정실리콘층을 이용하여 50 ∼ 500Å 두께로 형성한다.First, a first photoresist film is formed on the semiconductor substrate 11 to form a stacked structure of the buffer layer 13 and the first insulating film 15, and exposes a predetermined portion of the device isolation region on the first insulating film 15. The pattern 17 is formed. In this case, the buffer layer 13 is LP-TEOS (low pressure tetra ethyl ortho silicate glass), PE-TEOS (plasma enhanced tetra ethyl ortho silicate glass), high temperature oxide (HTO), high density plasma oxide film (high density) It is formed to a thickness of 50 to 500 kW using a chemical vapor deposition oxide (hereinafter referred to as a CVD oxide film), a thermal oxide film or a polysilicon layer such as plasma oxide (HDP).
그리고, 상기 제1절연막(15)은 PE-질화막(plasma enhanced nitride), LP-질화막(low pressure nitride) 등의 질화막 또는 LP-TEOS, PE-TEOS, 고온산화막, 고밀도플라즈마산화막 등의 CVD 산화막 또는 PSG(phospho silicate glass)막 또는 BPSG(borophospho silicate glass)막을 이용하여 100 ∼ 5000Å 두께로 형성한다.The first insulating layer 15 may be a nitride film such as a PE-nitride film, a low pressure nitride film, or a CVD oxide film such as LP-TEOS, PE-TEOS, high temperature oxide film, or high density plasma oxide film. It is formed to a thickness of 100 ~ 5000Å using a PSG (phospho silicate glass) film or BPSG (borophospho silicate glass) film.
다음, 상기 제1절연막(15) 상부에 소자분리영역으로 예정되는 부분을 노출시키는 제1감광막 패턴(17)을 형성한다. (도 2 참조)Next, a first photoresist layer pattern 17 is formed on the first insulating layer 15 to expose a portion of the device isolation region. (See Figure 2)
그 다음, 상기 제1감광막 패턴(17)을 식각마스크로 사용하여 상기 적층구조 및 반도체기판(11)을 식각하여 트렌치(19)를 형성한다. 이때, 상기 트렌치(19)는 1000 ∼ 4000Å 깊이의 반도체기판(11)을 식각하여 형성된다. (도 3 참조)Next, the trench 19 is formed by etching the stacked structure and the semiconductor substrate 11 using the first photoresist pattern 17 as an etching mask. At this time, the trench 19 is formed by etching the semiconductor substrate 11 having a depth of 1000 ~ 4000Å. (See Figure 3)
다음, 상기 제1감광막 패턴(17)을 제거한다.Next, the first photoresist layer pattern 17 is removed.
한편, 상기 제1감광막 패턴(17)을 식각마스크로 상기 적층구조를 식각하여 제1절연막(15) 패턴과 버퍼층(13) 패턴을 형성하고, 상기 제1감광막 패턴(17)을 제거한 다음, 상기 제1절연막(15) 패턴을 식각마스크로 사용하여 상기 반도체기판(11)을 식각하여 트렌치(19)를 형성할 수도 있다. (도 4 참조)The first photoresist layer pattern 17 may be etched using the etching mask to form a first insulating layer 15 pattern and a buffer layer 13 pattern, and then the first photoresist layer pattern 17 may be removed. The trench 19 may be formed by etching the semiconductor substrate 11 using the first insulating layer 15 pattern as an etching mask. (See Figure 4)
다음, 전체표면 상부에 제2절연막(21)을 형성하여 상기 트렌치(19)가 매립되도록 한다. 상기 제2절연막(21)은 중온산화막(middle temperature oxide, MTO), 고온산화막, TEOS막 등의 CVD산화막, PSG막 또는 BPSG막 등을 1000 ∼ 6000Å 두께로 형성한다.Next, a second insulating layer 21 is formed on the entire surface so that the trench 19 is buried. The second insulating film 21 is formed of a CVD oxide film such as a middle temperature oxide (MTO), a high temperature oxide film, and a TEOS film, a PSG film, or a BPSG film in a thickness of 1000 to 6000 GPa.
이때, 상기 제2절연막(21)은 상기 제1절연막(15)과 식각선택비를 갖는 박막으로 형성한다.In this case, the second insulating layer 21 is formed of a thin film having an etching selectivity with the first insulating layer 15.
상기 제1절연막(15)을 질화막으로 형성하는 경우 상기 제2절연막(21)은 CVD산화막, PSG막 또는 BPSG막으로 형성할 수 있고, 상기 제1절연막(15)을 CVD 산화막으로 형성하는 경우 상기 제2절연막(21)은 PSG막 또는 BPSG막으로 형성할 수 있다. 그리고, 상기 제1절연막(15)을 PSG막 또는 BPSG막으로 형성하는 경우 제2절연막(21)은 CVD산화막으로 형성할 수 있다. (도 5 참조)When the first insulating film 15 is formed of a nitride film The second insulating film 21 may be formed of a CVD oxide film, a PSG film, or a BPSG film, and when the first insulating film 15 is formed of a CVD oxide film. The second insulating film 21 may be formed of a PSG film or a BPSG film. When the first insulating film 15 is formed of a PSG film or a BPSG film, the second insulating film 21 may be formed of a CVD oxide film. (See Figure 5)
다음, 상기 제2절연막(21)은 상기 제1절연막(15)을 식각마스크로 사용하여 식각하여 상기 트렌치(19)를 매립하는 소자분리막(25)을 형성한다. 이때, 상기 식각공정은 전면식각공정 또는 CMP공정으로 실시할 수 있다. (도 6 참조)Next, the second insulating layer 21 is etched using the first insulating layer 15 as an etch mask to form an isolation layer 25 to fill the trench 19. In this case, the etching process may be performed by a front surface etching process or a CMP process. (See Figure 6)
다음, 전체표면 상부에 게이트전극으로 예정되는 부분을 노출시키는 제2감광막 패턴(23)을 형성한다. (도 7 참조)Next, a second photoresist pattern 23 is formed on the entire surface to expose a portion, which is intended as a gate electrode. (See Figure 7)
그 다음, 상기 제2감광막 패턴(23)을 식각마스크로 사용하여 상기 제1절연막(15)과 버퍼층(13)을 식각하여 게이트 전극이 형성될 틈을 형성하고, 상기 제2감광막 패턴(23)을 제거한다. 상기 식각공정으로 도 1 의 y'축의 단면을 보면 소자분리영역인 B부분의 소자분리막(25)은 제1절연막(15)과 동시에 제거되어 단차가 낮아진다. (도 8 참조)Next, the first insulating layer 15 and the buffer layer 13 are etched using the second photoresist pattern 23 as an etch mask to form a gap in which a gate electrode is formed, and the second photoresist pattern 23 is formed. Remove it. Referring to the cross-section of the y 'axis of FIG. 1 by the etching process, the device isolation layer 25 of the portion B, which is the device isolation region, is removed at the same time as the first insulating layer 15 to reduce the level difference. (See Figure 8)
다음, 전체표면 상부에 게이트 절연막(27)과 도전층(29)을 순차적으로 형성한 다음, 전면식각공정을 실시하여 상기 틈의 일부에만 게이트 절연막(27)과 도전층(29)이 형성되게 한다. 상기 도전층(29)은 다결정실리콘층, 다결정실리콘층/텅스텐실리사이드막, 티타늄실리사이드막 또는 텅스텐막을 사용하여 500 ∼ 2000Å 두께로 형성한다. (도 9 참조)Next, the gate insulating layer 27 and the conductive layer 29 are sequentially formed on the entire surface, and then the entire surface etching process is performed to form the gate insulating layer 27 and the conductive layer 29 only in a part of the gap. . The conductive layer 29 is formed to have a thickness of 500 to 2000 mm by using a polysilicon layer, a polycrystalline silicon layer / tungsten silicide film, a titanium silicide film or a tungsten film. (See FIG. 9)
그 다음, 전체표면 상부에 마스크절연막을 형성하고, 상기 마스크절연막을 전면식각공정 또는 CMP공정으로 식각하여 상기 틈을 완전히 메우는 마스크절연막 패턴(31)을 형성한다.Next, a mask insulating film is formed over the entire surface, and the mask insulating film is etched by a front etching process or a CMP process to form a mask insulating film pattern 31 which completely fills the gap.
이때, 상기 마스크절연막 패턴(31)은 PE-질화막, LP-질화막 등의 질화막 또는 LP-TEOS, PE-TEOS, 고온산화막, 고밀도플라즈마산화막 등의 CVD 산화막으로 형성할 수 있고, 상기 제1절연막(15)과 식각선택비를 갖는 박막을 사용하여 100 ∼ 5000Å 두께로 형성한다. (도 10 참조)In this case, the mask insulating layer pattern 31 may be formed of a nitride layer such as a PE-nitride layer or an LP-nitride layer, or a CVD oxide layer such as LP-TEOS, PE-TEOS, high temperature oxide layer, or high density plasma oxide layer. 15) and a thin film having an etching selectivity to form a thickness of 100 ~ 5000Å. (See FIG. 10)
다음, 상기 제1절연막(15) 패턴을 제거하여 반도체기판(11)을 노출시킨다. 상기 공정후 반도체기판(11) 상에는 돌출되어 형성된 소자분리막(25)과 게이트절연막(27), 도전층(29) 및 마스크절연막 패턴(31)의 적층구조로된 게이트전극이 형성된다.Next, the first insulating layer 15 pattern is removed to expose the semiconductor substrate 11. After the process, a gate electrode having a stacked structure of the device isolation layer 25, the gate insulation layer 27, the conductive layer 29, and the mask insulation layer pattern 31 formed protruding from the semiconductor substrate 11 is formed.
그 다음, 상기 게이트전극 양측 반도체기판(11)에 저농도의 불순물을 이온주입하여 LDD영역(도시안됨)을 형성한다. (도 11 참조)Next, a low concentration of impurities are implanted into the semiconductor substrate 11 on both sides of the gate electrode to form an LDD region (not shown). (See Figure 11)
다음, 상기 소자분리막(25) 및 게이트전극의 측벽에 제3절연막 스페이서(33)를 형성한다. 이때, 상기 제3절연막 스페이서(33)는 제3절연막(도시안됨)인 질화막 또는 산화막을 100 ∼ 1000Å 두께로 형성한 다음, 전면식각공정을 실시하여 형성된다.Next, a third insulating layer spacer 33 is formed on sidewalls of the device isolation layer 25 and the gate electrode. In this case, the third insulating film spacer 33 is formed by forming a nitride film or an oxide film as a third insulating film (not shown) to a thickness of 100 to 1000 ∼, and then performing an entire surface etching process.
그 다음, 상기 제3절연막 스페이서(33) 양측의 반도체기판(11)에 고농도의 불순물을 이온주입하여 소오스/드레인영역(도시안됨)을 형성한다. (도 12 참조)Next, a high concentration of impurities are implanted into the semiconductor substrate 11 on both sides of the third insulating layer spacer 33 to form a source / drain region (not shown). (See Figure 12)
그 다음, 전체표면 상부에 랜딩콘택플러그용 다결정실리콘층을 100 ∼ 5000Å 두께로 형성한다.Then, a polysilicon layer for landing contact plug is formed on the entire surface to a thickness of 100 to 5000 mm 3.
그 후, 상기 랜딩콘택플러그용 다결정실리콘층을 CMP공정이나 전면식각공정으로 식각하여 랜딩콘택플러그(35)를 형성한다.Thereafter, the landing contact plug polycrystalline silicon layer is etched by a CMP process or an entire surface etching process to form a landing contact plug 35.
또한, 상기 랜딩콘택플러그(35)는 상기 제1절연막(15) 패턴이 제거되어 노출된 반도체기판(11)에 선택적으로 다결정실리콘층을 성장시켜 형성할 수도 있다. (도 13 참조)In addition, the landing contact plug 35 may be formed by selectively growing a polysilicon layer on the semiconductor substrate 11 to which the pattern of the first insulating layer 15 is removed. (See FIG. 13)
도 14 내지 도 18 은 본 발명의 제2실시예에 따른 반도체소자의 제조방법을 도시한 단면도로서, 도 5 까지의 공정을 실시한 다음, 게이트전극으로 예정되는 부분을 노출시키는 게이트전극 마스크를 식각마스크로 사용하여 제2절연막(130), 제1절연막(120) 및 버퍼층(110)을 식각하여 게이트전극이 형성될 틈을 형성한다.14 to 18 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention. After performing the process up to FIG. 5, an etching mask is performed on the gate electrode mask exposing a predetermined portion of the gate electrode. The second insulating layer 130, the first insulating layer 120, and the buffer layer 110 are etched to form a gap in which the gate electrode is to be formed.
다음, 제1실시예에서와 같이 게이트전극 및 마스크절연막 패턴(160)을 형성한 다음, 상기 제1절연막(120) 패턴을 식각하여 반도체기판(100)을 노출시킨다. 상기 식각공정은 후속공정에서 랜딩콘택플러그가 형성될 마진을 증가시키기 위하여 상기 소자분리막(132)이 등방성식각되도록 실시하여 상기 소자분리막(132)의 측벽이 식각되게 한다. (도 14, 15, 16 참조)Next, as in the first embodiment, the gate electrode and the mask insulation layer pattern 160 are formed, and then the pattern of the first insulation layer 120 is etched to expose the semiconductor substrate 100. In the etching process, the device isolation layer 132 is isotropically etched to increase the margin for forming the landing contact plug in a subsequent process so that the sidewall of the device isolation layer 132 is etched. (See Figures 14, 15 and 16)
그 후, 제1실시예에서와 같은 후속공정을 실시하여 랜딩콘택플러그(180)를 형성한다. (도 17, 18 참조)Thereafter, a subsequent contact as in the first embodiment is performed to form the landing contact plug 180. (See Figures 17 and 18)
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 제조방법은, 반도체기판 상부에 소자분리마스크로 사용되는 절연막 패턴을 형성한 다음, 상기 절연막 패턴을 식각마스크로 반도체기판을 식각하여 트렌치를 형성하고 상기 트렌치를 매립하는 소자분리막을 형성한 후, 게이트전극 마스크를 식각마스크로 상기 절연막 패턴을 식각하여 게이트 전극이 형성될 홈을 형성하고, 상기 홈내부에 게이트전극과 마스크절연막 패턴을 형성한 다음, 상기 절연막 패턴을 제거하여 상기 소자분리막과 게이트전극과 마스크절연막 패턴 적층구조를 돌출시킨 후 상기 소자분리막과 적층구조의 측벽에 절연막 스페이서를 형성한 다음, 전면에 랜딩콘택플러그용 도전층을 형성하고 전면식각하여 랜딩콘택플러그를 형성함으로써 후속공정시 실시되는 콘택공정시 미스얼라인에 의한 쇼트현상을 방지하고, 게이트전극 형성후 실시되는 평탄화공정을 생략할 수 있고, 별도의 사진공정 없이 랜딩콘택플러그를 형성하여 공정을 단순하게 하는 이점이 있다.As described above, in the method of manufacturing a semiconductor device according to the present invention, an insulating film pattern used as an isolation mask is formed on a semiconductor substrate, and the trench is formed by etching the semiconductor substrate using the insulating film as an etching mask. After forming a device isolation layer to fill the trench, a groove in which the gate electrode is formed is formed by etching the insulating layer pattern using a gate electrode mask as an etch mask, and forming a gate electrode and a mask insulating layer pattern in the groove. After removing the insulating film pattern, the device isolation film, the gate electrode and the mask insulating film pattern layered structure are protruded, and an insulating film spacer is formed on the sidewalls of the device isolation film and the stacked structure, and then a conductive contact layer for the landing contact plug is formed on the entire surface, and the entire surface is etched. During the subsequent process by forming a landing contact plug It is possible to prevent short phenomenon caused by misalignment, to omit the planarization process performed after the formation of the gate electrode, and to simplify the process by forming a landing contact plug without a separate photo process.
Claims (14)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990025953A KR20010005155A (en) | 1999-06-30 | 1999-06-30 | Fabricating method for semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019990025953A KR20010005155A (en) | 1999-06-30 | 1999-06-30 | Fabricating method for semiconductor device |
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