KR20010004799A - Method for manufacturing capacitor of a semiconductor device - Google Patents

Method for manufacturing capacitor of a semiconductor device Download PDF

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Publication number
KR20010004799A
KR20010004799A KR1019990025518A KR19990025518A KR20010004799A KR 20010004799 A KR20010004799 A KR 20010004799A KR 1019990025518 A KR1019990025518 A KR 1019990025518A KR 19990025518 A KR19990025518 A KR 19990025518A KR 20010004799 A KR20010004799 A KR 20010004799A
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South Korea
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film
capacitor
mps
contact hole
tungsten silicide
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KR1019990025518A
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Korean (ko)
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KR100322881B1 (en
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우상호
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김영환
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material

Abstract

PURPOSE: A method for manufacturing a capacitor of a semiconductor device is provided to increase the capacitance of a cell by enlarging a surface area of a tungsten silicide layer. CONSTITUTION: A capacitor contact hole is formed on an active area of a semiconductor substrate(10). A contact electrode(20) is formed by filling the capacitor contact hole. Then, a tungsten silicide film(30) and an MPS film are sequentially formed on the surface of the semiconductor substrate(10). Then, the tungsten silicide film(30) is etched by using the MPS film as an etching mask. Then, the MPS film is removed. A lower electrode is patterned through the lower electrode mask. After patterning the lower electrode, a dielectric film is formed. Then, an upper electrode is formed on the dielectric film.

Description

반도체장치의 커패시터 제조방법 {METHOD FOR MANUFACTURING CAPACITOR OF A SEMICONDUCTOR DEVICE}METHODS FOR MANUFACTURING CAPACITOR OF A SEMICONDUCTOR DEVICE

본 발명은 반도체장치의 커패시터 제조방법에 관한 것으로서, 보다 상세하게는 커패시터의 하부 전하저장 전극을 거친 표면을 갖는 금속계열을 이용하여 셀 커패시턴스를 증대시키도록 한 것을 특징으로 하는 반도체장치의 커패시터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and more particularly, to a method of manufacturing a capacitor of a semiconductor device, wherein the cell capacitance is increased by using a metal series having a surface that passes through a lower charge storage electrode of the capacitor. It is about.

일반적으로, 반도체장치의 종류에는 여러 가지가 있으며, 이 반도체장치 내에 형성되는 트랜지스터 및 캐패시터등을 구성시키는 방법에는 다양한 제조기술이 사용되고 있으며 특히, 개패시터의 경우에는 적은 면적에도 불구하고 정전용량이 증가되어야 한다. 따라서 이러한 문제점들을 해결하기 위해 적은 면적에서도 표면적을 최대로 할 수 있는 구조를 연구하게 된다.In general, there are many kinds of semiconductor devices, and various manufacturing techniques are used to configure transistors, capacitors, and the like formed in the semiconductor device. In particular, in the case of a capacitor, capacitance increases despite a small area. Should be. Therefore, in order to solve these problems, the structure that can maximize the surface area in a small area is studied.

현재 반도체 소자는 고집적화가 이루어질수록 캐패시터의 면적은 급격하게 감소되고 있기 때문에 기억소자의 동작에 필요한 전하 즉, 단위 면적에 확보되는 캐패시턴스를 더욱 증가시켜야만 한다.At present, since the area of the capacitor is rapidly decreasing as the semiconductor device is highly integrated, the charge required for the operation of the memory device, that is, the capacitance secured in the unit area, must be further increased.

한편, 메모리 셀에 사용되는 캐패시터의 기본 구조는 전하저장전극용 하부 전극, 유전막 및 플레이트(plate)용 상부전극으로 구성된다. 이러한 구조를 가지는 캐패시터는 작은 면적 내에서 보다 큰 고정전용량을 얻기 위해서 첫째 얇은 유전막 두께를 확보하거나, 둘째 3차원적인 캐패시터의 구조를 통해서 유효 면적을 증가시키거나, 셋째 유전율이 높은 물질을 사용하여 유전막을 형성하는 등의 몇 가지 조건이 만족되어야만 한다.Meanwhile, the basic structure of a capacitor used in a memory cell is composed of a lower electrode for a charge storage electrode, a dielectric film, and an upper electrode for a plate. Capacitors with this structure can be used to secure the first thin dielectric film thickness, to increase the effective area through the structure of three-dimensional capacitors, or to use materials with high dielectric constants in order to obtain a larger fixed capacitance in a small area. Several conditions must be met, such as forming a dielectric film.

도1은 일반적으로 사용되고 있는 캐패시터의 구조를 나타낸 단면도로서 (a)는 핀구조의 캐패시터를 나타낸 단면도이고 (b)는 실린더구조의 캐패시터를 나타낸 단면도이다.1 is a cross-sectional view showing the structure of a capacitor generally used, (a) is a cross-sectional view showing a capacitor of the fin structure (b) is a cross-sectional view showing a capacitor of the cylinder structure.

위와 같이 캐패시터의 구조의 변형은 동일한 크기내에서 넓은 단면적을 갖을 수 있도록 하기 위한 것이다.The deformation of the structure of the capacitor as described above is intended to have a large cross-sectional area within the same size.

위의 핀구조의 전하저장전극은 후속공정에 토폴로지를 크게주지 않는 장점이 있는 반면, 실린더구조에 비해 공정이 복잡한 단점을 가지고 있어 최근에는 실린더구조로 전하저장전극을 형성하는 추세다.The above fin structured charge storage electrode has the advantage of not giving a large topology to a subsequent process, while the process has a complicated disadvantage compared to the cylinder structure, and in recent years, the charge storage electrode has a trend of forming a cylinder structure.

그런데, 전하저장전극은 반도체장치가 고집적화됨에 따라 더 많은 정전용량을 요구하는데 금속전극을 이용하여 전하저장전극을 형성할 경우 단순하게 적재하는 방식이외는 제시된 바 없으며 금속전극 상부에 고유전율의 유전체막을 형성하여도 소자에서 요구하는 충분한 용량의 셀커패시턴스를 확보하는 것은 아주 어렵다는 문제점이 있다.However, the charge storage electrode requires more capacitance as the semiconductor device is highly integrated. However, when the charge storage electrode is formed using the metal electrode, a charge storage electrode has not been proposed except a simple loading method. Even if formed, there is a problem that it is very difficult to secure a cell capacitance of sufficient capacity required by the device.

본 발명은 상기와 같은 문제점을 해결하기 위해 창작된 것으로서, 본 발명의 목적은 커패시터의 하부 전하저장전극으로 금속계열을 사용할 때 하부 전하저장전극의 표면에 미세한 요철이 형성되도록 하여 셀 커패시턴스를 증가시킬 수 있도록 한 커패시터의 제조방법을 제공함에 있다.The present invention has been made to solve the above problems, and an object of the present invention is to increase the cell capacitance by forming fine irregularities on the surface of the lower charge storage electrode when the metal series is used as the lower charge storage electrode of the capacitor. The present invention provides a method of manufacturing a capacitor.

도1은 일반적으로 사용되고 있는 캐패시터의 구조를 나타낸 단면도이다.1 is a cross-sectional view showing the structure of a capacitor generally used.

도 2 내지 도 5는 본 실시예에 의한 반도체장치의 커패시터 제조 방법을 설명하기 위한 단면도들이다.2 to 5 are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to the present embodiment.

- 도면의 주요부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawings-

10 : 기판 20 : 콘택전극10: substrate 20: contact electrode

30 : 텅스텐 실리사이드 40 : MPS막30: tungsten silicide 40: MPS film

상기와 같은 목적을 실현하기 위한 본 발명은 반도체기판의 활성영역에 캐패시터 콘택홀을 형성하는 단계와, 캐패시터 콘택홀을 매립하여 콘택전극을 형성하는 단계와, 결과물 전면에 텅스텐 실리사이드막과 MPS막을 순차적으로 형성하는 단계와, MPS막을 마스크로 텅스텐 실리사이드막을 식각하는 하는 단계와, 텅스텐 실리사이드막을 식각한 후 MPS막을 제거하는 단계와, 하부전극 마스크를 통해 하부전극을 패터닝하는 단계와, 하부전극을 패터닝한 다음 유전체막을 형성한 후 상부전극을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.According to the present invention, a capacitor contact hole is formed in an active region of a semiconductor substrate, a contact electrode is formed by filling a capacitor contact hole, and a tungsten silicide layer and an MPS layer are sequentially formed on the entire surface of the resultant. Forming a layer; etching the tungsten silicide layer using the MPS layer as a mask; removing the MPS layer after etching the tungsten silicide layer; patterning the lower electrode through the lower electrode mask; and patterning the lower electrode And then forming an upper electrode after the dielectric film is formed.

위와 같이 이루어진 본 발명은 텅스텐 실리사이드막위로 미세한 요철이 있는 MPS막을 형성한 후 이 MPS막을 마스크로 텅스텐 실리사이드막을 식각하게 되면 MPS박의 요철에 따라 텅스텐 실리사이드막에도 요철이 형성되도록 하여 텅스텐 실리사이드막의 표면적을 증대시켜 전하저장 면적을 증가시켜 셀 커패시턴스를 증대시킬 수 있도록 한다.According to the present invention made as described above, when the MPS film having fine unevenness is formed on the tungsten silicide film and the tungsten silicide film is etched using the MPS film as a mask, the surface area of the tungsten silicide film is formed by forming the unevenness in the tungsten silicide film according to the unevenness of the MPS foil. It increases the charge storage area to increase the cell capacitance.

이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다. 또한 본 실시예는 본 발명의 권리범위를 한정하는 것은 아니고, 단지 예시로 제시된 것이다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, this embodiment is not intended to limit the scope of the present invention, but is presented by way of example only.

도 2 내지 도 5는 본 실시예에 의한 반도체장치의 커패시터 제조 방법을 설명하기 위한 단면도들이다.2 to 5 are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to the present embodiment.

도 2는 반도체기판(10)의 활성영역에 캐패시터 콘택홀을 형성하고 콘택홀을 매립하여 콘택전극(20)을 형성한 다음 전면에 텅스텐 실리사이드막(30)을 형성한 상태를 나타낸 단면도이다.FIG. 2 is a cross-sectional view illustrating a state in which a capacitor contact hole is formed in an active region of the semiconductor substrate 10, a contact electrode is filled to form a contact electrode 20, and a tungsten silicide layer 30 is formed on the entire surface of the semiconductor substrate 10.

이때 콘택홀을 매립할 때 선택적인 에피텍셜 공정을 이용하여 에피텍셜 폴리실리콘을 성장시켜 매립한다. 또한, 콘택홀 전면에 도핑된 폴리실리콘막을 형성한 다음 에치백공정을 이용하여 콘택홀을 매립하기도 한다.At this time, when filling contact holes, epitaxial polysilicon is grown by using an epitaxial process. In addition, a doped polysilicon film is formed on the entire contact hole, and then the contact hole is buried using an etch back process.

도 3은 도2의 텅스텐 실리사이드막(30) 전면에 MPS막(40)을 형성한 상태를 나타낸 단면도이다.3 is a cross-sectional view illustrating a state in which the MPS film 40 is formed on the entire surface of the tungsten silicide film 30 of FIG. 2.

MPS막(40)은 500℃∼700℃의 온도범위에서 0.05 Torr ∼ 5 Torr의 압력으로 SiH4, Si2H6계열의 가스와 PH3계열의 가스를 이용하여 형성하게 된다.The MPS film 40 is formed using SiH 4 , Si 2 H 6 -based gas and PH 3 -based gas at a pressure of 0.05 Torr to 5 Torr in the temperature range of 500 ° C. to 700 ° C.

다른 방법으로는 텅스텐 실리사이드막(30) 표면에 일정한 두께의 비정질 실리콘막을 형성한 다음 일정한 공정조건하에서 시딩(seeding) 프로세스 및 열공정을 이용하여 MPS막(40)을 형성한다.Alternatively, an amorphous silicon film having a predetermined thickness is formed on the surface of the tungsten silicide film 30, and then the MPS film 40 is formed by using a seeding process and a thermal process under constant process conditions.

도 4는 MPS막(40)을 마스크로 하여 텅스텐 실리사이드막(30)을 식각한 상태를 나타낸 단면도이다.4 is a cross-sectional view illustrating a state in which the tungsten silicide film 30 is etched using the MPS film 40 as a mask.

여기에서 보는 바와 같이 표면에 요철이 있는 MPS막(40)을 마스크로 하여 식각함에 따라 MPS막(40)의 凹부가 깊게 식각되어 텅스텐 실리사이드막(30)을 식각하게 된다.As shown here, by etching the MPS film 40 having irregularities on the surface as a mask, the convex portions of the MPS film 40 are deeply etched to etch the tungsten silicide film 30.

도 5는 MPS막을 제거한 상태를 나타낸 단면도이다.5 is a cross-sectional view showing a state in which the MPS film is removed.

여기에서 보는 바와 같이 MPS막(40)을 제거하게 되면 표면에 요철이 형성된 텅스텐 실리사이드막(30)이 형성되어 하부 전하저장전극의 표면적이 증대하게 되어 셀 커패시턴스가 증대하게 된다.As shown here, when the MPS film 40 is removed, the tungsten silicide film 30 having irregularities on the surface is formed to increase the surface area of the lower charge storage electrode, thereby increasing the cell capacitance.

이후 하부전극 마스크를 통해 하부전극을 패터닝하고, 고유전율을 갖는 Ta2O5, BST, PZT 등을 이용하여 유전체막을 형성한 후 상부 전하저장전극을 형성하여 커패시터를 완성하게 된다.Thereafter, the lower electrode is patterned through the lower electrode mask, a dielectric film is formed using Ta 2 O 5 , BST, PZT, etc. having a high dielectric constant, and then an upper charge storage electrode is formed to complete the capacitor.

상기한 바와 같이 본 발명은 커패시터의 하부 전하저장전극인 텅스텐 실리사이드의 표면을 요철이 있도록 형성함으로써 표면적을 증대시켜 셀 커패시턴스를 증해시킬 수 있다는 효과가 있다.As described above, the present invention has the effect of increasing the surface area by increasing the surface area by forming the surface of the tungsten silicide, which is the lower charge storage electrode of the capacitor, with unevenness, thereby increasing the cell capacitance.

Claims (6)

반도체기판의 활성영역에 캐패시터 콘택홀을 형성하는 단계와,Forming a capacitor contact hole in an active region of the semiconductor substrate; 상기 캐패시터 콘택홀을 매립하여 콘택전극을 형성하는 단계와,Filling the capacitor contact hole to form a contact electrode; 상기 결과물 전면에 텅스텐 실리사이드막과 MPS막을 순차적으로 형성하는 단계와,Sequentially forming a tungsten silicide layer and an MPS layer on the entire surface of the resultant; 상기 MPS막을 마스크로 상기 텅스텐 실리사이드막을 식각하는 하는 단계와,Etching the tungsten silicide layer using the MPS layer as a mask; 상기 텅스텐 실리사이드막을 식각한 후 상기 MPS막을 제거하는 단계와,Removing the MPS film after etching the tungsten silicide film; 하부전극 마스크를 통해 하부전극을 패터닝하는 단계와,Patterning the lower electrode through the lower electrode mask; 상기 하부전극을 패터닝한 다음 유전체막을 형성한 후 상부전극을 형성하는 단계Patterning the lower electrode, forming a dielectric layer, and then forming an upper electrode 를 포함하여 이루어진 것을 특징으로 하는 반도체장치의 커패시터 제조방법.Capacitor manufacturing method of a semiconductor device comprising a. 제 1항에 있어서, 상기 콘택홀을 매립하는 단계에서 선택적인 에피텍셜 공정을 이용하여 에피텍셜 폴리실리콘을 성장시켜 매립하는 것을 특징으로 하는 반도체장치의 커패시터 제조방법.The method of claim 1, wherein in the filling of the contact hole, epitaxial polysilicon is grown and buried using an optional epitaxial process. 제 1항에 있어서, 상기 콘택홀을 매립하는 단계에서 콘택홀 전면에 도핑된 폴리실리콘막을 형성한 다음 에치백공정을 이용하여 콘택홀을 매립하는 것을 특징으로 하는 반도체장치의 커패시터 제조방법.The method of claim 1, wherein the doping polysilicon layer is formed on the entire contact hole in the filling of the contact hole, and then the contact hole is buried by an etch back process. 제 1항에 있어서, 상기 MPS막은 500℃∼700℃의 온도범위에서 0.05 Torr ∼ 5 Torr의 압력으로 SiH4, Si2H6계열의 가스와 PH3계열의 가스를 이용하여 형성하는 것을 특징으로 하는 반도체장치의 커패시터 제조방법.The method of claim 1, wherein the MPS film is formed using a gas of SiH 4 , Si 2 H 6 series and PH 3 series gas at a pressure of 0.05 Torr to 5 Torr in the temperature range of 500 ℃ to 700 ℃. Method of manufacturing a capacitor of a semiconductor device. 제 1항 또는 제 4항에 있어서, 상기 MPS막은 텅스텐 실리사이드막 표면에 일정한 두께의 비정질 실리콘막을 형성한 다음 일정한 공정조건하에서 시딩 프로세스 및 열공정을 이용하여 형성하는 것을 특징으로 하는 반도체장치의 커패시터 제조방법.The semiconductor device capacitor manufacturing method according to claim 1 or 4, wherein the MPS film is formed on a surface of a tungsten silicide film by forming an amorphous silicon film having a predetermined thickness, and then using a seeding process and a thermal process under constant process conditions. Way. 제 1항에 있어서, 상기 유전체막은 고유전율을 갖는 Ta2O5, BST, PZT 중 어느 하나로 형성하는 것을 특징으로 하는 반도체장치의 커패시터 제조방법.The method of claim 1, wherein the dielectric layer is formed of any one of Ta 2 O 5 , BST, and PZT having a high dielectric constant.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100388468B1 (en) * 2001-06-30 2003-06-25 주식회사 하이닉스반도체 Capacitor making methods of ferroelectric random access memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100388468B1 (en) * 2001-06-30 2003-06-25 주식회사 하이닉스반도체 Capacitor making methods of ferroelectric random access memory

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