KR960030407A - Capacitor of semiconductor memory device and manufacturing method thereof - Google Patents

Capacitor of semiconductor memory device and manufacturing method thereof Download PDF

Info

Publication number
KR960030407A
KR960030407A KR1019950001779A KR19950001779A KR960030407A KR 960030407 A KR960030407 A KR 960030407A KR 1019950001779 A KR1019950001779 A KR 1019950001779A KR 19950001779 A KR19950001779 A KR 19950001779A KR 960030407 A KR960030407 A KR 960030407A
Authority
KR
South Korea
Prior art keywords
layer
hsg
etch stop
spacer
forming
Prior art date
Application number
KR1019950001779A
Other languages
Korean (ko)
Inventor
심세진
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950001779A priority Critical patent/KR960030407A/en
Publication of KR960030407A publication Critical patent/KR960030407A/en

Links

Landscapes

  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

반구상그레인을 실리콘층 위에 형성하여 고용량의 캐패시터를 제조하는 방법, 특히 스토리지전극 형성을 위한 식각시에 실린더상단에 형성된 반구상그레인실리콘(HSG-Si)층이 손상을 입는 것을 방지하고 실린더 바닥에 형성된 HSG-Si층을 잔존시켜 고용량의 캐패시터를 얻는 방법을 개시한다.Forming a hemispherical grain on the silicon layer to produce a high capacity capacitor, in particular to prevent damage to the hemispherical grain silicon (HSG-Si) layer formed on the top of the cylinder during etching to form the storage electrode A method of obtaining a high capacity capacitor by remaining the formed HSG-Si layer is disclosed.

이를 위해 제거되어야 할 HSG-Si층은 도핑되지 않는 절연층 위에 형성시키고 잔존해야 할 HSG-Si층은 도핑된 다결정실리콘층 위에 형성시킨다. 본 발명의 실시예에서는 스토리지전극의 다결정실리콘층은 도핑된 상태이고 식각중지층은 도핑되지 않게 하여 각각에 형성된 HSG-Si층의 식각율이 다르게 하여 HSG-Si층을 선택적으로 식각한다.For this purpose, the HSG-Si layer to be removed is formed over the undoped insulating layer and the HSG-Si layer to be remaining is formed over the doped polysilicon layer. In an embodiment of the present invention, the polycrystalline silicon layer of the storage electrode is doped and the etch stop layer is not doped so that the etching rate of the HSG-Si layer formed on each is different, thereby selectively etching the HSG-Si layer.

Description

반도체 메모리장치의 캐패시터 및 그 제조방법Capacitor of semiconductor memory device and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2I도는 본 발명의 일실시예에 따른 캐패시터의 제조방법을 나타내는 단면도이다.2A to 2I are cross-sectional views showing a method of manufacturing a capacitor according to an embodiment of the present invention.

Claims (6)

반구상그레인을 갖는 다결정실리콘(HSG-Si)막을 가지는 캐패시터에 있어서, 반도체 기판 상면 소정부분에 순차적으로 제1절연층, 식각중지층 및 제2절연층을 형성하는 단계; 상기 제1절연층, 식각중지층 및 제2절연층의 소정부분을 식각하여 접촉구를 형성하는 단계; 상기 접촉구의 측벽에 스페이서를 형성하는 단계; 반도체 기판전면에 다결정실리콘층을 형성하는 단계; 상기 다결정실리콘층 일부영역에 포토레지스터를 형성하는 단계; 상기 포토레지스터의 측벽에 스페이서를 형성하는 단계; 상기 포토레이지스트와 스페이서를 마스크로 이용하여 상기 다결정실리콘층을 식각하는 단계; 상기 포토레지스트를 제거하는 단계; 상기 스페이서를 마스크로 이용하여 다결정실리콘층을 식각하는 단계; 상기 스페이서와 제2절연층을 제거하는 단계; 기판 전면에 HSG를 증착하여 다결정실리콘층과 식각중지층표면에 HSG-Si층을 형성시키는 단계; 및 상기 식각중지층표면의 HSG-Si층만 제거하는 단계를 구비함을 특징으로 하는 캐패시터의 제조방법.A capacitor having a polycrystalline silicon (HSG-Si) film having hemispherical grains, comprising: sequentially forming a first insulating layer, an etch stop layer, and a second insulating layer on a predetermined portion of an upper surface of a semiconductor substrate; Etching a predetermined portion of the first insulating layer, the etch stop layer, and the second insulating layer to form a contact hole; Forming a spacer on a sidewall of the contact hole; Forming a polysilicon layer on the front surface of the semiconductor substrate; Forming a photoresist on a portion of the polysilicon layer; Forming a spacer on sidewalls of the photoresist; Etching the polysilicon layer using the photoresist and the spacer as a mask; Removing the photoresist; Etching the polysilicon layer using the spacer as a mask; Removing the spacers and the second insulating layer; Depositing HSG on the entire surface of the substrate to form an HSG-Si layer on the polycrystalline silicon layer and the etch stop layer; And removing only the HSG-Si layer on the surface of the etch stop layer. 제1항에 있어서, 상기 다결정실리콘층은 불순물이 도핑되었고 상기 식각중지층은 불순물이 도핑되어 있지 않음을 특징으로 하는 캐패시터의 제조방법.The method of claim 1, wherein the polysilicon layer is doped with impurities and the etch stop layer is not doped with impurities. 제1항에 있어서 상기 제1 및 제2절연층이 BPSG, USG, 고온산화막, PE-TEOS 산화막, PE-SiH4, 산화막 또는 SOG 중의 어느 하나임을 특징으로 하는 캐패시터의 제조방법.The method of claim 1, wherein the first and second insulating layers are any one of BPSG, USG, high temperature oxide film, PE-TEOS oxide film, PE-SiH 4 , oxide film, or SOG. 제1항에 있어서, 상기 식각중지층이 SiN임을 특징으로 하는 캐패시터의 제조방법.The method of claim 1, wherein the etch stop layer is SiN. 제1항에 있어서, 상기 스페이서가 SiN임을 특징으로 하는 캐패시터의 제조방법.The method of claim 1, wherein the spacer is SiN. 제1항 또는 2항에 있어서, 상기 다결정실리콘층은 포클을 이온주입하여 형성함을 특징으로 하는 캐패시터의 제조방법.The method of claim 1, wherein the polysilicon layer is formed by ion implanting a fockle. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950001779A 1995-01-28 1995-01-28 Capacitor of semiconductor memory device and manufacturing method thereof KR960030407A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950001779A KR960030407A (en) 1995-01-28 1995-01-28 Capacitor of semiconductor memory device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950001779A KR960030407A (en) 1995-01-28 1995-01-28 Capacitor of semiconductor memory device and manufacturing method thereof

Publications (1)

Publication Number Publication Date
KR960030407A true KR960030407A (en) 1996-08-17

Family

ID=66531341

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950001779A KR960030407A (en) 1995-01-28 1995-01-28 Capacitor of semiconductor memory device and manufacturing method thereof

Country Status (1)

Country Link
KR (1) KR960030407A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100533363B1 (en) * 2000-05-24 2005-12-06 주식회사 하이닉스반도체 Forming method for storage node of semiconductor device
KR100540257B1 (en) * 1998-12-29 2006-05-03 주식회사 하이닉스반도체 Method for forming charge storage electrode of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100540257B1 (en) * 1998-12-29 2006-05-03 주식회사 하이닉스반도체 Method for forming charge storage electrode of semiconductor device
KR100533363B1 (en) * 2000-05-24 2005-12-06 주식회사 하이닉스반도체 Forming method for storage node of semiconductor device

Similar Documents

Publication Publication Date Title
US5716883A (en) Method of making increased surface area, storage node electrode, with narrow spaces between polysilicon columns
US5284787A (en) Method of making a semiconductor memory device having improved electrical characteristics
US6037220A (en) Method of increasing the surface area of a DRAM capacitor structure via the use of hemispherical grained polysilicon
JP3640763B2 (en) Manufacturing method of capacitor of semiconductor memory device
JPH06188381A (en) Capacitor of dram cell and its preparation
KR940003021A (en) Semiconductor Memory and Manufacturing Method
KR19990073712A (en) Semiconductor memory device provided with COB and manufacturing method thereof
US5536673A (en) Method for making dynamic random access memory (DRAM) cells having large capacitor electrode plates for increased capacitance
US5770510A (en) Method for manufacturing a capacitor using non-conformal dielectric
US6597033B1 (en) Semiconductor memory device and manufacturing method thereof
KR960030407A (en) Capacitor of semiconductor memory device and manufacturing method thereof
US5756388A (en) Method for fabricating a rake-shaped capacitor
US6060367A (en) Method of forming capacitors
US6596577B2 (en) Semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry
KR100356814B1 (en) Method of fabricating a capacitor in semiconductor device
US5973350A (en) Stacked capacitor structure for high density DRAM cells
KR0168343B1 (en) Storage electrode fabrication method having hemispherical grain
KR0183883B1 (en) Contact forming method of semiconductor device
KR0168335B1 (en) Semiconductor device & its fabrication method
KR100546112B1 (en) Manufacturing method of semiconductor device
KR100213211B1 (en) Manufacturing method of large scale integrated memory devices
KR100618693B1 (en) method for fabricating storage node electrode of capacitor
KR100255658B1 (en) Manufacture method of storage electron pole having hsg silicon
KR0136529B1 (en) The fabrication method for semiconductor memory device
KR0165382B1 (en) Capacitor fabrication method of semiconductor memory device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
WITB Written withdrawal of application