KR20010004675A - Data output buffer - Google Patents

Abstract

PURPOSE: A data output buffer is provided to sense the magnitude of a load applied to a data input and output pads and adjust a buffer driving power respectively depending on the magnitude, thereby achieving the high speed of data output while reducing noise. CONSTITUTION: In a data output buffer, devices(10,20) for controlling a pull-up and pull-down operations generates a pull-up signal and a pull-down signal respectively by the association of a read selecting signal and a data signal. The first pull-up and pull-down devices pull-up and pull-down the potentials of data input and output pads respectively by turning on by the pull-up and pull-down signal respectively. The second pull-up and pull-down device is parallel-connected to the first pull-up and pull-down device using the data input and output pads. A delay device(30) receives the read selecting signal and delays the signal by a desired time. The first and second comparing devices(40,50) are activated selectively depending on the association result of the data signal and the read selecting signal generated from the delay device. The first and second comparing devices are controlled to activate the operation of the second pull-up and pull-down device after delaying the operation by the desired time depending on the compared results by feedbacking the potentials of the data input and output pads and comparing the potentials with the first and second reference potentials respectively. Devices(60,70) for generating the first and second reference potentials generate the first and second reference potentials respectively.

Description

Data output buffer

The present invention relates to a data output buffer that buffers or amplifies internally processed data in a semiconductor integrated circuit so that the data has a voltage level sufficient to drive an external peripheral circuit. The present invention relates to a data output buffer that realizes a high speed data output with a reduction in damping noise by changing a pull-up and pull-down driving capability of an output terminal potential according to a sensed load size.

In general, in a system configuration of a semiconductor memory device, a system having a small capacity such as a PC may be configured, or a system requiring a large capacity such as a server may be configured. In a small capacity, a data output buffer of a semiconductor memory device may be used. In a system with a small load and a large capacity, the load on the output buffer of the semiconductor memory device is large.

By the way, in the operation of the semiconductor memory device with respect to the reference buffer, it is impossible to increase the size of the data output buffer indefinitely. The reason is that when the size is large according to the load applied from the outside, the overall data output operation becomes slow. This is because high-speed data output operation is possible when the external load is small. However, damping noise may affect the next data output and cause a malfunction.

1 is a block diagram schematically illustrating a conventional data output buffer, in which a read select signal (RS) and a data signal (data) indicating a data output are received and a combination of these two signals (RS) is received. Pull-up and pull-down drive control means (10, 20) for selectively activating pull-up or pull-down drive control signals (pu, pd) by means of; It is connected in series between the power supply voltage Vdd applying terminal and the ground terminal, and is selectively turned on by the pull-up and pull-down signals pu and pd to supply the potential of the data input / output pad DQ pad. It is composed of pull-up and pull-down means (T, T2) to pull up and pull-down to the power supply potential or ground potential level, respectively.

In the case of the same figure, the pull-up and pull-down means T1 and T2 are all composed of NMOS transistors.

By the above configuration, when the read select signal RS is enabled, it is determined whether the data signal is 'logic high' or 'logic low' information. In this case, the pull-up driving control means 10 is activated to activate the pull-up signal pu (in this case, since the pull-up element T1 is composed of NMOS transistors, the logic high is obtained.) State). Thereafter, the pull-up element T1 is turned on by the pull-up signal pu in an active state, so that the data output pad DQ pad is pulled up to the power supply potential Vdd of 'logic high'. Let's go.

On the other hand, when the data signal is a logic low signal, the pull-down driving control means 20 is activated to activate the pull-down signal pd (in the case of the figure, pull-down). Since the device T2 is made of an NMOS transistor, the element T2 is in a logic high state. Thereafter, the pull-down device T1 is turned on to pull down the data output pad DQ pad to the ground potential Vss of the logic low level.

Since the size of the pull-up and pull-down elements T1 and T2 is fixed in the conventional data output buffer for outputting data by the above operation, the data access time depends on the change of the external load acting on the data output. Noise and noise also change, which can cause performance degradation and malfunction of the main chip or system.

In addition, when the load from the outside is smaller than the buffer size, a problem arises in that not only noise but also power consumption are unnecessarily large.

FIG. 2 is a diagram illustrating a simulation result of installing one module on a board when designing a system using the data output buffer shown in FIG. 1. As shown in (a), the lead selection (RS) signal is 'high'. When the data signal is input as shown in (b) while the signal is enabled, the output signal data_out which does not show a difference from the input data signal as shown in (c) is used as a data input / output pad (DQ pad). Will be printed as

This figure shows that the data output operation is performed without any problem when the load on the data input / output pad (DQ pad) is small.

FIG. 3 is a diagram illustrating a result of installing and simulating a plurality of modules on a board when designing a system using the data output buffer shown in FIG. 1. The output data signal shown by (c) compared to the signal waveform of FIG. 2. It can be seen that the waveform of) is caused by a predetermined time delay in a somewhat distorted state.

In other words, if the size of the load on the data input / output pad (DQ pad) increases, a predetermined delay time until the data of the desired potential level is loaded on the data input / output pad (DQ pad) (in the case of FIG. In the case of the second output data ('logic low' data) signal, the output signal waveform is changed due to the reflected wave due to the impedance at the transition line. It will be greatly shaken, indicating a longer time to reach the potential level of logic low.

As described above, the data output buffer conventionally used has a fixed size in accordance with the size of the load applied to the data input / output pad (DQ pad). Since the drive capacity cannot be changed, when the buffer size of the data output buffer is the reference size, that is, when the operation is based on a small impedance, the load size becomes larger than the buffer size, and thus the constant level of the VOH / VOL is achieved. The required time becomes long, which causes delay in time and distortion of the signal waveform as shown in FIG. 3. Therefore, there is a problem that causes the performance degradation and malfunction of the product.

On the other hand, if the size of the data output buffer is designed to operate based on a large impedance, there is a possibility of malfunction due to noise in the configuration of a system with a small impedance, and waste of power due to excessive current consumption. There is a problem that becomes large.

The present invention has been made to solve the above problems, and an object of the present invention is to detect the size of the load acting on the data input and output pads, and to operate by controlling the buffer driving force differently according to the size, thereby providing a high speed data output. It is to provide a data output buffer realized with noise reduction.

In order to achieve the above object, the data output buffer according to the present invention comprises pull-up drive control means and pull-down drive control means for generating pull-up and pull-down signals, respectively, by a combination of a read select signal and a data signal. and;

First pull-up and pull-down means which are turned on by the pull-up and pull-down signals, respectively, to pull-up and pull-down potentials of data input and output pads, respectively;

Second pull-up and pull-down means connected in parallel with the first pull-up and pull-down means via the data input / output pads;

Delay means for receiving the read selection signal and delaying the predetermined time;

It is selectively activated by a combination result of the read select signal and the data signal generated from the delay means. The potentials of the data input / output pads are fed back and compared with the first and second reference potentials, respectively. First and second comparison means for controlling the operation of the second pull-up and pull-down means to be activated after a delay of the predetermined time;

And first and second reference potential generating means for generating the first and second reference potentials.

In addition, the present invention provides a transition detection means and the transition detection means for detecting the data transition by receiving the data signal in front of the delay means for the application in the EDO method and the synchronous memory device that the data is continuously output And a logic means for AND-combining an output signal and the read select signal, wherein the delay means is configured to receive an output signal of the logic means and delay a predetermined time.

1 is a block diagram of a conventional data output buffer

FIG. 2 is a diagram illustrating simulation results of installing one module on a board when designing a system using the data output buffer shown in FIG.

FIG. 3 is a diagram illustrating results of installing and simulating a plurality of modules on a board in a system design using the data output buffer shown in FIG.

4 is a configuration diagram of a data output buffer according to an embodiment of the present invention.

FIG. 5 is a circuit diagram according to an embodiment of the first comparison means shown in FIG. 4.

FIG. 6 is a circuit diagram according to an embodiment of the second comparison means shown in FIG. 4.

7 is a result of the simulation and the installation of a plurality of modules on the board in the system design using a data output buffer according to the present invention

8 is a configuration diagram of a data output buffer according to another embodiment of the present invention.

9 is an operation timing diagram of the data output buffer shown in FIG.

<Explanation of symbols for main parts of drawing>

10: pull-up drive control means 20: pull-down drive control means

30: delay means 40, 50: comparison means

60, 70: reference potential generating means T1, T3: pull-up means

T2, T4: pull-down means

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a block diagram of a data output buffer according to an exemplary embodiment of the present invention. The pull-up and pull-down signals pu and pd are combined by the read select signal RS and the data signal data. Pull-up and pull-down drive control means (10, 20) for generating a); First pull-up and pull-up which are respectively turned on by the pull-up and pull-down signals pu and pd to pull-up and pull-down potentials of the data input / output pads DQ pad, respectively; Down means T1 and T2; Second pull-up and pull-down means T3 and T4 connected in parallel with the first pull-up and pull-down means T1 and T2 via the data input / output pad DQ pad. and; Delay means (30) for receiving the read selection signal (RS) for delaying a predetermined time; It is selectively activated by a combination result of the read select signal RS and the data signal data generated from the delay means 30. The potential of the data input / output pad DQ pad is fed back to the first and A first and second operation for comparing the second reference potentials Vref_H and Vref_L, respectively, and controlling the operation of the second pull-up and pull-down means T3 and T4 to be activated after a delay of the predetermined time according to the comparison result; Second comparing means (40, 50); First and second reference potential generating means 60 and 70 generating the first and second reference potentials Vref_H and Vref_L, respectively, and transferring the first and second reference potentials Vref_H and Vref_L to one input terminal of the first and second comparison means 40 and 50, respectively. It is configured with.

Although the first and second pull-up and pull-down means T1 to T4 are implemented as NMOS transistors in the drawing, only the first and second pull-up means T1 and T3 are PMOS transistors. It can be said that it can be implemented.

In addition, the first reference potential Vref_H, which is an input signal of one side of the first comparing means 40, is higher than the high-impedance value and has a value similar to the VOH (2.4V in the LVTTL interface structure) potential. The second reference potential Vref_L generated from the second comparing means 50 is lower than the high-impedance value and is similar to the VOL potential (0.4V in the LVTTL interface structure).

Hereinafter, the operation of the present invention having the above configuration will be described in detail.

First, when the read select signal RS informing of the data output is enabled as 'logic high', the data signals in the pull-up and pull-down driving control means 10 and 20 are set to 'logic high'. It checks whether it is information or 'logic low' information and selectively activates the pull-up and pull-down signals pu and pd accordingly. In this case, when the data signal is 'logic high', the pull-up signal pu is activated to turn on the first pull-up means T1 of the rear stage. Accordingly, the logic high level signal is carried on the data input / output pad (DQ pad). On the other hand, when the data signal is 'logic low', the pull-down signal pd is activated to turn on the first pull-down means T2 of the rear stage. Accordingly, the logic low level signal is carried on the data input / output pad (DQ pad).

The operation up to this point is performed as in the prior art, and when the load applied to the data input / output pad (DQ pad) is small, by the selective activation operation of the first pull-up and pull-down elements in the same manner. The data is output.

However, when the load on the data input / output pad (DQ pad) is large, only the first pull-up and pull-down means T1 and T2 provide a desired potential level signal to the data input / output pad DQ. The time required to be loaded on the pad becomes longer, and the lead selection signal RS_d delayed by the predetermined time from the delay means 30 is activated and transferred to the first and second comparison means 40 and 50 at the rear end. To selectively activate these comparison means 40, 50.

If the data signal data is 'logic high', the first comparison means 40 is activated. If the data signal data is 'logic low', the second comparison means 50 is performed. Is activated.

The configuration and operation of the first and second comparison means 40 and 50 will be described in detail with reference to the drawings.

FIG. 5 is a circuit diagram according to an embodiment of the first comparison means 40 shown in FIG. 4. The read select signal RS_d and the data signal data delayed through the delay means 30. ) And an output data signal (optionally activated by the logic unit 1 and the output signal received from the reference potential signal Vref_H and the data input / output pad DQ pad). a comparator 3 having a current-mirror structure for comparing the potentials of data_out), a buffering part 5 for buffering and outputting the output signal of the comparator 3 at a predetermined potential level, and the buffering part 5 And a potential converting section 7 for converting the signal outputted from the display according to the operating characteristics of the second pull-up means T3.

Since the comparator 3 is controlled to be activated by the NMOS transistor MN1 to which the output signal of the logic unit 1 is applied to the gate terminal, the output signal of the logic unit 1 is 'logic high'. That is, only when the data signal data is 'logic high', it is activated to generate the second pull-up signal pu2.

At this time, when the potential of the output data signal data_out fed back from the data input / output pad DQ pad is lower than the first reference potential Vref_H, the second pull-up signal pu2 is generated in an active state. The second pull-up means T3 of the rear stage is controlled to be driven.

The second pull-up means T3 is pulled up and stopped until data_out≥Vref_H.

In addition, since the second pull-up means T3 may be implemented as a PMOS transistor as well as the NMOS transistor, the potential converter 7 is provided to adjust the potential level of the second pull-up signal accordingly. Done. For example, when the second pull-up means T3 is formed of a PMOS transistor, the second pull-up means T3 is controlled to have an on / off potential between a power supply voltage and a ground voltage. In the case of the NMOS transistor, the output potential is switched to have an on / off potential between the potential higher than the power supply voltage and the ground potential higher than the threshold voltage.

FIG. 6 is a circuit diagram illustrating a circuit according to an embodiment of the second comparison means 50 shown in FIG. 4. The read select signal RS_d and the data signal data delayed through the delay means 30. Is selectively activated by the logic unit 2 for NAND combining the inverted signals of the &lt; RTI ID = 0.0 &gt;) &lt; / RTI &gt; and the output signal of the logic unit 2 from the second reference potential signal Vref_L and the data input / output pad DQ pad. And a current-mirror comparing section 4 for comparing the potential of the feedback output data signal data_out and a buffering section 6 for buffering the output signal of the comparing section 4.

Since the comparator 4 is activated and controlled by the PMOS transistor MP1 to which the output signal of the logic unit 2 is applied to the gate terminal thereof, the output signal of the logic unit 2 is 'logic low'. In other words, only when the data signal data is 'logic low', it is activated to generate the second pull-down signal pd2.

At this time, when the potential of the output data signal data_out fed back from the data input / output pad DQ pad is higher than the second reference potential Vref_L, the second pull-down signal pd2 is generated in an active state. The second pull-down means T4 of the rear stage is controlled to be driven.

The second pull-down means T4 is pulled down and stopped until data_out≤Vref_L.

As described above, when the load becomes large on the data input / output pad (DQ pad) and the time until the data is loaded becomes long, the first and second comparison means 40, 50 are used. The read select signal RS is transmitted from the delay means 30, and one of the two comparison means 40, 50 is selectively activated according to the potential value of the data signal data, thereby causing the second pull-up and pull-up. And selectively generates the down signals pu2 and pd2, and by the activation of the second pull-up and pull-down signals pu and pd generated in this manner, the second pull-up and pull-down means T3, T4) is driven to greatly increase the pull-up and pull-down driving capability of the data output buffer.

FIG. 7 is a result of installing and simulating a plurality of modules on a board when designing a system using a data output buffer according to the present invention. The load acting on a data input / output pad (DQ pad) is compared with that of FIG. 3. Even when the output data signal (data_out) shown in (c) is large, the distortion is large and the influence of the reflected wave due to the impedance is greatly reduced even in the transition period from 'logic high' to 'logic low'. It can be seen.

However, since the data output buffer having the configuration shown in FIG. 2 delays the operations of the first and second comparison means 40 and 50 only with the read select signal RS, data is continuously output to select the read. Application of EDO (Extended Data Out) and synchronous memory devices in which data is output while only data information is changed while the signal RS is continuously enabled is difficult.

FIG. 8 is a block diagram of a data output buffer according to another embodiment of the present invention. The data output buffer shown in FIG. 2 is an example of an application in the above-described EDO and synchronous memory devices. Transition detection means 80 for receiving data and detecting data transition; and logic means 90 for combining and combining the output signal of the transition detection means 80 and the read select signal RS. In addition, the delay means 30 is configured to delay the predetermined time by receiving the output signal of the logic means 90.

FIG. 9 illustrates an operation timing diagram of the data output buffer shown in FIG. 8, when a transition of the next data signal occurs after the output operation of the first data signal occurs while the read select signal RS is enabled. The transition detection means 80 detects the transition or not and outputs the transition detection result to the node N1 as shown in (c).

Thereafter, when the output signal of the transition detecting means 80 and the lead selection signal RS are AND-combined to generate a signal as shown in (d) to the node N2, this is delayed means 30 at the rear end. After a predetermined time delay, the RS_d signal is generated as shown in (e).

In this case, the reason for the AND combination of the signal (signal of N1) and the read select signal RS, which are enabled only at the time of data transition, is to detect the transition of data only while the read select signal RS is enabled. have.

By this operation, it is possible to generate a predetermined time delayed read select signal RS_d by detecting a data transition even when the read select signal RS is continuously enabled by the continuous output of data. The first and second comparison means 40 and 50 connected to the rear stages are delayed for a predetermined time according to the load size acting on the data input / output pad (DQ pad), so that the buffer pull-up and pull-down driving capability It is possible to sequentially adjust according to the rod size.

Hereinafter, detailed operation descriptions will be omitted to avoid duplication of description.

As described above, according to the data output buffer according to the present invention, it is possible to prevent noise increase and unnecessary current consumption when there is a small load acting from the outside. The ability to increase up- and pull-down drive capability makes it possible to realize high speed data output with noise reduction.

That is, when the system is designed using the data output buffer according to the present invention, it has excellent operating characteristics in terms of data access time, noise and current consumption during operation according to system capacity, that is, load change applied to the data output buffer. Being has a very outstanding effect.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to make various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the scope of the claims You will have to look.

Claims (6)

Pull-up and pull-down drive control means for generating pull-up and pull-down signals respectively by a combination of a read select signal and a data signal; First pull-up and pull-down means which are turned on by the pull-up and pull-down signals, respectively, to pull-up and pull-down potentials of data input and output pads, respectively; Second pull-up and pull-down means connected in parallel with the first pull-up and pull-down means via the data input / output pads; Delay means for receiving the read selection signal and delaying the predetermined time; It is selectively activated by a combination result of the read select signal and the data signal generated from the delay means. The potentials of the data input / output pads are fed back and compared with the first and second reference potentials, respectively. First and second comparison means for controlling the operation of the second pull-up and pull-down means to be activated after the delay of the predetermined time; And first and second reference potential generating means for generating the first and second reference potentials, respectively. The method of claim 1, Transition detection means for receiving the data signal and detecting a data transition; And logic means for AND-combining the output signal of the transition detecting means and the read select signal; And the delay means receives the output signal of the logic means and delays the signal for a predetermined time. The method of claim 1, The first comparing means includes a logic unit for AND-combining the read selection signal and the data signal delayed through the delay means; A comparator having a current-mirror structure which is selectively activated by an output signal of the logic unit and compares a potential of a first reference potential signal and an output data signal fed back from the data input / output pads; A buffering unit for buffering and outputting the output signal of the comparator to a previous electric potential level; And a potential converting unit for converting the signal output from the buffering unit into a potential conversion in accordance with an operation characteristic of the second pull-up means. The method of claim 1, And the first comparison means generates a control signal for activating the second pull-up means until the potential signal fed back from the data input / output pad is equal to or higher than the first reference potential. buffer. The method of claim 1, The second comparing means includes a logic unit for NAND combining the read selection signal delayed through the delay means and the inverted signal of the data signal; A comparator having a current-mirror structure which is selectively activated by an output signal of the logic unit and compares a potential of a second reference potential signal and an output data signal fed back from the data input / output pads; And a buffering unit for buffering the output signal of the comparing unit. The method of claim 1, And the second comparing means generates a control signal for activating the second pull-down means until the potential signal fed back from the data input / output pad is equal to or lower than the second reference potential. buffer.