KR100420086B1 - Voltage conversion circuit of semiconductor device - Google Patents

Abstract

PURPOSE: A voltage conversion circuit of a semiconductor device is provided to improve a delay of a response period of an internal supply voltage according to the dip/overshooting of the internal supply voltage by using a control circuit. CONSTITUTION: A voltage conversion circuit of a semiconductor device includes a power line, a comparator, a driver, and a controller. The power line is used for transmitting an internal supply voltage. The comparator is used for comparing an external reference voltage with the internal supply voltage and outputting the first signal. The driver is used for supplying the predetermined current from an external power line to an internal power line in response to the fist signal. The controller(240) is used for generating a control signal equal to or more than the reference voltage in response to the second signal synchronized with a chip activation signal.

Description

Voltage conversion circuit of semiconductor device.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a voltage conversion circuit of a semiconductor device for converting an external power supply voltage into an internal power supply voltage.

)에 따라 활성화되거나 비활성화된다.In general, the voltage conversion circuit, i.e., the internal power supply voltage generation circuit, is used separately for standby and active according to the purpose of use. The standby internal power supply voltage generation circuit has a slow recovery speed against external change factors such as power noise compared with that of the active one. This is to reduce power consumption. The active internal supply voltage generator circuit only operates when the chip is activated to minimize current consumption. The active voltage conversion circuit includes an internal power supply circuit for the array for supplying only the array of memory cells during the data sensing operation and an internal power supply voltage generator for supplying the internal power supply voltage to the remaining peripheral circuits except the array. As mentioned earlier, in order to reduce current consumption, the active voltage conversion circuit uses a chip activation signal (

Is activated or deactivated.

1 is a voltage conversion circuit for generating an internal power supply voltage for a conventional array.

)에 동기되는 신호 (PIACT)가 인버터(6)를 통해 반전되어 인가된다. 따라서, 상기 칩 활성화 신호(

)가 로우 레벨(low level)로 활성화되는 동안만 전압 변환 회로가 동작하게 된다. 상기 인버터(6)의 공급 전원은 도 1에 보이는 바와같이 내부 전원 전압(IVC)이다. 여기서, 전압 변환 회로는 어레이용 전원 전압만을 발생하는 회로에만 국한되지 않음은 이 분야의 지식을 가진 자들은 잘 알 수 있을 것이다.Referring to FIG. 1, a voltage conversion circuit includes a differential amplifier circuit 10 including PMOS transistors 1 and 2 and NMOS transistors 3, 4, and 5 and a power supply voltage for an array. A driver 20 for driving the VCCA and comprising a PMOS transistor 7 is configured. The NMOS transistor 5 operates as a current source, that is, a source transistor 5 of the differential amplifying circuit 10, and its gate activates the chip activation signal (

Signal (PIACT) synchronized with () is applied inverted through the inverter (6). Therefore, the chip activation signal (

The voltage conversion circuit operates only while the low level is activated. The power supply of the inverter 6 is an internal power supply voltage IVC as shown in FIG. Here, it will be appreciated by those skilled in the art that the voltage conversion circuit is not limited to a circuit that generates only the supply voltage for the array.

The DRAM using the internal power supply voltage IVC and the power supply voltage VCCA for the array may be caused by noise of the power supply voltage or a sensing operation when the external power supply voltage EVC changes in a short cycle. A dip (see FIG. 4) occurs due to a large current consuming operation. Here, the dip means that the level of the internal power supply voltage IVC or the internal power supply voltage VCCA for the array is reduced to a predetermined voltage level (target level) or less.

)에 의해서 발생된 신호 (PIACT)의 제어를 받는 PMOS 트랜지스터(5)의 게이트로 인버터(6)를 통해 내부 전원 전압(IVC)이 인가될 경우, 내부 전원 전압(IVC)의 딥 또는 오버슈팅(overshooting) 발생시 또는 내부 전원 전압(IVC)의 파워 라인의 로딩이 클 경우 어레이용 내부 전원 전압(VCCA)이 요구되는 레벨로 승압되는 응답 시간(respose time)이 늦어지게 된다.As shown in FIG. 1, the chip activation signal (

When the internal power supply voltage IVC is applied to the gate of the PMOS transistor 5 under the control of the signal PIACT generated by the inverter 6 through the inverter 6, a dip or overshooting of the internal power supply voltage IVC ( When overshooting occurs or when the load of the power line of the internal power supply voltage IVC is large, the response time for boosting the internal power supply voltage VCCA for the array to a required level is delayed.

Therefore, when the response time is delayed, the operation characteristics of the low power supply voltage (low VCC) and the short cycle are degraded, which causes the malfunction inside the chip. In order to solve this problem, if the size of the PMOS transistor 5 is increased, the sensitivity is improved, but the current consumption is increased and the operating current is increased.

Accordingly, an object of the present invention is to provide a voltage conversion circuit of a semiconductor device capable of speeding up the time of stepping up to a set voltage level after a dip is generated in an internal power supply voltage for an array under low power supply voltage or a short cycle.

1 is a circuit diagram showing a conventional voltage conversion circuit;

2 is a circuit diagram showing a voltage conversion circuit according to a preferred embodiment of the present invention;

3 is a waveform diagram showing pull-up and pull-down drive signals generated by a signal PIACT synchronized to the chip activation signal;

4 is a waveform diagram showing a dip degree of an internal power supply voltage for an array according to the prior art and the present invention when a chip activation signal is applied;

Explanation of symbols on the main parts of the drawings

200: differential amplifier circuit 220: driver

240: control circuit

According to an aspect of the present invention for achieving the above object, a voltage conversion circuit for converting an external power supply voltage into an internal power supply voltage, comprising: a power supply line for transferring the internal power supply voltage; Comparison means for outputting a first signal by comparing a reference voltage applied from the outside with the internal power supply voltage when the external power supply voltage is supplied; Drive means for supplying a predetermined current from the external power supply voltage to the internal power supply line in response to the first signal; Control means for generating a control signal at a level equal to or higher than said reference voltage in response to a second signal synchronized with a chip activation signal; The comparison means is activated or deactivated by the control signal.

In this embodiment, the control means comprises: delay means for receiving the second signal and outputting pull-up and pull-down drive signals with a predetermined time delay; And output drive means for outputting the control signal in response to the pull-up and pull-down drive signals output from the delay means.

In this embodiment, the pull up and pull down drive signals and the first signal are driven to the level of the external power supply voltage.

In this embodiment, the driving means comprises a first PMOS transistor having a source to which the external power supply voltage is applied, a drain connected to the power supply line, and a gate to which the first signal is applied.

In this embodiment, the delay means includes: first and second inverters that receive the second signal and delay a predetermined time and are sequentially connected in series; A NOR gate having one input terminal to which the second signal is applied and the other input terminal connected to an output terminal of the second inverter; A third inverter having an input terminal connected to an output terminal of the NOR gate and an output terminal for outputting the pull-up driving signal; A NAND gate having one input terminal to which the second signal is applied and the other input terminal connected to an output terminal of the second inverter; And a fourth inverter having an input terminal connected to the output terminal of the NAND gate and an output terminal for outputting the pull-down driving signal.

In this embodiment, the third and fourth inverters are each applied the external power supply voltage to their power supply terminals.

In this embodiment, the output driving means includes a gate to which the pull-up driving signal is applied, a source to which a voltage of a level equal to or higher than the reference voltage is applied, and a drain connected to a line for transmitting the control signal. A second PMOS transistor having; An NMOS transistor has a gate to which the pull-down driving signal is applied, a drain connected to the line, and a source connected to ground.

By such a circuit, the level of the signal for controlling the current source in the differential amplifier circuit can be applied at a voltage independent of the variation of the internal power supply voltage.

Reference to the drawings according to an embodiment of the present invention will be described in detail with reference to Figs.

Referring to FIG. 2, the voltage converting circuit of the novel semiconductor device of the present invention is always independent of the variation of the internal power supply voltage IVC for controlling the source transistor 110 used as the current source of the differential amplifying circuit 100. A control circuit 240 is provided for outputting a control signal of a voltage (Vrefp) level that maintains a constant voltage level. As a result, even when a dip occurs in the internal power supply voltage for the array, it is possible to supply stable power to the cell array as the voltage is rapidly increased to its set voltage level.

2 is a voltage conversion circuit of a semiconductor device according to a preferred embodiment of the present invention. In Fig. 2, since the differential amplifier circuit 200 and the driver 220 conventionally used in this field have the same configuration as those of Fig. 1 mentioned above, the description thereof is omitted here to avoid duplication of explanation.

)에 의해서 내부적으로 발생된 신호 (PIACT)를 입력받아 제어 신호(C)를 발생한다. 상기 제어 신호(C)는 상기 차동 증폭 회로(200)의 소오스 트랜지스터(110)의 게이트로 인가되며 그것의 레벨에 따라 상기 소오스 트랜지스터(110)가 활성화되거나 비활성화된다. 즉, 상기 제어 회로(240)는 칩이 활성화되는 동안만 로우 레벨의 상기 제어 신호(C)를 발생하게 된다.Referring back to FIG. 2, the voltage conversion circuit of the present invention provides a control circuit 240 for controlling the differential amplifier circuit 200 in an active operation. The control circuit 240 is a chip activation signal (

The control signal C is generated by receiving the internally generated signal PIACT. The control signal C is applied to the gate of the source transistor 110 of the differential amplifier circuit 200, and the source transistor 110 is activated or deactivated according to its level. That is, the control circuit 240 generates the control signal C at the low level only while the chip is activated.

The control circuit 240 is composed of a delay circuit 242 and an output driving circuit 244. The delay circuit 242 receives the signal PIACT and outputs pull-up and pull-down driving signals PU and PD, which are delayed for a predetermined time, and the output driving circuit 244 responds to them. To output the control signal (C).

According to a preferred embodiment of the present invention, the delay circuit 242 includes inverters 114, 116, 122, and 124, a NOR gate 118, and a NAND gate 120. The output drive circuit 244 includes a pull-up transistor 126 and a pull-down transistor 128.

The signal PIACT is applied to each one input terminal of the NOR gate 118 and the NAND gate 120, and the signal PIACT is applied through the inverters 114 and 115 to each other input terminal. Is approved. The input terminal of the inverter 122 is connected to the output terminal of the NOR gate 118 and its output terminal is connected to the gate of the pull-up transistor 126, and the input terminal of the inverter 124 is the NAND gate. It is connected to the output terminal of 120 and its output terminal is connected to the gate of the pull-down transistor 128. The current paths of the pull-up and pull-down transistors 126 and 128 are sequentially connected between the terminal 125 to which the voltage Vrefp is applied and the ground, and at their connection point 109 the source transistor ( 110 is gated.

Here, an external power supply voltage EVC is applied to the power supplies of the inverters 122 and 124, and the voltage Vrefp is higher than or equal to a voltage Vrefa applied to the differential amplifier circuit 200. Is a voltage having The voltage Vrefp is a reference voltage applied to the internal power supply voltage generating circuit generating the internal power supply voltage IVC described above, and dip / overshooting is applied to the internal power supply voltage IVC. Although generated, it generally maintains a constant stable voltage level. And it is obvious to those skilled in the art that the voltage Vrefp can be applied as another voltage having this characteristic.

)에 동기된 신호 (PIACT)에 의해 발생된 풀업 및 풀다운 구동 신호들(PU) 및 (PD)을 보여주는 파형도이다. 그리고, 도 4는 칩 활성화 신호가 인가될 때 종래 및 본 발명에 따른 어레이용 내부 전원 전압(VCCA)의 딥(dip) 정도를 보여주는 파형도이다. 본 발명의 동작은 첨부된 도면들에 의거하여 이하 설명될 것이다.3 is a chip activation signal (

Is a waveform diagram showing pull-up and pull-down driving signals PU and PD generated by a signal PIACT synchronized to the < RTI ID = 0.0 > 4 is a waveform diagram showing a dip level of an internal power supply voltage VCCA for an array according to the related art and the present invention when a chip activation signal is applied. The operation of the present invention will be described below with reference to the accompanying drawings.

)가 하이 레벨에서 로우 레벨로 천이됨과 아울러 신호 (PIACT) 역시 로우 레벨로 천이된다. 이에따라, 상기 신호 (PIACT)가 인가되는 지연 회로(242)에 의해서 로우 레벨의 풀업 및 풀다운 구동 신호들(PU) 및 (PD)이 발생된다. 계속해서, 로우 레벨의 상기 풀업 구동 신호(PU)에 게이팅되는 풀업 트랜지스터(126)가 턴-온된다. 이에 따라, 상기 풀업 트랜지스터(126)를 통해 전압 (Vrefp)의 레벨을 갖는, 즉 하이 레벨의 제어 신호(C)가 차동 증폭 회로(200)의 소오스 트랜지스터(110)로 인가되어 상기 소오스 트랜지스터(110)는 턴-온된다.Referring to FIG. 3, when the chip enters the active state, the chip activation signal (

) Transitions from the high level to the low level, as well as the signal PIACT. Accordingly, low level pull-up and pull-down driving signals PU and PD are generated by the delay circuit 242 to which the signal PIACT is applied. Subsequently, the pull-up transistor 126 gated to the low-level pull-up driving signal PU is turned on. Accordingly, the control signal C having the level of the voltage Vrefp, that is, the high level, is applied to the source transistor 110 of the differential amplification circuit 200 through the pull-up transistor 126, thereby providing the source transistor 110. ) Is turned on.

At this time, when the signal PIACT is activated to reduce the standby current, the pull-down driving signal PD is shifted to the low level after the transition to the low level before the pull-up driving signal PU. In addition, when the signal PIACT is deactivated, the pull-up driving signal PU is first transitioned to the high level and then delayed for a predetermined time so that the pull-down driving signal PD transitions to the high level, that is, the pull-up transistor 126 First the high level is followed by the pull down transistor 128 to the high level.

Subsequently, the differential amplification circuit 200 compares the reference voltage Vrefa and the array internal power supply voltage VCCA and outputs a high or low level comparison signal S_COMP according to the result. If the internal power supply voltage VCCA for the array is lower than the reference voltage Vrefa, the comparison signal S_COMP at a low level is output. Accordingly, the driver 220 is activated to activate the internal power supply for the array. The voltage VCCA is driven at the set voltage level.

Thereafter, when the internal power supply voltage VCCA for the array is boosted to a set voltage level, the comparison signal S_COMP having a high level is output through the differential amplifier circuit 200 to deactivate the driver 220. The internal power supply voltage VCCA for the array is maintained at a constant level without being boosted. If the internal power supply voltage VCCA for the array is decompressed due to internal operation or for some reason, the aforementioned operation is repeatedly performed to remain at its set level.

As such, the voltage level of the signal C output from the control circuit 240 for controlling the source transistor 110 of the differential amplifier circuit 200 is set to the level of the voltage Vrefp instead of the internal power supply voltage IVC. To be provided. If a dip occurs in the internal power supply voltage IVC, the differential amplification circuit 200 is also not affected by the voltage Vrefp that maintains a constant level irrespective of the dip, thereby causing the internal power supply voltage VCCA for the array. Response time due to the deep / overshooting of the?) Can be faster than that of the conventional art.

As described above, by providing a control circuit such that the level of the signal gated to the source transistor of the differential amplifying circuit is applied to its gate, the voltage which is the reference of the internal power supply voltage instead of the internal power supply voltage, Overshooting can prevent the response time of the internal power supply voltage for the array from slowing down. Thus, stable power can be supplied to the cell array.

Claims (7)

In the voltage conversion circuit for converting an external power supply voltage into an internal power supply voltage, A power line for transferring the internal power voltage; Comparison means for outputting a first signal by comparing a reference voltage applied from the outside with the internal power supply voltage when the external power supply voltage is supplied; Drive means for supplying a predetermined current from the external power supply voltage to the internal power supply line in response to the first signal; Control means for generating a control signal at a level equal to or higher than said reference voltage in response to a second signal synchronized with a chip activation signal; And the comparison means activates or deactivates the comparison means. The method of claim 1, The control means, Delay means for receiving the second signal and outputting pull-up and pull-down drive signals with a predetermined time delay; And output drive means for outputting the control signal in response to the pull-up and pull-down drive signals output from the delay means. The method of claim 2, The pull-up and pull-down drive signals and the first signal are driven to a level of the external power supply voltage. The method of claim 1, And the driving means comprises a first PMOS transistor having a source to which the external power supply voltage is applied, a drain connected to the power supply line, and a gate to which the first signal is applied. The method of claim 2, The delay means receives the second signal and delays a predetermined time, the first and second inverters are sequentially connected in series; A NOR gate having one input terminal to which the second signal is applied and the other input terminal connected to an output terminal of the second inverter; A third inverter having an input terminal connected to an output terminal of the NOR gate and an output terminal for outputting the pull-up driving signal; A NAND gate having one input terminal to which the second signal is applied and the other input terminal connected to an output terminal of the second inverter; And a fourth inverter having an input terminal connected to an output terminal of the NAND gate and an output terminal for outputting the pull-down driving signal. The method of claim 5, wherein And the third and fourth inverters are each supplied with the external power supply voltage to their power supply terminals. The method of claim 6, The output drive means A second PMOS transistor having a gate to which the pull-up driving signal is applied, a source to which a voltage equal to or higher than the reference voltage is applied, and a drain connected to a line for transmitting the control signal; And a NMOS transistor having a gate to which the pull-down driving signal is applied, a drain connected to the line, and a source connected to ground.

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