KR20010004665A - High level voltage generator - Google Patents

Abstract

PURPOSE: A high voltage generator is provided to make a variation of a potential difference between a gate and a source of a MOS capacitor inducing a high voltage to a boosting node and largely reduce degree of an electric potential drop to realize maximization of the pumping efficient by low power consumption CONSTITUTION: A high voltage generator includes a precharge portion(10), a switching portion(20), a boosting portion(30), and a boosting node connecting portion(40). The precharge portion selectively precharges both precharge nodes under control of a first pulse signal to an outer power supply voltage level. The switching portion is selectively switched according to the electric potential level of the both precharge nodes and respectively controls connection for both boosting nodes. The boosting portion selectively boosts the both boosting nodes to a high voltage level under control of a second pulse signal being generated with a timing different with the first pulse signal. The boosting node connecting portion selectively connects the both boosting nodes under control of a third pulse signal being generated before the second pulse signal is transitted, and controls so as to reduce the width of an electric potential variation of each boosting node according to an electric charge distribution between two boosting nodes.

Description

High level voltage generator

The present invention relates to a high voltage generator used to generate a high voltage higher than a power supply voltage in a semiconductor memory device. More particularly, the potential drop between the gate sources of a MOS capacitor which induces a high voltage to the boosting node is changed to greatly increase the potential drop. The present invention relates to a high voltage generator that realizes maximization of pumping efficiency by reducing power consumption.

In general, a high voltage (Vpp) pulse generated by a high voltage generator maintains a potential level of more than Vcc + Vt to compensate for the threshold voltage loss (Vt loss) of the transistor. It is widely used in the field of memory circuits such as word line driver, bit line isolation circuit and data output buffer.

1 is a block diagram of a conventional high voltage generator, which detects a potential level of a high voltage fed back from an output terminal and generates a pump enable signal pump_en when the potential level falls below a predetermined voltage. The timing sensing circuit unit 100, the oscillation circuit unit 200 receiving the pump enable signal pump_en to generate a pulse signal osc of a predetermined period, and the pulse signal osc are received, and the timing is adjusted. The control signal generating circuit unit 300 for generating the respective pulse control signals p1, p2, g1, and g2 and the pumping operation according to the state of the control signals p1, p2, g1, and g2 are performed to obtain a high voltage ( And a pumping circuit unit 400 for adjusting the potential of Vpp).

FIG. 2 is a detailed circuit diagram illustrating an exemplary embodiment of the pumping circuit unit 400 illustrated in FIG. 1, wherein both side precharge nodes are under the control of the first pulse signals g1 and g2 generated from the control signal generating circuit unit 300. Precharge means (10) for selectively precharging (N3, N4) to an external power supply voltage (Vext) level; Switching means (20) for selectively switching according to potential levels of the both precharge nodes (N3, N4) to control the connection with both boosting nodes (N1, N2); The second pulse signals p1 and p2 which are different from the first pulse signals g1 and g2 and are generated from the control signal generating circuit unit 300 are signals generated with a phase difference of 180 ° from each other. And boosting means 30 for boosting the two boosting nodes N1 and N2 to a high voltage level Vpp under control.

The precharge means 10 has the first pulse signals g1 and g2 applied to the respective source and drain ends at different timings, and the gate ends thereof are connected to the both precharge nodes N3 and N4, respectively. NMOS transistors MN1 and MN2 diode-connected between MOS capacitors C1 and C2, an external power supply voltage Vext, and each of the two precharge nodes N3 and N4, and the external Each of the NMOS transistors MN3 and MN4 connected in parallel with the two NMOS transistors MN1 and MN2 in a cross-coupling structure between a power supply voltage Vext applying terminal and the two precharge nodes N3 and N4. It is composed of

In addition, the switching means 20 has its gate end connected to both of the precharge nodes N3 and N4, and connected between the external power supply voltage Vext and the boosting node N1 and N2. Each of the NMOS transistors MN5 and MN6 is constituted.

On the other hand, the boosting means 30 is the second pulse signal (p1, p2) is 180 ° out of phase with each other is applied to each source and drain terminal, the gate terminal is connected to both boosting nodes (N1, N2) Each of the MOS capacitors C3 and C4; An NMOS transistor MN7 connected in a diode form between the external power supply voltage Vext applying end and the high voltage Vpp generating end; Two PMOS transistors MP1 and MP2 connected in a cross-coupling structure between the high voltage Vpp generator and both boosting nodes N1 and N2; Both sides of the high voltage Vpp applying terminal and the two boosting nodes N1 and N2 are connected in series with each other, and both gate boosting nodes 9N1 and N2 and the high voltage applying terminal are respectively connected to the gate ends thereof. It consists of two PMOS transistors (MP3 and PM4, MP5 and MP6).

FIG. 3 is a signal waveform diagram of each part of the pumping circuit unit shown in FIG. 2, and a high voltage pumping operation will be described with reference to the drawing.

For the sake of simplicity, only the one side of the precharge node N3 and the boosting node N1 will be described in the operation description.

First, when the pulse signal g1 shown in (b) transitions from 'low' to 'high' as at time t1, a high voltage is induced to the precharge node N3 and the NMOS in the switching means 20 The transistor MN5 is turned on to precharge the potential of the boosting node N1 to the level of the external power supply voltage Vext.

In this state, when the pulse signal p1 is transitioned from 'low' to 'high' as shown in (a), the boosting node N1 is induced at a high voltage by the coupling of the MOS capacitor C3. Lose. The high voltage induced by the boosting node N1 is transferred to the high voltage Vpp generation terminal by the PMOS transistor MP1 to increase the high voltage.

Subsequently, when the pulse signal p1 transitions from 'high' to 'low', the potential of the boosting node N1 is coupled to the pulse signal p1 to decrease the potential, and precharge the dropped potential again. The means 10 supplements the charge with an external power supply voltage Vext.

This operation is repeated two pulse signals (p1, p2) shown in (a) and (c) alternately to increase the potential of the high voltage.

In the prior art which generates a high voltage by the above operation, when two pulse signals p1 and p2 controlling high voltage pumping fall from 'high' to 'low', between these signal applying stages and each of the boosting nodes N1 and N2. Since the capacitance of the MOS capacitors C3 and C4 included in the capacitor is large, a problem arises in that the potential drop width of each of the boosting nodes N1 and N2 increases accordingly.

This phenomenon causes a secondary problem that increases the power consumption required to precharge the potential of the boosting node to a constant potential level.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to change the potential difference between the gate sources of a MOS capacitor which induces a high voltage in a boosting node, thereby greatly reducing the potential drop, thereby pumping efficiency due to low power consumption. To provide a high voltage generator that maximizes the

In order to achieve the above object, the high voltage generator according to the present invention comprises: precharge means for selectively precharging both precharge nodes to an external power supply voltage level under the control of the first pulse signal;

Switching means for selectively switching in accordance with the potential level of the two precharge nodes to control the connection to both boosting nodes, respectively;

Boosting means for boosting both boosting nodes to a high voltage level selectively under the control of a second pulse signal generated at a different timing than the first pulse signal;

A boosting node for selectively connecting the boosting nodes on both sides under the control of the third pulse signal generated before the first pulse signal is transitioned to reduce the potential change width of each boosting node according to the charge distribution between the two boosting nodes. A connecting means;

The first to third pulse signals may be pulse signals generated at different output timings of pulse signals generated from the oscillator for high voltage pumping control.

1 is a block diagram of a conventional high voltage generator

FIG. 2 is a detailed circuit diagram illustrating an embodiment of the pumping circuit part shown in FIG. 1. FIG.

3 is a signal waveform diagram of each pumping circuit part shown in FIG. 2;

4 is a block diagram of a high voltage generator according to the present invention.

FIG. 5 is a detailed circuit diagram illustrating an embodiment of the pumping circuit part shown in FIG. 4. FIG.

FIG. 6 is a graph of capacitance change according to a potential change between gate sources of a MOS capacitor illustrated in FIG. 5.

7 is a signal waveform diagram of each pumping circuit part shown in FIG. 5;

<Description of reference numerals for the main parts of the drawings>

10: precharge means 20: switching means

30: boosting means 40: boosting node connection means

100: potential detection circuit portion 200: oscillation circuit portion

300, 310: control signal generator 400, 410: pumping circuit

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a block diagram of a high voltage generator according to the present invention. When the potential level of the high voltage (Vpp) fed back from the output terminal is sensed and the potential level drops below a predetermined voltage, the pump enable signal pump_en The potential sensing circuit unit 100 for generating a), the oscillation circuit unit 200 for receiving the pump enable signal (pump_en) to generate a pulse signal (osc) of a predetermined period, and receives the pulse signal (osc) A control signal generation circuit unit 310 for generating respective pulse control signals p1, p2, con1, con2, g1, and g2 whose timing is adjusted, and the respective control signals p1, p2, con1, con2, g1, and a pumping circuit unit 410 for performing a pumping operation according to the state of g2) to adjust the potential of the high voltage Vpp.

When the high voltage generator according to the present invention further generates separate pulse control signals con1 and con2 for controlling the operation of the pumping circuit unit 410 connected to the rear end of the control signal generating circuit unit 310, the pumping of the rear end is performed. The circuit unit 410 is received and used for high voltage pumping.

FIG. 5 is a detailed circuit diagram illustrating an exemplary embodiment of the pumping circuit unit illustrated in FIG. 4, wherein both sides of the precharge node N3, under the control of the first pulse signals g1 and g2 generated from the control signal generating circuit unit 310, are illustrated. Precharge means (10) for selectively precharging N4) to an external power supply voltage level Vext; Switching means (20) for selectively switching according to potential levels of the both precharge nodes (N3, N4) to control the connection with both boosting nodes (N1, N2); The second pulse signals p1 and p2 which are different from the first pulse signals g1 and g2 and are generated from the control signal generating circuit unit 310 are signals generated with a phase difference of 180 ° from each other. Boosting means (30) for boosting both boosting nodes (N1, N2) to a high voltage (Vpp) level under control; Under the control of the third pulse signals con1 and con2 generated before the second pulse signals p1 and p2 are transitioned, the two boosting nodes N1 and N2 are selectively connected by connecting the two boosting nodes N1 and N2. Boosting node connecting means 40 for controlling to reduce the potential change of each of the boosting node (N1, N2) in accordance with the charge distribution between the ().

The configuration and operation of the precharge means 10, the switching means 20, and the boosting means 30 are the same as in the prior art shown in FIG. 2 and will be omitted to avoid duplication of description. Will focus on the boosting node connection means 40 to proceed.

First, the boosting node connecting means 40 includes first and second switching units MN12 and MN13 connected between the boosting nodes N1 and N2, respectively; The first and second switching units Mn12 and MN13 under the control of the third pulse signals con1 and con2: these signals are pulse signals generated before the transition of the second pulse signals p1 and p2. First and second connection controllers C5 and C6 for selectively inducing the high voltage to control the connection of both boosting nodes N1 and N2; A precharge unit 1 precharges the potentials of the output terminals N5 and N6 of the first and second connection control units C5 and C6 to the external power supply voltage Vext level.

In the same figure, the first and second switching units are composed of NMOS transistors MN12 and MN13, respectively.

In addition, the first and second connection controllers may include the NMOS transistors in which the third pulse signals con1 and con2 are applied to the source and drain terminals thereof, and the gate terminals thereof constitute the first and second switching units. The first and second MOS capacitors C5 and C6 are connected to the gate ends of the respective MN12 and MN13.

Meanwhile, the precharge unit 1 is diode-connected between an external power supply voltage Vext applying terminal and gate terminals N5 and N6 of the MOS capacitors C5 and C6 constituting the first and second connection controllers. Each of the NMOS transistors MN8 and MN9, the external power supply voltage Vext, and the two nodes N5 and N6 in cross-coupling structure in parallel with the NMOS transistors MN8 and MN9. Each of the connected NMOS transistors 9MN10 and MN11.

FIG. 6 is a graph showing the change in capacitance according to the change in potential between the gate sources of the MOS capacitor shown in FIG. 5. This can be seen from the drawing.

The present invention uses this principle to reduce the capacitance component by adjusting the potential difference Vgs between the gate sources of the MOS capacitors C3 and C4 in the boosting means 30, thereby reducing the capacitance component of the pumping control pulse signals p1 and p2. It becomes a high voltage generator which minimizes the power consumption required to recover the changed potential by reducing the potential change width of both boosting nodes N1 and N2 due to the transition.

FIG. 7 is a signal waveform diagram of each part of the pumping circuit unit shown in FIG. 5, and the operation of the present invention will be described in detail with reference to the drawing.

First, the potential of the boosting node N1 induced to a high voltage by the second pulse signal p1 applied with a signal waveform as shown in (a) shows a potential as shown in (g) and generates a high voltage. It is delivered to the stage to level up the potential of the high voltage.

Thereafter, as shown in (c), the timing is adjusted before the third pulse signal con1 transitions from 'high' to 'low' as shown in (a). By generating, the output terminal N5 potential of the MOS capacitor C5 is controlled to be induced at a high voltage.

Accordingly, the NMOS transistor MN12, which is a switching element in the boosting node connecting means 40, is turned on, thereby connecting both boosting nodes N1 and N2.

Therefore, the potential of the boosting node N1 maintaining a relatively high potential level flows to the other boosting node N2 maintaining a relatively low potential level, and as shown in (g) and (i), the boosting node ( The potential of N1) is lowered by a predetermined potential and the potential of the other boosting node N2 is increased as the potential of the boosting node N1 is lowered.

As the potential of the boosting node N1 is lowered, the potential difference Vgs between the gate sources of the MOS capacitors C3 connected thereto can be lowered, thereby reducing the capacitance component.

As a result, when the second pulse signal p1 transitions from 'high' to 'low', a change range in which the potential of the boosting node N1 falls decreases and is precharged again by the external power supply voltage Vext. It will be able to reduce the amount of current to be.

This operation is performed in the same manner when the other third pulse signal con2 shown in (f) is applied to efficiently perform the high voltage pumping operation.

As described above, according to the high voltage generator according to the present invention, the high voltage pumping efficiency is improved, thereby greatly reducing the amount of external power consumed when the high voltage is generated. In other words, by reducing the total amount of power used by the device, it can contribute to making low-power products.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to make various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the scope of the claims You will have to look.

Claims (5)

Precharge means for selectively precharging both precharge nodes to an external power supply voltage level under the control of the first pulse signal; Switching means for selectively switching in accordance with the potential level of the two precharge nodes to control the connection to both boosting nodes, respectively; Boosting means for boosting both boosting nodes to a high voltage level selectively under the control of a second pulse signal generated at a different timing than the first pulse signal; A boosting node for selectively connecting the boosting nodes on both sides under the control of the third pulse signal generated before the second pulse signal is transitioned to reduce the potential change of each boosting node according to the charge distribution between the two boosting nodes. A connecting means; And the first to third pulse signals are pulse signals generated at different output timings of pulse signals generated from the oscillator for high voltage pumping control. The method of claim 1, The boosting node connecting means may include first and second switching units connected between the boosting nodes, respectively; First and second connection controllers for selectively inducing high voltages to the first and second switching units under the control of the third pulse signal to control the connection of both boosting nodes; And a precharge unit configured to precharge the output terminal potentials of the first and second connection controllers to an external power supply voltage level. The method of claim 2, And the first and second switching units are formed of NMOS transistors. The method of claim 2, The first and second connection controllers may be configured such that the third pulse signal is applied to each of the source and drain terminals, and the gate terminal includes first and second MOS capacitors connected to the first and second switching units, respectively. High voltage generator characterized by. The method of claim 2, The precharge unit may include first and second NMOS transistors connected in a diode form between an external power supply voltage supply terminal and an output terminal of the first and second connection controllers, respectively; And third and fourth NMOS transistors connected in parallel with the first and second NMOS transistors in a cross-coupling structure between the external power voltage applying stage and the output terminals of the first and second connection controllers, respectively. High voltage generator.