KR100813549B1 - Internal volgage generating circuit - Google Patents

Abstract

An internal voltage generating circuit is provided to achieve stable operation by overcoming threshold voltage loss at a charge pump, by increasing a voltage of a clock signal by increasing a supply voltage of an oscillator. A level detector(500) outputs a detection signal by comparing a reference voltage with an internal voltage. An oscillator(600) operates according to the output of the level detector. A pumping unit(10) generates a boosted clock signal by boosting an output signal of the oscillator, and generates an internal voltage in response to the boosted clock signal. The pumping unit includes a clock boosting stage(700) generating the boosted clock signal by boosting the output signal of the oscillator and a charge pump stage(800) outputting the internal voltage in response to the boosted clock signal.

Description

Internal Voltage Generating Circuit

1 is a circuit diagram of a typical charge pump (Charge Pump),

2 is a circuit diagram of a Dickson Charge Pump,

3 is a block diagram of an internal voltage generation circuit according to an embodiment of the present invention;

4 is a block diagram illustrating an embodiment of a clock boosting stage according to FIG. 3;

5 is a detailed circuit diagram of a clock boosting stage according to FIG. 4;

6 is a detailed circuit diagram illustrating another embodiment of a clock boosting stage according to FIG. 3;

7 is an operational waveform diagram of FIG. 6;

8A and 8B are circuit diagrams in which the capacitor according to FIG. 5 is an NMOS or PMOS;

9 is a block diagram of an internal voltage generation circuit according to another embodiment of the present invention;

FIG. 10 is a detailed circuit diagram of the selector according to FIG. 9.

<Description of the symbols for the main parts of the drawings>

10 pumping means 100 input unit

210,220: First and second bias stage 310,320: First and second pump stage

410,420: first and second transfer transistor unit 500: VPP level detector

600: oscillator 700: clock boosting stage

800: charge pump stage 900: comparison unit

1000: selection

The present invention relates to a semiconductor memory device, and more particularly, to an internal voltage generation circuit for increasing the efficiency of a charge pump.

The memory semiconductor requires a VPP voltage higher than the supply voltage VDD. In memory, the VPP voltage is generated using an internal voltage generator.

The conventional VPP generation circuit is composed of a VPP level detector, an oscillator, and a charge pump stage. The VPP level detector compares the VPP generated at the charge pump stage with the reference voltage VREF and outputs the oscillator driving signal when the VPP is lower than the reference voltage VREF. Otherwise, the VPP level detector outputs the oscillator non-driving signal. do. The oscillator generates a clock signal according to the output signal of the VPP level detector. The charge pump stage receives the clock signal to generate the VPP voltage.

The charge pump raises the voltage of the floating node using coupling of the capacitor. In practice, however, the charge pump circuit uses MOS transistors, resulting in a threshold voltage loss (Vth Loss), which reduces the efficiency of the charge pump. In addition, since the threshold voltage Vth is further increased by the body effect, the efficiency of the charge pump is further reduced.

1 is a circuit diagram of a typical charge pump.

The basic principle is that Node A is charged to VDD when the first switch is closed. At this time, when the first switch is opened and the clock signal CLK rises to 'high', the node A voltage ideally rises to 2VDD. When the second switch is closed, the node B voltage becomes VDD by node sharing with node A. When the second switch is opened and the clock signal CLK is at a low level, the node B voltage rises above 2VDD. I will go. When the third switch is closed, the node C voltage is transferred to the VPP terminal.

Using this principle, the Dickson Charge Pump, which is often used as a charge pump, is composed of transistors instead of switches.

2 is a basic circuit diagram of a Dickson charge pump.

The Dickson charge pump is configured using an NMOS transistor instead of the switch of FIG. However, the problem with such a Dickson charge pump is that a threshold voltage loss occurs in the NMOS transistor. This decreases the efficiency of the charge pump and makes it difficult for the VPP to meet the target. This is not just a problem with Dickson charge pumps, but also with all charge pumps in use today. Moreover, since the threshold voltage becomes larger due to the body effect, the threshold voltage loss becomes more and more a critical factor as the supply voltage is lowered.

In the above description, the problem has been described by taking the high voltage VPP rising by increasing the supply voltage VDD, but the bulk bias voltage generated by using the charge pump to apply reverse bias to the bulk of the transistor of the semiconductor memory device ( In the case of VBB), similarly to the case of the high voltage VPP, a loss due to a threshold voltage occurs.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and an object thereof is to provide a stable internal voltage generation circuit by overcoming a threshold voltage loss in a charge pump.

According to an aspect of the present invention, there is provided an internal voltage generation circuit including a level detector configured to output a detection signal according to a comparison result by inputting a reference voltage and an internal voltage; An oscillator operating according to the output of the level detector; boosting an output signal of the oscillator to generate a boosted clock signal, and pumping means for generating an internal voltage in response to the boosted clock signal.

In addition, the internal voltage generation circuit according to another embodiment of the present invention includes a level detector for outputting a detection signal according to the comparison result by receiving a reference voltage and the internal voltage; an oscillator operating in accordance with the output of the level detector; A charge pump stage for receiving an output of the oscillator and outputting an internal voltage; A comparison unit comparing the output of the charge pump stage with a supply voltage; And a selector configured to output one of the output of the charge pump stage and the supply voltage as a driving voltage of the oscillator according to the output of the comparator.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Hereinafter, since the same principle is applied to the internal voltage generation circuit of the present invention as well as the VPP voltage generation circuit, the following VPP generation circuit will be described as an example.

3 is a block diagram of an internal voltage generation circuit according to an embodiment of the present invention.

As shown, the internal voltage generation circuit of the present invention comprises the VPP level detector 500, the oscillator 600, and the pumping means 10. The clock CLK from the oscillator 600 is boosted by the pumping means 10 to generate a clock voltage HCLK of a higher voltage level to generate an internal voltage. The VPP level detector 500 supplies an enable signal to the oscillator 600 until the output of the pump means 10 reaches the VPP target value. The pump means 10 consists of a clock boosting stage 700 and the charge pump 800. The clock CLK from the oscillator is boosted by the clock boosting stage 700 and supplied to the charge pump stage 800. As a result, a higher voltage level clock HCLK is supplied to the charge pump stage 800 to increase the efficiency of the charge pump stage 800.

 4 is a block diagram illustrating an embodiment of a clock boosting stage 700 of FIG. 3.

As shown in the drawing, the clock boosting stage 700 is applied with a clock signal CLK, and according to the clock signal CLK, the first bias stage 210 for precharging the voltage level of the first node N1 to a predetermined voltage. ), A first pumping stage 310 for boosting the voltage of the first node N1, and a first transfer transistor unit 410 for transferring the boosted voltage to an output terminal (a fifth node).

The first bias stage 210 always maintains the first node N1 voltage level above a certain voltage. The first pumping stage 310 outputs a voltage obtained by increasing the clock voltage to the power supply voltage VDD due to a coupling effect according to the clock signal CLK. The first transfer transistor unit 410 sends or receives current to the output terminal N5 according to the pumped voltage.

FIG. 5 is a diagram for describing a detailed circuit configuration of an embodiment of the clock boosting stage 700 according to FIG. 4.

The first bias terminal 210 is connected to a drain electrode and a gate electrode of the first NMOS MN1, and a power supply voltage VDD is supplied to the drain electrode. As a result, the first node N1, which is the source electrode of the first NMOS MN1, is always precharged to maintain a predetermined voltage level VDD-Vth or more.

The first pumping stage 310 is composed of a first capacitor (C1). The clock signal CLK is applied to one electrode, and one electrode is connected to the first NMOS MN1 source terminal N1, which is the first bias terminal 210. Therefore, when the clock signal CLK is 'high', the voltage of the first node N1 rises to 2VDD-Vth (ideal) by the coupling of the first capacitor C1. When the clock signal CLK is 'low', the voltage of the first node N1 maintains VDD-Vth.

The first transfer transistor unit 410 includes a second inverter IV2 that inverts the clock signal CLK, a first PMOS MP1, and a second NMOS MN2. The output of the second inverter IV2 is connected to the gate electrode of the first PMOS MP1 and the second NMOS MN2. The drain electrode of the first PMOS MP1 and the drain electrode of the second NMOS MN2 are connected to each other. The operating principle is that the output of the second inverter IV2 is 'low' when the clock signal CLK is 'high'. As a result, the first PMOS MP1 is turned on and the second NMOS MN2 is turned off. As a result, the output voltage HCLK becomes 2VDD-Vth. When the clock signal CLK is 'low', the output of the second inverter IV2 is 'high'. As a result, the first PMOS MP1 is turned off and the second NMOS MN2 is turned on. As a result, the voltage of the fifth node N5 becomes 'low'. Therefore, when the clock signal CLK is VDD, the output signal is 2VDD-Vth, and when the clock signal CLK is 'low', the output signal is 'low'.

6 is a diagram for describing a detailed circuit configuration of another embodiment of the clock boosting stage 700 of FIG. 3.

The clock boosting stage 700 illustrated in FIG. 6 shows a circuit configuration used when the charge pump stage 800 simultaneously receives HCLK and HCLKb, which is a signal whose phase is inverted.

The clock boosting stage 700 may include an input unit 100, a first bias stage 210, a second bias stage 220, a first pumping stage 310, a second pumping stage 320, and a first transfer transistor unit. 410 and the second transfer transistor unit 420.

The input unit 100 includes a first inverter IV1 for generating an inverted clock signal CLKb. That is, when the clock signal CLK is 'high', the inverted clock signal CLKb is 'low'.

The circuit configuration of the second bias stage 220 is the same as that of the first bias stage 210. The second bias terminal 220 is connected to a drain electrode and a gate electrode of the third NMOS MN3 and is supplied with a power supply voltage VDD. Accordingly, the second node N2, which is the source electrode of the third NMOS MN3, is always precharged to maintain the predetermined voltage level VDD-Vth or more.

The circuit configuration of the second pumping stage 320 is the same as that of the first pumping stage 310. The second pumping stage 320 includes a second capacitor C2, one electrode N3 is applied with an inverted clock signal CLKb, and one electrode is the third NMOS of the second bias terminal 220. (MN3) is connected to the source terminal (N2). Therefore, when the inverted clock signal CLKb is 'high', the voltage of the second node N2 is increased to 2VDD-Vth by the coupling of the second capacitor C2. When the inverted clock signal CLKb is 'low', the voltage of the second node N2 maintains VDD-Vth.

The circuit structure of the second transfer transistor unit 420 is the same as that of the first transfer transistor unit 410. The second transfer transistor unit 420 includes a third inverter IV3, a second PMOS MP2, and a fourth NMOS MN4 for inverting the inverted clock signal CLKb. An output of the third inverter IV3 is connected to the gate electrode of the second PMOS MP2 and the fourth NMOS MN4. In addition, the drain electrode of the second PMOS (MP2) and the drain electrode of the fourth NMOS (MN4) are connected. The operating principle is that the output of the third inverter IV3 is 'low' when the inverted clock signal CLKb is 'high'. As a result, the second PMOS MP2 is turned on and the fourth NMOS MN4 is turned off. As a result, the inverted output signal HCLKb at the sixth node becomes 2VDD-Vth. When the clock signal CLK is 'low', the output of the third inverter IV3 is 'high'. Thus, the second PMOS MP2 is turned off and the fourth NMOS MN4 is turned on. As a result, the inversion output signal HCLKb becomes 'low' at the sixth node N6.

FIG. 7 is an operation waveform diagram of the clock boosting stage 700 shown in FIG. 6.

As shown, the clock signal CLK voltage level is VDD. When the clock signal CLK is applied, the output signal HCLK and the inverted output signal HCLKb have increased in voltage level by ΔV (= VDD-Vth) compared to the clock signal CLK.

8A and 8B are circuit diagrams using MOSs instead of the capacitors of FIG. 5.

8A and 8B show that the gate terminal and the source terminal of the NMOS and PMOS are connected to operate as a capacitor. Therefore, the NMOS or the PMOS is used instead of the capacitor of FIG. 5, and the voltage of the first node N1 is boosted by the coupling effect according to the clock signal CLK.

9 is a detailed circuit diagram showing another embodiment of the internal voltage generation circuit of the present invention.

As shown, the internal voltage generation circuit includes the VPP level detector 500, the oscillator 600, the charge pump stage 800, the comparator 900, and the selector 1000.

The VPP level detector 500, the oscillator 600, and the charge pump stage 800 have the same configuration as in FIG. 3. The charge pump stage 800 boosts the clock signal to generate VPP. The comparator 900 compares two signals in which VPP and the supply voltage VDD are reduced at a predetermined ratio, and outputs 'high' or 'low' depending on which signal is large. The selector 1000 inputs the VPP or the supply voltage VDD to the VDD supply terminal of the oscillator 600 according to the output signal of the comparator 900. That is, the selector 1000 outputs the VPP when the VPP is greater than the supply voltage VDD, and outputs the supply voltage VDD when the supply voltage VDD is greater than the VPP. Thus, the oscillator's drive voltage receives a higher voltage, producing a higher clock signal.

FIG. 10 is a detailed circuit diagram of the selector 1000 of FIG. 9.

As shown, the selector 1000 includes two inverters and two pass gates. The supply voltage VDD is input to the first pass gate PG1, and the input signal of the selector 1000 is input to the PMOS gate of the first pass gate PG1. The inverted signal of the fourth inverter IV4 is input to the NMOS gate of the first pass gate PG1.

The VPP is input to the second pass gate PG2, and the input signal of the selector is input to the NMOS gate of the second pass gate PG2. The inverted signal of the fifth inverter IV5 is input to the PMOS gate of the second pass gate PG2.

Therefore, when the input signal IN1 of the selector 1000 is 'high', the second pass gate PG2 is activated to output the VPP. That is, since the NMOS and the PMOS of the second pass gate PG2 are turned on, and the NMOS and the PMOS of the first pass gate PG1 are turned off, VPP, which is an input voltage of the second pass gate PG2, is output. .

When the input signal IN1 of the selector 1000 is 'low', the first pass gate PG1 is activated to output the supply voltage VDD. That is, since the NMOS and the PMOS of the first pass gate PG1 are turned on, and the NMOS and the PMOS of the second pass gate PG2 are turned off, the supply voltage, which is an input voltage of the first pass gate PG1, VDD) is output.

In addition, in the circuit configuration of the selector 1000, a circuit configuration in which VPP is input to the first pass gate PG1 and the supply voltage VDD is input to the second pass gate PG2 is also possible. You will know. That is, when the input signal IN1 of the selector 1000 is 'high', the second pass gate PG2 is activated to output the supply voltage VDD, and when the input signal IN1 is 'high', the first pass gate is 'low'. This is the case where (PG1) is activated to output the VPP.

In addition, the internal voltage generation circuit according to the present invention is applicable to the VBB supply circuit as well as the VPP supply circuit.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

The present invention has the effect of generating a clock signal of a higher voltage than the reference clock signal. In particular, by boosting the clock signal voltage before the clock signal is input to the charge pump, the threshold voltage (Vth) loss of the charge pump can be overcome, thereby reaching a more stable internal voltage target.

In addition, since the clock boosting circuit is arranged in front of the charge pump circuit, it is possible to supply a high voltage clock signal to several charge pump circuits at the same time, so that the layout of the clock pump circuit increases the clock voltage. It is also advantageous for area reduction.

Further, in another embodiment of the internal voltage generation circuit of the present invention, by increasing the supply voltage of the oscillator, the voltage of the clock signal may be increased to overcome the threshold voltage loss of the charge pump, and the target value of the stable internal voltage may be reached.

Claims (14)

A level detector configured to output a detection signal according to a comparison result by inputting a reference voltage and an internal voltage; An oscillator operating in response to the output of the level detector; And pumping means for boosting an output signal of the oscillator to generate a boosted clock signal and to generate an internal voltage in response to the boosted clock signal. The method of claim 1, The pumping means, A clock boosting stage configured to boost the output signal of the oscillator to generate the boosted clock signal; And a charge pump stage configured to output the internal voltage in response to the boosted clock signal. The method of claim 2, The clock boosting stage is; A first bias stage for precharging the first node voltage level to a constant voltage level; A first pumping stage for boosting the first node voltage according to an output signal of the oscillator; And And a first transfer transistor unit configured to transfer a boosted output signal to the charge pump stage. The method of claim 3, wherein An input unit for receiving the clock signal and outputting an inverted clock signal; A second bias stage for precharging the second node voltage level to a constant voltage level; A second pumping stage boosting the second node voltage according to the inverted clock signal; And And a second transfer transistor unit configured to transfer a boosted inverted output signal to the charge pump stage. The method of claim 4, wherein The input unit includes an internal voltage generation circuit. The method according to claim 4 or 5, The first and second bias stages are internal voltage generation circuits in which gate and drain electrodes of an NMOS are connected to a supply voltage. The method according to claim 4 or 5, The first and second transfer transistor units are connected to the drain electrode of the NMOS and the drain electrode of the PMOS, the internal voltage generation circuit of the gate electrode of the NMOS and the gate electrode of the PMOS. The method of claim 7, wherein The first and second transfer transistor unit is an internal voltage generation circuit connected to the output of the inverter to the gate electrode of the NMOS and the PMOS. The method of claim 3, wherein The first bias stage is an internal voltage generation circuit in which the gate electrode and the drain electrode of the NMOS are connected to the supply voltage. The method of claim 3, wherein And the first transfer transistor unit is connected to the drain electrode of the NMOS and the drain electrode of the PMOS, and the gate electrode of the NMOS and the gate electrode of the PMOS are connected to each other. The method of claim 10, The first transfer transistor unit is an internal voltage generation circuit connected to the output of the inverter to the gate electrode of the NMOS and the PMOS. A level detector configured to output a detection signal according to a comparison result by inputting a reference voltage and an internal voltage; An oscillator operating in response to the output of the level detector; A charge pump stage for receiving an output of the oscillator and outputting an internal voltage; A comparison unit comparing the output of the charge pump stage with a supply voltage; And And a selector configured to output one of an output of the charge pump stage and the supply voltage as a driving voltage of the oscillator according to an output of the comparator. The method of claim 12, And the selector outputs a higher voltage between the output of the charge pump stage and the supply voltage. The method of claim 13, The selection unit, A first pass gate configured to provide or block the supply voltage to an output terminal according to an output of the comparator; And And a second pass gate configured to block or provide an output of the charge pump stage to the output stage according to an output of the comparator.

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