KR20010003057A - Method of forming resist pattern for semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a resist pattern of a semiconductor device is provided to uniformly control critical dimension of a contact hole in forming contact holes of different sizes, by performing an exposure regarding a resist layer using a reticle with patterns having different light transmissivities to make the resist patterns have the same volume, and by flowing the resist layer pattern. CONSTITUTION: A resist layer is applied on a semiconductor substrate. Exposure and developing processes are performed regarding the resist layer. The first resist pattern(32A1,32A2) which has the first height, the first width and the first volume and is separated by the first interval, is formed in the first region of the semiconductor substrate. The second resist pattern(32B1,32B2) which has the second height higher than the first height, the second width wider than the first width and the second volume which is almost the same as the first volume, is separated by the second interval broader than the first interval, is formed in the second region of the substrate. The first and second resist patterns are flowed.

Description

Method of forming resist pattern for semiconductor device

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a resist pattern of a semiconductor device capable of realizing a fine contact hole according to high integration.

In order to overcome the limitations of the optical wavelength for forming fine contact holes due to the recent high integration, a resist flow technique has been proposed.

1A and 1B are cross-sectional views illustrating a method of forming a resist pattern using the resist flow technique described above.

Referring to FIG. 1A, a resist film is coated, exposed, and developed on a semiconductor substrate 10 having an insulating film 11 formed thereon to form a resist pattern 12 spaced at a first interval A1. Then, the resist pattern 12 is flowed in a thermal process to smooth its vertical profile, so that the gap between the resist patterns 12 is smaller than the first gap A1 as shown in FIG. 1B. Decrease to (A2). Thereafter, although not illustrated, the insulating layer 11 is etched to expose the substrate 10 by using the resist pattern 12 as an etching mask to form a contact hole having a size of the second gap A2.

Since the gap between them is narrowed by the flow of the resist pattern, contact holes can be formed due to high integration.

On the other hand, the resist amount depends on the size of the contact hole and the duty ratio of the light waveform. Therefore, as described above, in the case of forming contact holes having the same size, the duty ratio of the light waveform is the same and the amount of the resist is the same, so it is easy to adjust the CD (critical dimension) of the contact holes. On the other hand, in the case of forming contact holes of different sizes, since the duty ratios of the optical waveforms are different from each other, the widths of the resist patterns and the intervals therebetween are different. Accordingly, since the volume of the resist pattern is different from each other and the flow volume of the resist pattern is not easily adjusted, uniform CD adjustment of the contact hole is not easy, and thus, there is a difficulty in implementing the contact hole due to high integration.

Accordingly, an object of the present invention is to provide a method of forming a resist pattern of a semiconductor device capable of easily implementing fine contact holes having different sizes.

1A and 1B are cross-sectional views for explaining a resist pattern forming method of a conventional semiconductor device.

2A and 2B are cross-sectional views illustrating a method of forming a resist pattern in a semiconductor device according to an embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

30: semiconductor substrate

31: insulating film

32A1, 32A2: first resist pattern

32B1, 32B2: second resist pattern

100: reticle

100A1, 100A2: first pattern

100B1, 100B2: second pattern

W1, W2: width of resist pattern

H1, H2: height of resist pattern

C1, C2, C2, C4: gap between resist patterns

I, II: first and second regions

In order to achieve the object of the present invention described above, in accordance with the present invention, a resist film is applied onto a semiconductor substrate, and the resist film is exposed and developed to have a first height, a first width, and a first volume spaced at a first interval. A first resist pattern is formed in the first region of the substrate, the first resist pattern having a second height lower than the first height, a second width wider than the first width, and a second volume substantially equal to the first volume; After forming a second resist pattern having a second gap wider than the gap in the second region of the substrate, the first and second resist patterns are flowed.

In the present embodiment, the exposure of the resist film is disposed spaced apart at first intervals on the opposite portions of the first region and is spaced apart at the second interval on the first pattern having a first transmittance and on the opposite portions of the second region. It proceeds using a reticle having a second pattern having a second transmittance higher than the first transmittance.

In addition, the first pattern is a light blocking material such as a chromium pattern having a transmittance of 0%, and the second pattern is a light transmitting material having a transmittance of 5 to 10%. In addition, the first pattern is a light transmitting material having a transmittance of 5 to 10%, and the second pattern is a light transmitting material having a transmittance of 10 to 20%.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

2A and 2B are cross-sectional views illustrating a method of forming a resist pattern in a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 2A, an insulating film 21 is formed on a semiconductor substrate 20 on which first and second regions I and II in which contact holes of different sizes are to be formed are formed, and on the insulating film 21. A resist film is applied. Then, the photoresist film is exposed and developed by using the reticle 100, and as shown in FIG. 2A, the first space H1 has the first height H1, the first width W1, and the first volume. The first resist patterns 32A1 and 32A2 spaced apart from C1) are formed in the first region I, the second height H2 lower than the first height H1, and the second wider than the first width W1. Second resist patterns 32B1 and 32B2 are formed having a width W2 and a second volume approximately equal to the first volume and having a second interval C2 wider than the first interval C1.

Here, the reticle 100 is disposed at opposite portions of the first region I at a first interval C1 and is spaced apart from the first patterns 100A1 and 100A2 having the first transmittance and the second region II. The second portions 100B1 and 100B2 are disposed in the opposite portions to be spaced apart at the second interval C2 and have a second transmittance higher than the first transmittance. For example, when the first patterns 100A1 and 100A2 are light blocking materials such as chromium patterns having a transmittance of 0%, the second patterns 100B1 and 100B2 are light transmitting materials having a transmittance of 5 to 10%. When the first patterns 100A1 and 100A2 are light transmitting materials having a transmittance of about 5 to 10%, preferably about 6%, the second patterns 100B1 and 100B2 have a transmittance of about 10 to 20%, preferably about 18%. It is a light transmitting material having.

As a result, the upper portion of the resist film in the second region (II) is shallowly exposed and removed during exposure, so that the height is lower than that of the first resist patterns 32A1 and 32A2.

Then, the first and second resist patterns 32A1, 32A2, 32B1, and 32B2 are flowed in a thermal process to smooth their vertical profiles, as shown in FIG. 2B, to form the first resist patterns 32A1 and 32A2. Reduce the space between the third space (C3) smaller than the first space (C1), and the space between the second resist pattern (32B1, 32B2) to the fourth space (C4) less than the second space (C2) Decrease. Subsequently, although not shown, the insulating film 21 is etched to expose the substrate 20 using the first and second resist patterns 32A1, 32A2, 32B1, and 32B2 as an etching mask to form third and fourth gaps ( Contact holes having the sizes C3 and C4) are formed, respectively.

According to the present invention described above, by using a reticle having a pattern having a different light transmittance, the resist film is exposed to adjust the volume of the resist patterns in the same manner, and then the resist film pattern is flowed to provide contact holes of different sizes. Since the CD can be uniformly adjusted during the formation of the contact hole, the contact hole can be easily formed due to high integration.

In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.

Claims (4)

Applying a resist film on the semiconductor substrate; Exposing and developing the resist film; A first resist pattern having a first height, a first width, and a first volume, spaced at a first interval, is formed in the first region of the substrate, and has a second height lower than the first height and wider than the first width. Forming a second resist pattern in a second region of the substrate, the second resist pattern having a second width and a second volume substantially equal to the first volume and having a second interval wider than the first interval; And flowing the first and second resist patterns. The method of claim 1, wherein the exposure of the resist film comprises: a first pattern spaced apart from each other at the first interval on an opposite portion of the first region and having a first transmittance; Forming a resist pattern of the semiconductor device by using a reticle having a second pattern disposed at opposite portions of the second region at the second interval and having a second transmittance higher than the first transmittance Way. The semiconductor device of claim 2, wherein the first pattern is a light blocking material such as a chromium pattern having a transmittance of 0%, and the second pattern is a light transmitting material having a transmittance of 5 to 10%. Resist Pattern Formation Method. The resist pattern of claim 2, wherein the first pattern is a light transmissive material having a transmittance of 5 to 10%, and the second pattern is a light transmissive material having a transmittance of 10 to 20%. Formation method.