KR20010002214A - A semiconductor packages and manufacturing method for it - Google Patents

A semiconductor packages and manufacturing method for it Download PDF

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Publication number
KR20010002214A
KR20010002214A KR1019990021904A KR19990021904A KR20010002214A KR 20010002214 A KR20010002214 A KR 20010002214A KR 1019990021904 A KR1019990021904 A KR 1019990021904A KR 19990021904 A KR19990021904 A KR 19990021904A KR 20010002214 A KR20010002214 A KR 20010002214A
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South Korea
Prior art keywords
semiconductor
circuit board
semiconductor chip
attached
package
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KR1019990021904A
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Korean (ko)
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KR100393095B1 (en
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양준영
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마이클 디. 오브라이언
앰코 테크놀로지 코리아 주식회사
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Priority to KR10-1999-0021904A priority Critical patent/KR100393095B1/en
Publication of KR20010002214A publication Critical patent/KR20010002214A/en
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B65—CONVEYING; PACKING; STORING; HANDLING THIN OR FILAMENTARY MATERIAL
    • B65D—CONTAINERS FOR STORAGE OR TRANSPORT OF ARTICLES OR MATERIALS, e.g. BAGS, BARRELS, BOTTLES, BOXES, CANS, CARTONS, CRATES, DRUMS, JARS, TANKS, HOPPERS, FORWARDING CONTAINERS; ACCESSORIES, CLOSURES, OR FITTINGS THEREFOR; PACKAGING ELEMENTS; PACKAGES
    • B65D75/00—Packages comprising articles or materials partially or wholly enclosed in strips, sheets, blanks, tubes, or webs of flexible sheet material, e.g. in folded wrappers
    • B65D75/52—Details
    • B65D75/58—Opening or contents-removing devices added or incorporated during package manufacture
    • B65D75/66—Inserted or applied tearing-strings or like flexible elements
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B65—CONVEYING; PACKING; STORING; HANDLING THIN OR FILAMENTARY MATERIAL
    • B65D—CONTAINERS FOR STORAGE OR TRANSPORT OF ARTICLES OR MATERIALS, e.g. BAGS, BARRELS, BOTTLES, BOXES, CANS, CARTONS, CRATES, DRUMS, JARS, TANKS, HOPPERS, FORWARDING CONTAINERS; ACCESSORIES, CLOSURES, OR FITTINGS THEREFOR; PACKAGING ELEMENTS; PACKAGES
    • B65D33/00—Details of, or accessories for, sacks or bags
    • B65D33/004—Information or decoration elements, e.g. level indicators, detachable tabs or coupons

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  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE: A chip stack ball grid array package, as well as a manufacturing method therefor, is provided to realize a thinner package, more input/output terminals, and better productivity. CONSTITUTION: For a chip stack ball grid array package, two semiconductor chips(21,22) are provided facedown to a circuit substrate(10). The second chip(22) smaller than the first chip(21) is sandwiched between the first chip(21) and the circuit substrate(10). The circuit substrate(10) has a plurality of slot holes(11) through which circuitry patterns(3) on the substrate(10) are electrically connected to the first and second chips(21,22) by wires(4). The wire-connected portions are sealed with resin compound(5). Additionally, a plurality of solder balls(6) are provided as input/output terminals to the circuit substrate(10).

Description

반도체패키지와 그 제조방법{A SEMICONDUCTOR PACKAGES AND MANUFACTURING METHOD FOR IT}Semiconductor package and manufacturing method {A SEMICONDUCTOR PACKAGES AND MANUFACTURING METHOD FOR IT}

본 발명은 BGA반도체패키지와 그 제조방법에 대한 것으로, 더욱 상세하게는 하나의 회로기판에 2개의 반도체칩을 설치하여 입출력수를 확장할 수 있도록 한 반도체패키지와 그 제조방법에 관한 것이다.The present invention relates to a BGA semiconductor package and a method for manufacturing the same, and more particularly, to a semiconductor package and a method for manufacturing the same, which can expand the number of input and output by installing two semiconductor chips on one circuit board.

일반적으로 BGA(Ball Grid Array)반도체패키지는 회로패턴(3)이 인쇄된 플라스틱 재질의 회로기판(1)에 한 개의 반도체칩(2)을 부착하고 이 반도체칩(2)과 회로패턴(3)을 와이어(4)로 본딩 연결한 후 회로의 보호를 위해 컴파운드수지(5)로 성형하고 동 회로기판(1)의 저면에 각각의 회로패턴(3)과 연결되는 솔더볼(6)을 융착시켜서 만들어지게 된다.In general, a ball grid array (BGA) semiconductor package has one semiconductor chip 2 attached to a circuit board 1 made of a plastic material on which a circuit pattern 3 is printed, and the semiconductor chip 2 and the circuit pattern 3 are attached. Is bonded by wire (4) and then molded by compound resin (5) for protection of the circuit, and made by welding solder balls (6) connected to each circuit pattern (3) on the bottom of the copper circuit board (1) You lose.

따라서, 기존의 리드프레임을 이용하는 반도체패키지에 비해 반도체패키지의 크기를 키우지 않은 상태에서 상대적으로 많은 수의 입출력을 확보할 수 있게 되었다.Therefore, a relatively large number of input and output can be secured without increasing the size of the semiconductor package compared to the conventional semiconductor package using the lead frame.

그러나, 최근에는 여기에 만족하지 않고 보다 많은 입출력수를 확보하기 위해 두 개의 반도체패키지를 적층시켜서 결국 2개의 반도체칩을 공유토록하는 반도체패키지의 제조기술이 개발되어 반도체패키지의 대용량화를 실현하는 계기를 마련할 수 있게 되었다.(도 1)However, in recent years, the semiconductor package manufacturing technology has been developed to stack two semiconductor packages and eventually share two semiconductor chips in order to secure more input / output numbers, thereby realizing a large capacity of the semiconductor package. It became possible to prepare. (Fig. 1)

그러나, 종래의 이러한 단순 적층형 반도체패키지는 같은 성질을 갖는 두 개의 반도체칩을 리드프레임의 위·아래로 적층시키는 구조이기 때문에 패키지 크기의 증가로 인해 반도체패키지의 전체 부피를 증대시키게 되는 문제점을 낳게 되고, 제조과정에서 반도체칩을 부착하거나 와이어를 본딩연결하는 과정이 복잡하여(자재를 뒤집어서 작업하는 과정을 반복해야 함) 작업성을 크게 떨어뜨리게 되며, 나아가 마더보드(M/B) 상면에 실장되는 반도체패키지의 입출력단자수를 제한하게 되는 역작용을 하게 되는 또다른 문제점이 지적되어 왔었다.However, since the conventional simple stacked semiconductor package is a structure in which two semiconductor chips having the same property are stacked up and down the lead frame, the size of the semiconductor package is increased due to the increase in package size. In the manufacturing process, the process of attaching the semiconductor chip or bonding the wire is complicated (the process of inverting the material should be repeated), which greatly reduces the workability, and furthermore, it is mounted on the motherboard (M / B). Another problem has been pointed out that adversely affects the number of input and output terminals of semiconductor packages.

그리고, 그와 더불어 상기와 같은 단순 적층형 반도체패키지에 있어서는 위·아래로 부착되는 반도체칩이 반드시 동일 성질의 것이어야 한다는 제약으로 인해 반도체패키지의 특성이 제한되어 결국 상품성을 저하시키는 일 요인이 되어 왔었다.In addition, in the above-mentioned simple stacked semiconductor package, the characteristics of the semiconductor package have been limited due to the restriction that the semiconductor chip attached to the top and the bottom must be of the same property, which in turn has deteriorated the commerciality. .

이에, 본 발명에서는 상기와 같은 종래의 반도체패키지가 갖는 제반문제점을 해결하기 위하여 구성 및 기능이 보강된 새로운 반도체패키지를 창안하게 된 것으로, 본 발명의 목적은 한 개의 반도체패키지 내에 다수의 반도체칩을 적층하면서도 패키지의 전체 크기가 거의 칩사이즈의 얇은 형태를 갖는 반도체패키지를 제공하는데 있다. 그리고 본 발명의 다른 목적은 종래의 제한된 입출력 단자에 비하여 보다 많은 입출력(I/O) 단자수를 구비토록 함과 동시에 매우 양호한 작업성을 갖는 반도체패키지를 제조하는데 있으며, 본 발명의 또다른 목적은 구조의 다양화를 통한 고품격의 반도체패키지를 제공토록 하는데 있다.Accordingly, in the present invention, to solve the problems of the conventional semiconductor package as described above, a new semiconductor package with enhanced configuration and function is invented. An object of the present invention is to provide a plurality of semiconductor chips in one semiconductor package. The purpose of this invention is to provide a semiconductor package having a thin shape of a chip size while stacking the overall size of the package. In addition, another object of the present invention is to provide a semiconductor package having a very good workability while at the same time having a larger number of input / output (I / O) terminals than the conventional limited input and output terminals, another object of the present invention is It is to provide high quality semiconductor package through the diversification of structure.

도 1은 종래의 적층형 반도체패키지 구성도1 is a configuration diagram of a conventional stacked semiconductor package

도 2는 본 발명에 의한 반도체패키지 구성도2 is a schematic view of a semiconductor package according to the present invention

도 3은 본 발명의 제조과정을 개략적으로 도시한 공정별 구성도Figure 3 is a schematic configuration diagram showing the manufacturing process of the present invention by process

도 4는 본 발명의 제조공정 순서도4 is a manufacturing process flow chart of the present invention

도 5는 본 발명의 다른 실시예5 is another embodiment of the present invention

도 6은 본 발명의 또다른 실시예Figure 6 is another embodiment of the present invention

(도면의 주요부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)

1 : 회로기판 2 : 반도체칩1: circuit board 2: semiconductor chip

3 : 회로패턴 4 : 와이어3: circuit pattern 4: wire

5 : 컴파운드수지 6 : 솔더볼5: compound resin 6: solder ball

10 : 회로기판 11 : 슬롯홀10: circuit board 11: slot hole

21 : 제1반도체칩 22 : 제2반도체칩21: first semiconductor chip 22: second semiconductor chip

30 : 접착제 40 : 메탈시트(또는 퍼머넌트테이프)30: adhesive 40: metal sheet (or permanent tape)

50 : 보강제 60 : 히트싱크50: reinforcing agent 60: heat sink

상기와 같은 목적을 달성하기 위한 본 발명의 반도체패키지는 다음과 같은 구조적인 특징과 방법적인 특징을 제공한다.The semiconductor package of the present invention for achieving the above object provides the following structural features and method features.

반도체패키지를 구성함에 있어서, 패키지의 상단에 위치하는 제1반도체칩 (21)과, 상기 제1반도체칩(21)에 부착되며 상기 제1반도체칩(22)보다 크기가 작은 제2반도체칩(22)과, 상기 제2반도체칩(22)의 표면에 부착되며 다수의 슬롯홀(11)이 천공된 회로기판(10)과, 상기 회로기판(10)의 슬롯홀(11)을 통하여 회로기판(10)상의 회로패턴(3)과 제1·제2반도체칩(21)(22)을 전기적으로 연결해 주는 와이어(4)와, 상기 제1, 제2 반도체패키지(21)(22)와 와이어(4) 연결 부분을 봉합하는 컴파운드수지(5; 봉지제)와, 상기 회로기판(10)에 융착되어 입출력단자 기능을 수행하는 다수의 솔더볼(6)을 포함하여서 구성되는 것을 특징으로 하며,In constructing a semiconductor package, a first semiconductor chip 21 positioned at an upper end of a package and a second semiconductor chip attached to the first semiconductor chip 21 and smaller in size than the first semiconductor chip 22 ( 22), a circuit board 10 attached to the surface of the second semiconductor chip 22 and having a plurality of slot holes 11 drilled therethrough, and a circuit board through the slot holes 11 of the circuit board 10. A wire 4 electrically connecting the circuit pattern 3 on the top surface 10 with the first and second semiconductor chips 21 and 22, and the first and second semiconductor packages 21 and 22 and the wire. (4) characterized in that it comprises a compound resin (5; encapsulant) for sealing the connection portion, and a plurality of solder balls (6) fused to the circuit board 10 to perform the input and output terminal function,

상기 반도체패키지를 제조함에 있어서, 다수의 슬롯홀(11)이 천공된 회로기판(10) 위에 제1반도체칩(21)이 부착된 제2반도체칩(22)을 부착하는 반도체칩부착단계와, 상기 회로기판(10)에 천공된 슬롯홀(11)에 와이어(4)를 통과시켜 회로기판 (10)상에 인쇄된 회로패턴(3)과 제1·제2반도체칩(21)(22)을 전기적으로 연결해 주는 와이어본딩단계와, 상기 제1·제2 반도체패키지(21)(2) 및 와이어(4) 연결부분을 외부환경으로부터 보호하기 위해 컴파운드수지(5; 봉지제)로 봉합하는 봉지단계와, 상기 회로기판(10)에 입출력단자의 기능을 수행하는 솔더볼(6)을 다수 융착하는 솔더볼부착단계를 포함하여서 제조되는 것을 특징으로 한다.In the manufacturing of the semiconductor package, the semiconductor chip attaching step of attaching the second semiconductor chip 22 attached with the first semiconductor chip 21 on the circuit board 10 in which the plurality of slot holes 11 are drilled; The circuit pattern 3 and the first and second semiconductor chips 21 and 22 printed on the circuit board 10 by passing the wires 4 through the slot holes 11 bored in the circuit board 10. Wire bonding step of electrically connecting the first and second semiconductor packages 21 and 2 and the sealing portion of the wire 4 to be sealed with a compound resin 5 (encapsulation agent) to protect the environment from the external environment. And a solder ball attaching step of fusion bonding a plurality of solder balls 6 serving as input / output terminals to the circuit board 10.

따라서, 본 발명에 의하면 반도체패키지의 두께 및 사이즈를 크게 증가시키지 않으면서 많은 입출력단자수를 확보할 수 있고, 나아가 구조의 다양화를 통한 고품격의 반도체패키지를 제공하는 효과가 있다.Therefore, according to the present invention, it is possible to secure a large number of input and output terminals without significantly increasing the thickness and size of the semiconductor package, and furthermore, there is an effect of providing a high quality semiconductor package by diversifying the structure.

(실시예)(Example)

이하, 본 발명을 첨부된 비한정의 예시도면을 통해 보다 구체적으로 설명하면 다음과 같다.Hereinafter, the present invention will be described in more detail with reference to the attached non-limiting exemplary drawings.

도2는 본 발명에 의한 반도체패키지 구성도이고, 도3은 본 발명의 제조과정을 개략적으로 도시한 공정별 구성도이며, 도4는 본 발명의 제조공정 순서도를 나타낸다.FIG. 2 is a schematic diagram of a semiconductor package according to the present invention, FIG. 3 is a schematic diagram illustrating a manufacturing process of the present invention, and FIG. 4 is a flowchart illustrating a manufacturing process of the present invention.

도시한 바와 같이, 본 발명의 반도체패키지는 두 개의 반도체칩(동일 또는 이질의 반도체칩)을 적층시켜서 회로기판에 부착하고 회로기판(10)의 회로패턴(3)과 상기 두 개의 적층된 제1·제2반도체칩(21)(22)을 와이어(4)로 연결하여 반도체패키지의 크기를 크게 변화시키지 않으면서도 입출력단자수를 증대시킨 것으로,As shown, the semiconductor package of the present invention is laminated with two semiconductor chips (same or heterogeneous semiconductor chips), attached to a circuit board, the circuit pattern 3 of the circuit board 10 and the two stacked first layers. By connecting the second semiconductor chips 21 and 22 with the wires 4, the number of input / output terminals is increased without greatly changing the size of the semiconductor package.

상기 제2반도체칩(22)은 상기 제1반도체칩(21)의 크기보다 작게 구성되며, 와이어(4)가 본딩 연결되는 본딩패드가 제2반도체칩(22)의 사각면 가장자리에 형성되어 회로기판(10)에 사각형태로 천공된 슬롯홀(11)을 통하여 와이어(4)가 연결되게 된다. 하지만 경우에 따라 제2반도체칩(22)의 중앙 부위에 2열로 본딩패드를 형성하고 이와 대응되는 위치의 회로기판(10)에 슬롯홀(11)을 추가 천공하여 와이어(4)를 연결할 수도 있으나 이는 하나의 설계상 변형에 지나지 않는다 할 것이다.The second semiconductor chip 22 is configured to be smaller than the size of the first semiconductor chip 21, and a bonding pad to which the wire 4 is bonded is formed at the edge of the square surface of the second semiconductor chip 22 to form a circuit. The wire 4 is connected to the substrate 10 through a slot hole 11 formed in a rectangular shape. However, in some cases, the bonding pads may be formed in two rows at the center of the second semiconductor chip 22, and the wire 4 may be connected by additionally drilling the slot holes 11 in the circuit board 10 corresponding to the bonding pads. This is just a design variation.

상기 제1반도체칩(1)은 그 표면이 외부로 일부 노출되도록 성형되거나 또는 노출되지 않도록 매입 성형하게 되는데, 표면이 외부로 노출되도록 성형하게 되면 외부에 노출된 제1반도체칩(21)의 표면을 통해 열의 방출이 보다 쉽게 이루어져 방열성이 좋아지게 된다.The first semiconductor chip 1 is molded so that its surface is partially exposed to the outside or embedded molded so as not to be exposed. When the surface is molded to the outside, the surface of the first semiconductor chip 21 exposed to the outside is formed. Through the release of heat more easily, the heat dissipation is improved.

그리고, 본 발명에 적용되는 제1·제2반도체칩(21)(22)은 서로 같은 성질의 것을 사용할 수도 있고 또한 서로 이질의 반도체칩을 사용할 수가 있어 보다 다양한 기능의 반도체패키지를 구성할 수 있는 이점이 있는 것이다.In addition, the first and second semiconductor chips 21 and 22 to be applied to the present invention may use the same properties as each other or may use heterogeneous semiconductor chips to form a semiconductor package having various functions. There is an advantage.

상기 제1·제2반도체칩(21)(22)을 수용하는 회로기판(10)은 경박단소화를 위하여 반도체패키지의 실장업계에서 널리 알려져 있는 PCB(또는 인쇄회로필림) 재질로 구성되며, 그 표면에는 많은 수의 회로패턴(구리신호선)이 인쇄되어 있으며, 그리고 와이어(4)를 연결하기 위한 슬롯홀(11)이 일정패턴을 이루며 사각형태로 천공되어 있어 이 슬롯홀(11)을 관통하여 와이어(4)가 회로패턴(3)과 제1반도체칩(21) 및 제2반도체칩(22)을 전기적으로 연결시켜 주게 된다.The circuit board 10 accommodating the first and second semiconductor chips 21 and 22 is made of a PCB (or printed circuit film) material which is widely known in the semiconductor package mounting industry for light and small size reduction. A large number of circuit patterns (copper signal lines) are printed on the surface, and the slot holes 11 for connecting the wires 4 form a predetermined pattern and are perforated in a rectangular shape to penetrate the slot holes 11. The wire 4 electrically connects the circuit pattern 3 with the first semiconductor chip 21 and the second semiconductor chip 22.

한편, 본 발명의 반도체패키지를 구성함에 있어서 도5의 예시와 같이 반도체칩이 부착되지 아니하는 회로기판(10)의 가장자리 부분에 보강제(50)를 붙이거나 또는 히트싱크(60)를 붙여 반도체패키지의 강성을 보강하고 열방출 효과를 증대시킬 수가 있다.Meanwhile, in constructing the semiconductor package of the present invention, as shown in FIG. 5, the semiconductor package is attached to the edge of the circuit board 10 to which the semiconductor chip is not attached, or the heat sink 60 is attached. It can reinforce the stiffness and increase the heat dissipation effect.

본 발명의 반도체패키지는 다음과 같은 순서에 의해 제조된다.The semiconductor package of the present invention is manufactured in the following order.

〈반도체칩부착단계〉〈Semiconductor chip attachment step〉

다수의 슬롯홀(11)이 천공된 회로기판(10) 위에 제1반도체칩(21)이 부착된 제2반도체칩(22)을 부착하여 반도체칩을 부착하는 방법을 선택하거나, 또는 별도의 메탈시트(40; 또는 접착테이프)를 깔고 접착제(30)를 사용해 제1·제2반도체칩 (21)(22)을 부착하는 공정을 수행한다.Selecting a method of attaching a semiconductor chip by attaching a second semiconductor chip 22 having a first semiconductor chip 21 attached thereto on a circuit board 10 having a plurality of slot holes 11 formed therein, or a separate metal The sheet 40 (or adhesive tape) is laid and the first and second semiconductor chips 21 and 22 are attached using the adhesive 30.

〈와이어본딩단계〉〈Wire Bonding Step〉

회로기판(10)에 적층된 제1·제2반도체칩(21)(22)을 부착한 다음, 상기 회로기판(10)에 천공된 슬롯홀(11)에 와이어(4)를 통과시켜 회로기판 (10)상에 인쇄된 회로패턴(3)과 제1·제2반도체칩(21)(22)을 본딩 연결한다. 따라서 회로패턴(3)과 제1·제2반도체칩(21)(22)은 서로 전기적으로 연결된 상태가 된다.The first and second semiconductor chips 21 and 22 stacked on the circuit board 10 are attached to each other, and then the wire 4 is passed through the slot holes 11 drilled through the circuit board 10. The circuit pattern 3 printed on (10) and the first and second semiconductor chips 21 and 22 are bonded to each other. Therefore, the circuit pattern 3 and the first and second semiconductor chips 21 and 22 are electrically connected to each other.

〈봉지단계〉〈Envelope Phase〉

외부환경으로부터 제1·제2반도체칩(21)(22)의 회로를 보호하기 위해 컴파운드수지(5; 봉지재)로 성형하는 봉지공정을 수행한다.In order to protect the circuits of the first and second semiconductor chips 21 and 22 from the external environment, an encapsulation step of forming a compound resin 5 (encapsulation material) is performed.

즉, 최상단에 위치하는 상기 제1반도체칩(21)이 컴파운드수지(5)에 완전히 매입되도록 봉합 성형하거나, 또는 제1반도체칩(21)의 일 표면이 외부로 노출되도록 와이어(4)가 연결된 부분만을 봉합 성형하는 봉지공정을 수행한다.That is, the first semiconductor chip 21 positioned at the uppermost end may be sealed to be completely embedded in the compound resin 5, or the wire 4 may be connected to expose one surface of the first semiconductor chip 21 to the outside. An encapsulation process of suture molding only a portion is performed.

〈솔더볼부착단계〉〈Solder Ball Attaching Step〉

상기 회로기판(10)에 입출력단자의 기능을 수행하는 솔더볼(6)을 다수 융착한다.A plurality of solder balls 6 that perform a function of an input / output terminal are fused to the circuit board 10.

그러므로써 많은 수의 입출력(I/O)을 갖는 대용량의 다기능 반도체패키지가 제조되는 것이다.Therefore, a large capacity multifunctional semiconductor package having a large number of input / output (I / O) is manufactured.

이와 같이, 본 발명에 의하면 반도체패키지의 두께를 크게 증가시키지 않으면서 많은 입출력단자수를 확보할 수 있고, 나아가 구조의 다양화를 통한 고품격의 경박단소형 반도체패키지를 제공하는 효과가 있다.As described above, according to the present invention, a large number of input / output terminals can be secured without greatly increasing the thickness of the semiconductor package, and further, there is an effect of providing a high-quality thin and thin semiconductor package by diversifying the structure.

이상에서 설명한 것은 본 발명에 의한 반도체패키지 및 그 제조방법을 설명하기 위한 하나의 실시예에 불과한 것이며, 본 발명은 상기한 실시예에 한정하지 않고 이하의 청구범위에서 청구하는 본 고안의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.What has been described above is only one embodiment for explaining a semiconductor package and a method for manufacturing the same according to the present invention, the present invention is not limited to the above-described embodiment and deviates from the gist of the present invention claimed in the following claims Without this, any person having ordinary knowledge in the field of the present invention will be able to implement various changes.

Claims (5)

반도체패키지를 구성함에 있어서, 패키지의 상단에 위치하는 제1반도체칩 (21)과, 상기 제1반도체칩(21)에 부착되며 상기 제1반도체칩(22)보다 크기가 작은 제2반도체칩(22)과, 상기 제2반도체칩(22)의 표면에 부착되며 다수의 슬롯홀(11)이 천공된 회로기판(10)과, 상기 회로기판(10)이 슬롯홀(11)을 통하여 회로기판(10)상의 회로패턴(3)과 제1·제2반도체칩(21)(22)을 전기적으로 연결해 주는 와이어(4)와, 상기 제1·제2반도체패키지(21)(22) 및 와이어(4)가 연결된 부분을 봉합하는 컴파운드수지(5; 봉지제)와, 상기 회로기판(10)에 융착되어 입출력단자 기능을 수행하는 다수의 솔더볼(6)을 포함하여서 구성되는 것을 특징으로 하는 반도체패키지.In constructing a semiconductor package, a first semiconductor chip 21 positioned at an upper end of a package and a second semiconductor chip attached to the first semiconductor chip 21 and smaller in size than the first semiconductor chip 22 ( 22), a circuit board 10 attached to the surface of the second semiconductor chip 22 and having a plurality of slot holes 11 perforated, and the circuit board 10 through the slot holes 11. A wire 4 for electrically connecting the circuit pattern 3 on the top surface 10 and the first and second semiconductor chips 21 and 22, the first and second semiconductor packages 21 and 22 and the wires. A semiconductor comprising a compound resin 5 (sealing agent) for sealing a portion to which 4 is connected, and a plurality of solder balls 6 fused to the circuit board 10 to perform an input / output terminal function. package. 제1항에 있어서 반도체칩이 부착되지 아니한 회로기판(10)의 상면에 보강제 (50)를 부착함을 특징으로 하는 반도체패키지.The semiconductor package according to claim 1, wherein a reinforcing agent (50) is attached to an upper surface of the circuit board (10) to which the semiconductor chip is not attached. 제1항에 있어서 반도체칩이 부착되지 아니한 회로기판(10)의 상면에 열방출을 위한 히트싱크(60)를 부착함을 특징으로 하는 반도체패키지.The semiconductor package according to claim 1, wherein a heat sink (60) for heat dissipation is attached to an upper surface of the circuit board (10) to which the semiconductor chip is not attached. 상기 반도체패키지를 제조함에 있어서, 다수의 슬롯홀(11)이 천공된 회로기판(10) 위에 제1반도체칩(21)이 부착된 제2반도체칩(22)을 부착하는 반도체칩부착단계와, 상기 회로기판(10)에 천공된 슬롯홀(11)에 와이어(4)를 통과시켜 회로기판 (10)상에 인쇄된 회로패턴(3)과 제1·제2반도체칩(21)(22)을 전기적으로 연결해 주는 와이어본딩단계와, 상기 제1·제2반도체패키지(21)(22) 및 와이어(4) 연결부분을 외부환경으로부터 보호하기 위해 컴파운드수지(5; 봉지제)로 봉합하는 봉지단계와, 상기 회로기판(10)에 입출력단자의 기능을 수행하는 솔더볼(6)을 다수 융착하는 솔더볼부착단계를 포함하여서 제조되는 것을 특징으로 하는 반도체패키지 제조방법.In the manufacturing of the semiconductor package, the semiconductor chip attaching step of attaching the second semiconductor chip 22 attached with the first semiconductor chip 21 on the circuit board 10 in which the plurality of slot holes 11 are drilled; The circuit pattern 3 and the first and second semiconductor chips 21 and 22 printed on the circuit board 10 by passing the wires 4 through the slot holes 11 bored in the circuit board 10. A wire bonding step of electrically connecting the first and second semiconductor packages 21 and 22 and the wires 4 to the connecting portion and sealing the compound resin 5 with an encapsulation agent to protect the external parts from the external environment. And a solder ball attaching step of fusion bonding a plurality of solder balls (6) performing a function of an input / output terminal to the circuit board (10). 제 4항에 있어서, 메탈시트(40) 위에 적층된 제1·제2반도체칩(21)(22)을 부착하고, 상기 제2반도체칩(22)에 회로기판(10)을 부착하는 방법에 의해 제조되는 것을 특징으로 하는 반도체패키지의 제조방법.The method according to claim 4, wherein the first and second semiconductor chips (21) and (22) are stacked on the metal sheet (40), and the circuit board (10) is attached to the second semiconductor chip (22). Method for manufacturing a semiconductor package, characterized in that the manufacturing.
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